[all-commits] [llvm/llvm-project] 3e30a8: [AMDGPU] Add MemoryPipeline scheduling to Coexec s...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/users/jebyrnes/FenceWaitRebase2
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e30a813c9cbb0636e29e0762c69613eeb372818
      https://github.com/llvm/llvm-project/commit/3e30a813c9cbb0636e29e0762c69613eeb372818
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  [AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5


  Commit: a9ec5a596479216cfe37b03bc8a63de6ecd5efc4
      https://github.com/llvm/llvm-project/commit/a9ec5a596479216cfe37b03bc8a63de6ecd5efc4
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h

  Log Message:
  -----------
  Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484


  Commit: df70b43d7aa8c251c35f24f6f64b3a8110522cf7
      https://github.com/llvm/llvm-project/commit/df70b43d7aa8c251c35f24f6f64b3a8110522cf7
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h

  Log Message:
  -----------
  Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b


  Commit: b229698af73dd669e6d053b8f6274d44f65d4a03
      https://github.com/llvm/llvm-project/commit/b229698af73dd669e6d053b8f6274d44f65d4a03
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp

  Log Message:
  -----------
  Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f


  Commit: 8b730a5d66c217eed98ceb445808a1d8200464d6
      https://github.com/llvm/llvm-project/commit/8b730a5d66c217eed98ceb445808a1d8200464d6
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp

  Log Message:
  -----------
  Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133


  Commit: bf750e8818691e68878ccce1063add01cd5a79fd
      https://github.com/llvm/llvm-project/commit/bf750e8818691e68878ccce1063add01cd5a79fd
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Adrress comments from https://github.com/llvm/llvm-project/pull/188658

Change-Id: Ia94c567a753168c1ffa16dc5d91195e7dd0ba044


  Commit: 428e06882fb8e997c8f0e1b759622924da12d4ff
      https://github.com/llvm/llvm-project/commit/428e06882fb8e997c8f0e1b759622924da12d4ff
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Update tests

Change-Id: Ided5a4e6968d4670d1fd09bcb327a75a25273d4e


Compare: https://github.com/llvm/llvm-project/compare/aa5ebd8a97b7...428e06882fb8

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