[all-commits] [llvm/llvm-project] b76d08: [RISCV] Factor out common scheduling model part be...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b76d08a8fc46684c43728eb3c097718d0b6c00b7
      https://github.com/llvm/llvm-project/commit/b76d08a8fc46684c43728eb3c097718d0b6c00b7
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    A llvm/lib/Target/RISCV/RISCVSchedSiFive8.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td

  Log Message:
  -----------
  [RISCV] Factor out common scheduling model part between SiFive P400 and P500. NFCI (#199796)

This is the first part a patch series that tries to factor out common
bits from the SiFiveP400, SiFiveP500, and the SiFiveP600 scheduling
models.

This PR contains the related changes on the SiFiveP400 and SiFiveP500
models

NFCI.

---------

Co-authored-by: Craig Topper <craig.topper at sifive.com>



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