[all-commits] [llvm/llvm-project] da4e5c: [SCEV] Canonicalise round-up idiom when some bits ...

[Oliver Stannard via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: da4e5cc928c8f8000643e48bc2790b51927eeac6
      https://github.com/llvm/llvm-project/commit/da4e5cc928c8f8000643e48bc2790b51927eeac6
  Author: Oliver Stannard <oliver.stannard at arm.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Analysis/ScalarEvolution.cpp
    A llvm/test/Analysis/ScalarEvolution/rounding-demanded-bits.ll
    A llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-known-bits.ll

  Log Message:
  -----------
  [SCEV] Canonicalise round-up idiom when some bits known (#197126)

Since #174380, instcombine can clear some set bits in the added constant
in expressions like this, when A has some known-clear low order bits.
  (A + 15) & ~15

This transformation is valid, but can make it harder for later passes to
recognise this idiom for rounding up to a power of 2. This is causing
the ARM MVE tail predication pass to fail on loops with a trip count
which is a multiple of a small power of 2.

The fix is to reverse the transformation when building SCEV expressions,
canonicalising to always use the largest valid value for the added
constant.

Alive proofs:
https://alive2.llvm.org/ce/z/hhndoW
https://alive2.llvm.org/ce/z/_JYVat



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications