[all-commits] [llvm/llvm-project] 6619c8: [RISCV] Fix incorrect CM.MVSA01/QC_CM_MVSA01 gener...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6619c82f729487ada200a074c72f7260511bb23e
      https://github.com/llvm/llvm-project/commit/6619c82f729487ada200a074c72f7260511bb23e
  Author: Sudharsan Veeravalli <svs at qti.qualcomm.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
    A llvm/test/CodeGen/RISCV/move-merge-zdinx-mvsa-regression.mir

  Log Message:
  -----------
  [RISCV] Fix incorrect CM.MVSA01/QC_CM_MVSA01 generation with Zdinx (#200000)

The `RISCVMoveMerger` pass was incorrectly forming
`CM_MVSA01/QC_CM_MVSA01` when `Zdinx` was enabled. The pass attempted CM
merge for copy pairs even when the first copy was not an `a0/a1-based`
CM candidate.

Fix by only running `findMatchingInst` when the current copy is a valid
CM candidate.



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