[all-commits] [llvm/llvm-project] 2b3bc0: [AMDGPU] Use shorter form for i16 operands (#198005)

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b3bc03b5ef00e7eaa245420ca981c700e1c05c4
      https://github.com/llvm/llvm-project/commit/2b3bc03b5ef00e7eaa245420ca981c700e1c05c4
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2026-05-27 (Wed, 27 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float.ll
    M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/imm16.ll
    M llvm/test/CodeGen/AMDGPU/immv216.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.ll
    M llvm/test/CodeGen/AMDGPU/lround.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll
    M llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
    M llvm/test/MC/AMDGPU/gfx12_asm_sopc.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop1-fake16.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
    M llvm/test/MC/AMDGPU/gfx13_asm_sopc.s
    M llvm/test/MC/AMDGPU/gfx13_asm_vop1.s
    M llvm/test/MC/AMDGPU/gfx13_asm_vop1_t16_promote.s
    M llvm/test/MC/AMDGPU/gfx13_asm_vop3-fake16.s
    M llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
    M llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1-fake16.s
    M llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1.s
    M llvm/test/MC/AMDGPU/literals.s
    M llvm/test/MC/AMDGPU/vop3-gfx10.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3cx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_salu_float.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3cx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3c.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3cx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3c.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3cx.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx.txt

  Log Message:
  -----------
  [AMDGPU] Use shorter form for i16 operands (#198005)

For 16-bit operands an inline constant is zero extended
which in particular allows to use FP constants. These
will have 16 bits of zeroes in the high half and FP16
value in the low 16 bits.

The patch changes semantics of the FP literal argument
used in i16 context in the asm parser to fp16.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications