[all-commits] [llvm/llvm-project] 358f5e: [RISCV][P-ext] Add missing let Inst{31} = 0b0 to R...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 358f5e770361c0512b7f6e4027a3a674bb1fa654
      https://github.com/llvm/llvm-project/commit/358f5e770361c0512b7f6e4027a3a674bb1fa654
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-05-27 (Wed, 27 May 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td

  Log Message:
  -----------
  [RISCV][P-ext] Add missing let Inst{31} = 0b0 to RVPPairShift_rr. (#199885)

This bit was accidentally left unset. I think this means we might have
treated this bit as a don't care for the disassembler could disassemble
some invalid encodings to these instructions. I didn't check the opcode
map closely enough to confirm this.



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