[all-commits] [llvm/llvm-project] 6cb00b: [Hexagon] Fix up vector predicate before compressi...

[Alexey Karyakin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cb00b6c344cb6d61688cc993b15ee531dbfd0e4
      https://github.com/llvm/llvm-project/commit/6cb00b6c344cb6d61688cc993b15ee531dbfd0e4
  Author: Alexey Karyakin <akaryaki at qti.qualcomm.com>
  Date:   2026-05-27 (Wed, 27 May 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
    M llvm/test/CodeGen/Hexagon/inst_masked_store_bug1.ll
    M llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll

  Log Message:
  -----------
  [Hexagon] Fix up vector predicate before compressing it for bitcast (#199283)

In v64i1 vector Predicate, each i1 is represented by 2 bits of predicate
register. A predicate register needs to be fixed before we compress it.

Signed-off-by: Alexey Karyakin <akaryaki at qti.qualcomm.com>
Co-authored-by: Ikhlas Ajbar <iajbar at quicinc.com>



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