[all-commits] [llvm/llvm-project] 13f9f4: [AMDGPU] Emit entry function Dwarf CFI (#183152)

[Scott Linder via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 13f9f468dcf8e89d232f28304fa595bf0efbf84b
      https://github.com/llvm/llvm-project/commit/13f9f468dcf8e89d232f28304fa595bf0efbf84b
  Author: Scott Linder <scott.linder at amd.com>
  Date:   2026-05-26 (Tue, 26 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIFrameLowering.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
    M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll
    A llvm/test/CodeGen/AMDGPU/debug-frame.ll
    M llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
    A llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
    M llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
    M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
    M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
    M llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
    M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
    M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
    M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
    M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir

  Log Message:
  -----------
  [AMDGPU] Emit entry function Dwarf CFI (#183152)

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>



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