[all-commits] [llvm/llvm-project] 714608: [AArch64][DAG] Use getSetCCResultType in PromoteSE...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7146087fb49476055704f92e24295c549c89fa21
      https://github.com/llvm/llvm-project/commit/7146087fb49476055704f92e24295c549c89fa21
  Author: David Green <david.green at arm.com>
  Date:   2026-05-26 (Tue, 26 May 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
    M llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll

  Log Message:
  -----------
  [AArch64][DAG] Use getSetCCResultType in PromoteSETCC (#198320)

During the promotion of a v16bf16 vector setcc with 256 bit sve, a
v16i16 setcc(v16f32) is created, that gets legalized to a v8i16
setcc(v8f32), which trips up an assert in the aarch64 custom lowering to
vector registers. It could be solved elsewhere but this addresses it by
making sure that when the f32 setcc is created, the result type matches
getSetCCResultType.

The mvn+xtn vs xtn+mvn is mostly benign, and should both probably be a
subhn if it can be done without causing regressions.



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