[all-commits] [llvm/llvm-project] 088dd2: [AMDGPU][True16] Add regbank combiner cases to fix...

[Domenic Nutile via All-commits]

  Branch: refs/heads/users/saxlungs/true16-gisel-16bit-extloads-combiner
  Home:   https://github.com/llvm/llvm-project
  Commit: 088dd28f866fc706c6167fa2ff2a455abaad1c3c
      https://github.com/llvm/llvm-project/commit/088dd28f866fc706c6167fa2ff2a455abaad1c3c
  Author: Domenic Nutile <domenic.nutile at gmail.com>
  Date:   2026-05-26 (Tue, 26 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll

  Log Message:
  -----------
  [AMDGPU][True16] Add regbank combiner cases to fix regression around G_SEXTLOAD


  Commit: 4af6b1eac659edafd5cefbeb7d76d47b8fd9c42f
      https://github.com/llvm/llvm-project/commit/4af6b1eac659edafd5cefbeb7d76d47b8fd9c42f
  Author: Domenic Nutile <domenic.nutile at amd.com>
  Date:   2026-05-26 (Tue, 26 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll

  Log Message:
  -----------
  PR feedback, fix tests


Compare: https://github.com/llvm/llvm-project/compare/a97f71f416ab...4af6b1eac659

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