[all-commits] [llvm/llvm-project] c618e1: [MLIR][NVVM] Add `nvvm.divf` Op (#198744)

[Varad Rahul Kamthe via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c618e112145fbbbe7ab14ab202f8626703920b96
      https://github.com/llvm/llvm-project/commit/c618e112145fbbbe7ab14ab202f8626703920b96
  Author: Varad Rahul Kamthe <133588066+varadk27 at users.noreply.github.com>
  Date:   2026-05-26 (Tue, 26 May 2026)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
    M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
    A mlir/test/Target/LLVMIR/nvvm/divf/divf.mlir
    A mlir/test/Target/LLVMIR/nvvm/divf/divf_invalid.mlir

  Log Message:
  -----------
  [MLIR][NVVM] Add `nvvm.divf` Op (#198744)

Adds the `nvvm.divf` NVVM dialect op covering all 16 PTX `div` forms via attribute-driven selection:

- Default (`approx = false, full = false`): IEEE-compliant rounded divide (`div.<RM>[.ftz].{f32,f64}`), 12 forms -- requires `rnd` ∈ `{rn, rm, rp, rz}`; supports f32 and f64 (f64 does not accept `ftz`).
- `approx = true`: fast hardware approximation (`div.approx[.ftz].f32`), 2 forms -- f32 only.
- `full = true`: full-range approximation (`div.full[.ftz].f32`), 2 forms -- f32 only.



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