[all-commits] [llvm/llvm-project] 68dfda: [AMDGPU] Optimize fneg and fsub with packed fp16 o...

[Changpeng Fang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 68dfda06dfd20184d06e8ac82cb6eb96fd8f122e
      https://github.com/llvm/llvm-project/commit/68dfda06dfd20184d06e8ac82cb6eb96fd8f122e
  Author: Changpeng Fang <changpeng.fang at amd.com>
  Date:   2026-05-12 (Tue, 12 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
    A llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
    M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll

  Log Message:
  -----------
  [AMDGPU] Optimize fneg and fsub with packed fp16 ops (#196659)

The work optimize fneg and fsub when packed half math instructions are supported.
  On global isel path, for wider vectors of G_FSUB with element type of f16, we should
split them to v2f16 for v_pk_add_f16 to be selected.
  On SelectionDAG path, we make FNEG legal, and also make sure to split wider vectors
to v2f16. In this way, we can fold fneg into the source modifiers for packed half ops.



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