[all-commits] [llvm/llvm-project] b50027: [𝘀𝗽𝗿] initial version

[Alexey Bataev via All-commits]

  Branch: refs/heads/users/alexey-bataev/spr/slp-enable-full-non-power-of-2-vectorization-by-default
  Home:   https://github.com/llvm/llvm-project
  Commit: b50027fc3b227d3d56c573e075fe19cfb24e6828
      https://github.com/llvm/llvm-project/commit/b50027fc3b227d3d56c573e075fe19cfb24e6828
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2026-05-10 (Sun, 10 May 2026)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll
    M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/scalable-vector.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
    M llvm/test/Transforms/SLPVectorizer/RISCV/horizontal-list.ll
    M llvm/test/Transforms/SLPVectorizer/RISCV/reduced-value-repeated-and-vectorized.ll
    M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
    M llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-trunc.ll
    M llvm/test/Transforms/SLPVectorizer/X86/bool-mask.ll
    M llvm/test/Transforms/SLPVectorizer/X86/buildvector-store-chains.ll
    M llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
    M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
    M llvm/test/Transforms/SLPVectorizer/X86/entries-shuffled-diff-sizes.ll
    M llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
    M llvm/test/Transforms/SLPVectorizer/X86/gather-extractelements-different-bbs.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
    M llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
    M llvm/test/Transforms/SLPVectorizer/X86/multi_user.ll
    M llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
    M llvm/test/Transforms/SLPVectorizer/X86/parent-node-split-non-schedulable.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction-same-vals.ll
    M llvm/test/Transforms/SLPVectorizer/X86/rgb_phi.ll
    M llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
    M llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
    M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
    M llvm/test/Transforms/SLPVectorizer/logical-ops-poisonous-repeated.ll
    M llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll
    M llvm/test/Transforms/SLPVectorizer/reduced-gathered-vectorized.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.7



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