[all-commits] [llvm/llvm-project] 9c95f3: [CIR][AArch64] Lower NEON vuzp intrinsics (#195591)

[Jiahao Guo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9c95f3765930b964d2a42c3f08dae2fd281cc49b
      https://github.com/llvm/llvm-project/commit/9c95f3765930b964d2a42c3f08dae2fd281cc49b
  Author: Jiahao Guo <eoonguo at gmail.com>
  Date:   2026-05-10 (Sun, 10 May 2026)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
    M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
    M clang/test/CodeGen/AArch64/neon-perm.c
    M clang/test/CodeGen/AArch64/neon/perm.c

  Log Message:
  -----------
  [CIR][AArch64] Lower NEON vuzp intrinsics (#195591)

### Summary

part of : https://github.com/llvm/llvm-project/issues/185382

lower `vuzp` intrinsics in:
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#unzip-elements

this is a follow up : https://github.com/llvm/llvm-project/pull/195527

Lower `NEON::BI__builtin_neon_vuzp_v` and
`NEON::BI__builtin_neon_vuzpq_v`in CIRGenBuiltinAArch64.cpp by porting
by porting the existing incubator
logic(clangir/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp) : two
bitcasts on the input vectors,two rounds of cir.vec.shuffle generating
the deinterleave (even/odd) shuffle patterns with indices 2*i+vi, each
stored via ptr_stride on the sret base pointer.



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