[all-commits] [llvm/llvm-project] 2b0641: [MSP430] Compute c+1 at the operand bit width in E...

[Byeongjee Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b0641473766a304bd17d3d07264c6dd2047d897
      https://github.com/llvm/llvm-project/commit/2b0641473766a304bd17d3d07264c6dd2047d897
  Author: Byeongjee Kang <byeongjee.kang at gmail.com>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
    A llvm/test/CodeGen/MSP430/cmp-imm-high-bit.ll

  Log Message:
  -----------
  [MSP430] Compute c+1 at the operand bit width in EmitCMP (#195892)

EmitCMP folds `c CMP rhs` into `rhs CMP' c+1` for four condition codes.
The `c+1` must wrap modulo the i16 operand width, but the current code
does `DAG.getConstant(C->getSExtValue() + 1, dl, MVT::i16)`:
sign-extending to `int64_t`, adding there, then handing the result to
the unsigned
`getConstant(uint64_t, ..., MVT::i16)` overload. 

For constants with bit 15 set the negative `int64_t` is reinterpreted as
a huge `uint64_t`, which
trips the `isUIntN(16, val)` assertion in the APInt constructor under
`LLVM_ENABLE_ASSERTIONS` and yields an APInt with non-zero bits past its
declared width otherwise.

Switching to `DAG.getSignedConstant(C->getSExtValue() + 1, ...)` routes
through the signed `APInt` constructor, which checks `isIntN(16, val)`
and accepts the negative `c+1` produced when the high bit is set. The
four EmitCMP fold branches (SETUGE, SETULT, SETGE, SETLT) are updated
identically.



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