[all-commits] [llvm/llvm-project] 706241: [Hexagon] Correctly split masked loads/stores afte...

[Alexey Karyakin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 706241344808fdcb1c8ef58383c5b2599884779e
      https://github.com/llvm/llvm-project/commit/706241344808fdcb1c8ef58383c5b2599884779e
  Author: Alexey Karyakin <akaryaki at qti.qualcomm.com>
  Date:   2026-05-06 (Wed, 06 May 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
    A llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-multi.ll

  Log Message:
  -----------
  [Hexagon] Correctly split masked loads/stores after widening (#190689)

Non-power of 2 masked loads and stores are first widened to a power of 2
size. If the original vector was larger than the single HVX register
size, they become multiples of the double HVX register size (e.g.
v64f32, v128f32). Since double vector types are legal but do not support
masked operations, they are split during custom lowering.

MemoryVT is not changed during widening and the original code assumed
that MemoryVT is the same as the operand type and always equal to the
double HVX register size.

For example, @llvm.masked.store.v80f32.p0 is first widened to v128f32,
then split into two v64f32 (MemoryVT = v64f32 and v16f32). The first
half was lowered correctly but the second one could not be split due to
the unexpected v16f32 MemoryVT.



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