[all-commits] [llvm/llvm-project] a849bf: [NVPTX] Add commutativity to SETP instructions to ...
modiking via All-commits
all-commits at lists.llvm.org
Tue May 5 16:49:56 PDT 2026
Branch: refs/heads/users/modiking/nvptx-setp-predicate-inversion
Home: https://github.com/llvm/llvm-project
Commit: a849bfcc1cdb6182594ed0ac78691dc62c52298c
https://github.com/llvm/llvm-project/commit/a849bfcc1cdb6182594ed0ac78691dc62c52298c
Author: root <mmo at nvidia.com>
Date: 2026-05-05 (Tue, 05 May 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll
Log Message:
-----------
[NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates
Inverted predicates can be used freely in PTX. If we can invert a
predicate and CSE the generating instruction we can save calculating
the inverse.
Teach the NVPTX commuteInstructionImpl that SETP instructions can be
inverted to allow CSEing with previous SETP that match the inverted
form. This also inverts the branch users of the predicate to maintain
correctness.
Currently only allow the SETP inversion if all users are branches.
Future work can extend this to sel and not instructions.
Made-with: Cursor
Commit: ab563e9ba017d51f8eee95aaf2c0d74e9e9f3cdc
https://github.com/llvm/llvm-project/commit/ab563e9ba017d51f8eee95aaf2c0d74e9e9f3cdc
Author: Modi Mo <mmo at nvidia.com>
Date: 2026-05-05 (Tue, 05 May 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-rollback.mir
Log Message:
-----------
update rollback logic and add test exercising it
Commit: de26666a99e7083816b391d94266b714d2abab1e
https://github.com/llvm/llvm-project/commit/de26666a99e7083816b391d94266b714d2abab1e
Author: Modi Mo <mmo at nvidia.com>
Date: 2026-05-05 (Tue, 05 May 2026)
Changed paths:
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
M llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll
R llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll
A llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
Log Message:
-----------
Move inversion/no inversion tests to one file. Fixup issue in machine-cse-predicate-inversion-multiple-users.ll
Commit: 896c96ae73c104d89f1a1d28f553808463faefae
https://github.com/llvm/llvm-project/commit/896c96ae73c104d89f1a1d28f553808463faefae
Author: Modi Mo <mmo at nvidia.com>
Date: 2026-05-05 (Tue, 05 May 2026)
Changed paths:
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
Log Message:
-----------
move cmp modes into td and update users
Commit: 08d120207dba845029f8c95a8a732203860071c9
https://github.com/llvm/llvm-project/commit/08d120207dba845029f8c95a8a732203860071c9
Author: modiking <mmo at nvidia.com>
Date: 2026-05-05 (Tue, 05 May 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
Log Message:
-----------
Update NVPTXInstrInfo.td
Commit: 4c1d0ee3ecea2fe7abaf294d897796f6e8129dbe
https://github.com/llvm/llvm-project/commit/4c1d0ee3ecea2fe7abaf294d897796f6e8129dbe
Author: root <mmo at nvidia.com>
Date: 2026-05-05 (Tue, 05 May 2026)
Changed paths:
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
Log Message:
-----------
Revert "move cmp modes into td and update users"
This reverts commit 5950d9fcd6b2053e71929972b89cc983ce2cccaa, restoring
the hand-written PTXCmpMode enum in NVPTX.h and the switch-based
implementations of invertIntegerCmpMode, invertScalarFloatCmpMode,
NVPTXInstPrinter::printCmpMode and NVPTXDAGToDAGISel::getPTXCmpMode.
The TableGen GenericTable migration consolidated the comparison-mode
data but at the cost of an extra .inc file, an ODR-driven split between
NVPTXCodeGen and NVPTXDesc, and indirection through a generated lookup
where the local switches were already self-contained. Reverting until a
broader cleanup of NVPTX::PTXCmpMode is taken on as part of a larger
refactor.
Co-authored-by: Cursor <cursoragent at cursor.com>
Compare: https://github.com/llvm/llvm-project/compare/b873728d9ba0...4c1d0ee3ecea
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