[all-commits] [llvm/llvm-project] 99040b: [PowerPC] Further refactor atomic loads (#194445)

[Kai Nacke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 99040b6ea9c17c8bd3ab5dc127a98db0585d70ea
      https://github.com/llvm/llvm-project/commit/99040b6ea9c17c8bd3ab5dc127a98db0585d70ea
  Author: Kai Nacke <kai.peter.nacke at ibm.com>
  Date:   2026-05-05 (Tue, 05 May 2026)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td

  Log Message:
  -----------
  [PowerPC] Further refactor atomic loads (#194445)

Depending on the availability of the word-part feature, different code
is generated for 1 and 2 byte atomic loads. This change moves the
decision to use the word-part feature from C++ into TableGen patterns.
This is done via:

- move code from `EmitPartwordAtomicBinary()` into new function
'signExtendOperandIfUnknown()'
- decouple functions `EmitPartwordAtomicBinary()` and
`EmitAtomicBinary()`
- remove the size from the name of the pseudo instructions; instead,
introduce a pseudo instruction which is used in case the word-part
feature is missing
 - update the handling of the pseudo instruction insertion accordingly

A side effect of this change is the implementation requires 11 pseudo
instructions less.



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