[all-commits] [llvm/llvm-project] 239ca8: [IR] Add elementwise modifier to atomicrmw (#189517)
Yonah Goldberg via All-commits
all-commits at lists.llvm.org
Mon May 4 20:01:09 PDT 2026
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 239ca8d6c13a5c05a2363247e02edf29d2f253a2
https://github.com/llvm/llvm-project/commit/239ca8d6c13a5c05a2363247e02edf29d2f253a2
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-05-04 (Mon, 04 May 2026)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/Instructions.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Assembler/atomic.ll
A llvm/test/Assembler/invalid-atomicrmw-elementwise.ll
A llvm/test/Bitcode/atomicrmw-elementwise.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/unittests/Analysis/AliasAnalysisTest.cpp
M llvm/unittests/IR/VerifierTest.cpp
Log Message:
-----------
[IR] Add elementwise modifier to atomicrmw (#189517)
This PR implements the IR side modifications of [[RFC] Add elementwise
modifier to atomicrmw](https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomicrmw/90134).
Design Decisions:
- In the IR, the current atomicrmw record layout looks like: [ptrty,
ptr, valty, val, operation, vol, ordering, syncscope, align]. To encode
elementwise, I decided to pack it into the operation field, which also
contains the math op (i.e. fadd, fmin, add etc...). I could have changed
the record structure, but that would be slightly more complicated.
- elementwise vector atomics can be vectors of integers because we can always scalarize legally
- elementwise vector atomics need to have power of 2 size. We can potentially remove this restriction later.
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