[all-commits] [llvm/llvm-project] bda001: [MLIR][AMDGPU] Add amdgpu.global_transpose_load op...

[Nirvedh Meshram via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bda0016aa2b43f0817dddbd790ce4abd3df22e99
      https://github.com/llvm/llvm-project/commit/bda0016aa2b43f0817dddbd790ce4abd3df22e99
  Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
  Date:   2026-05-04 (Mon, 04 May 2026)

  Changed paths:
    M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
    M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
    M mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
    A mlir/test/Conversion/AMDGPUToROCDL/global_transpose_load.mlir
    M mlir/test/Dialect/AMDGPU/invalid.mlir
    M mlir/test/Dialect/AMDGPU/ops.mlir

  Log Message:
  -----------
  [MLIR][AMDGPU] Add amdgpu.global_transpose_load op for gfx1200+ global memory transpose loads (#195287)

Adds a new `amdgpu.global_transpose_load` op to the AMDGPU dialect that
wraps the `global_load_tr` family of instructions introduced in RDNA4
(gfx1250+). Each thread reads a column of a matrix from global memory
and receives the corresponding transposed row in its result register.

The op is kept separate from the existing `amdgpu.transpose_load` (which
targets LDS via `ds_read_tr` on gfx950+) because the two variants target
different GPU architecture families, have different chipset
requirements, and differ in their valid (element size, num elements)
combinations — in particular the 16-bit case produces a 128-bit
(8-element) result via `global_load_tr.b128` rather than the 64-bit
(4-element) result from `ds_read_tr16.b64`.

Lowering to the existing ROCDL `global.load.tr{4,6,.}.b{64,96,128}`
intrinsics added for gfx1200+.

---------

Signed-off-by: Nirvedh Meshram <nirvedh at gmail.com>
Co-authored-by: Claude Sonnet 4 (1M context) <noreply at anthropic.com>



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications