[all-commits] [llvm/llvm-project] aee55a: [X86] combineMinMaxReduction - match any minmax re...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aee55a87dd79c5167dd3b71a2a1376bef1235276
      https://github.com/llvm/llvm-project/commit/aee55a87dd79c5167dd3b71a2a1376bef1235276
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2026-05-01 (Fri, 01 May 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
    M llvm/test/CodeGen/X86/vector-extract-last-active.ll
    M llvm/test/CodeGen/X86/vector-reduce-smax.ll
    M llvm/test/CodeGen/X86/vector-reduce-smin.ll
    M llvm/test/CodeGen/X86/vector-reduce-umax.ll
    M llvm/test/CodeGen/X86/vector-reduce-umin.ll

  Log Message:
  -----------
  [X86] combineMinMaxReduction - match any minmax reduction to a legal scalar (#195261)

Further relaxation of the VECREDUCE minmax folds - recognise any
>=128-bit vector that reduces to a legal scalar.

Adds custom ops for more VECREDUCE types (inc vXi32/vXi64 types)

Remaining issues are sub-128-bit vector reductions (unnecessary padding
with neutral elements) and handling of i64 types on 32-bit targets - I'm
working on fixes for both of these.



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