[all-commits] [llvm/llvm-project] 9f7209: [VPlan] Include wide IVs with NUW as monotonic in ...
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Thu Apr 30 04:13:59 PDT 2026
Branch: refs/heads/users/kparzysz/dsa-conflicts
Home: https://github.com/llvm/llvm-project
Commit: 9f720984f08d161a8f996610840b859447c3ec5e
https://github.com/llvm/llvm-project/commit/9f720984f08d161a8f996610840b859447c3ec5e
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
Log Message:
-----------
[VPlan] Include wide IVs with NUW as monotonic in verifier. (#194959)
This fixes a verifier failure after
https://github.com/llvm/llvm-project/pull/194267 due to a wide IV
used in header mask compare being narrowed during later
optimizations.
This is in line how we treat other recipes, like adds, in the verifier
check.
Should fix https://lab.llvm.org/buildbot/#/builders/187/builds/19595.
Commit: a26d9c60372fde729ec63ac6d1ffa4da481e5274
https://github.com/llvm/llvm-project/commit/a26d9c60372fde729ec63ac6d1ffa4da481e5274
Author: Ralf Jung <post at ralfj.de>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] asm clobber constrains: '~memory' allows reads and synchronization (#150191)
I was not sure what the best way is for talking about "synchronization effects".
Commit: a9cef141e93ee5831bdd1ff01b8093bd80e02e57
https://github.com/llvm/llvm-project/commit/a9cef141e93ee5831bdd1ff01b8093bd80e02e57
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/MoveForwardingReferenceCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/move-forwarding-reference.cpp
Log Message:
-----------
[clang-tidy] Fix some false positive in bugprone-move-forwarding-reference (#191435)
In the following case:
template <typename T, typename U>
void shocase(U&& SomeU) {
[SomeU] () { T SomeT(std::move(SomeU)); };
}
We use to flag the move as a forward, while the lambda captures SomeU by
copy, which makes the move valid.
Commit: caa18a808aa0cc473a686fde72dfa12b4585eadd
https://github.com/llvm/llvm-project/commit/caa18a808aa0cc473a686fde72dfa12b4585eadd
Author: Farid Zakaria <fmzakari at fb.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/include/llvm/DWP/DWP.h
M llvm/include/llvm/DWP/DWPStringPool.h
A llvm/include/llvm/DWP/ELFWriter.h
M llvm/lib/DWP/CMakeLists.txt
M llvm/lib/DWP/DWP.cpp
A llvm/lib/DWP/ELFWriter.cpp
M llvm/test/tools/llvm-dwp/WebAssembly/simple_dwo.s
M llvm/tools/llvm-dwp/CMakeLists.txt
M llvm/tools/llvm-dwp/llvm-dwp.cpp
Log Message:
-----------
[llvm-dwp] Replace MCStreamer with direct ELF writer for zero-copy output (#192112)
Replace the MCStreamer-based output pipeline with a lightweight direct
ELF writer (DWPWriter). Section data is stored as zero-copy StringRef
chunks pointing to the mmap'd input files, and written as a minimal
ELF64 relocatable object directly to disk.
## Rationale
The MCStreamer pipeline copies all section data into 16KB MCDataFragment
blocks, accumulates them in memory, then writes everything out during
MCAssembler::Finish(). This can be cause lots of memory pressure and
slow down llvm-dwp.
For instance, on a 3.3GB DWP file, this translates to rougly ~3.3GB of
heap allocation and two full copies of the data.
The new DWPWriter avoids this via:
- emitBytes() stores a StringRef chunk (zero-copy, no allocation)
- emitIntValue() writes to a small per-section buffer (index tables)
- writeELF() streams chunks directly from input mmap to output file
- for single-input DWP files, string deduplication is also skipped since
all strings are already unique. (minor optimization)
Bonus: this also removes all MC library dependencies from llvm-dwp
(AllTargetsCodeGens, AllTargetsDescs, AllTargetsInfos, MC,
TargetParser), reducing the binary size.
## Benchmark
I benchmarked on a 3.3GB production DWP file (8638 CUs, ~981MB
.debug_str.dwo):
Results:
Before: 23.6s wall (19.6s user, 3.9s sys)
After: 6.0s wall (3.0s user, 2.9s sys)
**3.9x** wall time improvement, 6x fewer page faults (178K vs ~1M).
Commit: 965146d4e2a0922f2acdcfbe6e16cc7da65357f4
https://github.com/llvm/llvm-project/commit/965146d4e2a0922f2acdcfbe6e16cc7da65357f4
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/lib/DWARFLinker/Classic/DWARFLinkerDeclContext.cpp
A llvm/test/tools/dsymutil/X86/odr-simple-template-names-mixed.test
A llvm/test/tools/dsymutil/X86/odr-simple-template-names.test
Log Message:
-----------
[dsymutil] Fix ODR type uniquing for -gsimple-template-names (#194501)
With -gsimple-template-names (now the default on macOS with deployment
target >= 26), template types like vector<int> and vector<float> both
get DW_AT_name("vector") in DWARF, with template parameters encoded only
as DW_TAG_template_type_parameter children.
Previously, dsymutil used only DW_AT_name for ODR type uniquing, causing
different template specializations to collide. This PR fixes that by
reconstructing template parameter information from child DIEs when the
type name does not already contain template parameters.
The reconstructed name is used only for uniquing and not emitted into
the output DWARF. The parallel DWARF linker already handled this
correctly via SyntheticTypeNameBuilder.
rdar://175115639
Commit: 8f45c1e71859ebcfad8d8d43c3802207fc39e557
https://github.com/llvm/llvm-project/commit/8f45c1e71859ebcfad8d8d43c3802207fc39e557
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes caa18a8 (#194967)
This fixes caa18a808aa0cc473a686fde72dfa12b4585eadd.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 289b60430e10514dc1ba98ec2aea3226251f20ec
https://github.com/llvm/llvm-project/commit/289b60430e10514dc1ba98ec2aea3226251f20ec
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M libc/docs/dev/undefined_behavior.rst
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/thread.cpp
M libc/src/__support/threads/thread.h
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_join_test.cpp
Log Message:
-----------
[libc][thread] detect self-join and mutual-join deadlock (#194891)
Fix #194034.
Detect the deadlock cases of mutual thread joining.
Required by
`libcxx/test/std/thread/thread.jthread/join.deadlock.pass.cpp`
Assisted-by: Codex with gpt-5.5 high fast
Commit: 113479d119a997e4c4c3eae63e087588c9662121
https://github.com/llvm/llvm-project/commit/113479d119a997e4c4c3eae63e087588c9662121
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/test/CIR/Transforms/ternary.cir
Log Message:
-----------
[CIR] FlattenCFG: accept cir.trap as a ternary region terminator (#194497)
The CIRTernaryOpFlattening pattern only accepted cir.yield and
cir.unreachable as the terminator of a ternary region. Any other
terminator caused a verifier error ("unexpected terminator in ternary
false region") and aborted the backend with "IR failed to verify after
pattern application".
Real-world C++ code that uses the libc++ assertion macros hits this
path: _LIBCPP_ASSERT_NON_NULL expands to `cond ? (void)0 :
__builtin_trap()`, which lowers to a `cir.ternary` whose false region
ends in `cir.trap`. This is structurally identical to the
`cir.unreachable` case (both are non-returning Terminators), so the
flattening pattern just needs to leave the trap in place rather than
trying to rewrite it into a branch to the continue block.
Concretely this is blocking ~1,510 libc++ tests (~17% of the suite) that
all failed with the same diagnostic at construct_at.h, sample.h, and
pop_heap.h.
Extends clang/test/CIR/Transforms/ternary.cir with regression coverage
for cir.trap (true and false region) and cir.unreachable (false region).
Commit: bb82a7a8727dcc196f0acab644accf2165873712
https://github.com/llvm/llvm-project/commit/bb82a7a8727dcc196f0acab644accf2165873712
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Transforms/Instrumentation/MemProfInstrumentation.cpp
Log Message:
-----------
[MemProf] Skip GV `__prof*` during instrumentation (#193354)
The existing filter in `isInterestingMemoryAccess` skips globals named
`__llvm*`, but PGO counter globals are named `__profc_*` (and related
`__profd_*`, `__profvp_*`, etc.), so they bypass the name check, e.g.:
https://github.com/llvm/llvm-project/blob/b48d8a54e29f5f33ef52a4759414126904f01611/llvm/include/llvm/ProfileData/InstrProf.h#L128-L138
The section-based check above catches direct accesses where
`stripInBoundsOffsets` resolves to the GlobalVariable, but fails for
bias-based counter addressing `(inttoptr(add(ptrtoint(__profc_),
bias)))` which the strip cannot see through.
This causes MemProf to instrument PGO counter updates, inflating MGO
binary access profiles proportionally to __llvm_prf_cnts section size.
Filtering `__prof` prefixed globals closes this gap.
RFC: we have confirmed `__prof*` are dead weight, whether we should
block `llvm.*` like `InstrProfiling.cpp` did is an open question for ppl
familiar with MemProf, e.g.:
https://github.com/llvm/llvm-project/blob/b48d8a54e29f5f33ef52a4759414126904f01611/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp#L1518-L1521
Commit: 2296100e3b7ec901d972e88785768d3a2c494d72
https://github.com/llvm/llvm-project/commit/2296100e3b7ec901d972e88785768d3a2c494d72
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M lldb/tools/yaml2macho-core/yaml2macho.cpp
Log Message:
-----------
[lldb][windows] fix yaml2macho not loading file (#194909)
Commit: b5ff4526383dd83e256d3e3b72f8d1b36f044dc9
https://github.com/llvm/llvm-project/commit/b5ff4526383dd83e256d3e3b72f8d1b36f044dc9
Author: kjedruczyk <krzysztof.jedruczyk at gmail.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/ms-annotation.c
M clang/test/Sema/ms-annotation.c
Log Message:
-----------
[Clang] Reject __annotation on unsupported targets (#193731)
__annotation emits llvm.codeview.annotation intrinsics, which are only
consumed by CodeViewDebug
on Windows and UEFI targets. On other targets the intrinsic is silently
dropped, and codegen
hits an assertion due to wchar_t being 4 bytes (UTF-32) instead of the
expected 2 bytes
(UTF-16).
Fixes #184318
Commit: 560661319f3a8dff06c00bd219ca30be79501b66
https://github.com/llvm/llvm-project/commit/560661319f3a8dff06c00bd219ca30be79501b66
Author: Peter Collingbourne <pcc at google.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 7226f424bfe9
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/194975
Commit: 8ba1986136a4ab04b6849d8b54e3cdbcff71895e
https://github.com/llvm/llvm-project/commit/8ba1986136a4ab04b6849d8b54e3cdbcff71895e
Author: Peter Collingbourne <pcc at google.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/DWP/BUILD.gn
Log Message:
-----------
[gn build] Port caa18a808aa0
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/194976
Commit: cf3a327372f09815d78aa9066c19424f5a41f550
https://github.com/llvm/llvm-project/commit/cf3a327372f09815d78aa9066c19424f5a41f550
Author: Peter Collingbourne <pcc at google.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/IR/Verifier.cpp
A llvm/test/CodeGen/X86/elf-section-properties.ll
A llvm/test/Verifier/elf-section-properties.ll
Log Message:
-----------
IR: Introduce !elf_section_properties for setting section properties.
This new metadata type may be used to set sh_type and sh_entsize on a
global's section. The intent is that it will be used to mark up
CFI jump table sections.
Reviewers: fmayer, MaskRay, nikic, efriedma-quic
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/149260
Commit: 0177533792de5f891c46bce9c0c19e9002a1495e
https://github.com/llvm/llvm-project/commit/0177533792de5f891c46bce9c0c19e9002a1495e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
Log Message:
-----------
[RISCV] Remove isAsmParserOnly from LongBccPseudo and LongBcciPseudo. NFC (#194949)
These instructions are created by assembler relaxation. They aren't
"parsed.". isAsmParserOnly suppresses the disassembler for these, but
that was already suppressed by isPseudo and isCodeGenOnly.
Commit: 74f3b562b3393dfc619fdf4dbd58178922e3efbd
https://github.com/llvm/llvm-project/commit/74f3b562b3393dfc619fdf4dbd58178922e3efbd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
Log Message:
-----------
[RISCV] Remove isAsmParserOnly from isPseudo instructions. NFC (#194958)
isAsmParserOnly is only used to suppress DecoderEmiter, but that's
already supressed by isPseudo. The real usage for this should be for
instructions that have encoding information but we don't want to
disassemble.
Many of these pseudos are emitted from codegen meaning they aren't
really assembler only. So you can't argue this flag is good for
documentation either.
Commit: df32e6993816754ceb35a3d483c09ec1c98d55b5
https://github.com/llvm/llvm-project/commit/df32e6993816754ceb35a3d483c09ec1c98d55b5
Author: Aidan Shilling <aidanshilling at disroot.org>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
Log Message:
-----------
[AMDGPU]/GlobalISel: RegBankLegalize rules for fp8/bf8 cvt intrinsics (#193551)
Commit: fbdc27d8db04cea39772301452d25afa805afa6f
https://github.com/llvm/llvm-project/commit/fbdc27d8db04cea39772301452d25afa805afa6f
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M clang-tools-extra/modularize/CoverageChecker.cpp
M clang-tools-extra/modularize/ModularizeUtilities.cpp
Log Message:
-----------
[clang][tools] NFC: Replace `auto` with `Module *` (#194977)
This finishes what #194032 started.
Commit: 6cad48ae72fbf344aab52cf28d51cb874dc30e20
https://github.com/llvm/llvm-project/commit/6cad48ae72fbf344aab52cf28d51cb874dc30e20
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
R llvm/include/llvm/CodeGen/WasmEHFuncInfo.h
A llvm/include/llvm/CodeGen/WasmEHInfo.h
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
M llvm/test/CodeGen/WebAssembly/function-info.mir
M llvm/test/CodeGen/WebAssembly/multivalue-dont-move-def-past-use.mir
Log Message:
-----------
[WebAssembly] Remove WasmEHFuncInfo (NFC) (#194972)
This removes `WasmEHFuncInfo` class.
This class was created to maintain the information of, "If an exception
is not caught by EHPad A, what is its next unwind destination?". Turns
out this information is already in the CFG.
After #130374, we use the common `findUnwindDestination`:
https://github.com/llvm/llvm-project/blob/113479d119a997e4c4c3eae63e087588c9662121/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L2107-L2164
Note that in case of `catchswitch`, we follow its unwind destination
chain and add all of them to the invoke BB's successors until it meets a
`cleanuppad`, which always catches an exception. And the order of the
successor is the order of the unwind destination chain. So an invoke
BB's successor list would be like: [normal destination, unwind EHPad 1,
unwind EHPad 2, unwind EHPad 3, ...] where EHPad 2 is the next unwind
destination if EHPad 1 does not catch an exception and so on. So if we
want to know what the current EHPad's next unwind destination is, we can
examine the EHPad's predecessor (invoke BB)'s successor list, and find
the next successor of EHPad. If there is no further next unwind
destination, the list should end with that EHPad.
How we do this is in the added lambda functions in CFGStackify, which
replaces `WasmEHFuncInfo`'s `hasUnwindDest`/`getUnwindDest`.
This depends on the order of successors of a CFG, which someone can
argue may be not guaranteed, in case someone messes up the successor
order in later passes. But I think in practice this should be fine. Also
maintaining `WasmEHFuncInfo` has more risks, because if other passes
change EH-related CFGs, they have to make sure `WasmEHFuncInfo` stays
synced. I haven't personally found (so far) those passes and haven't had
to any adjustments to other passes, but it was always an inherent risk
when you maintain a separate data structure.
I wasn't able to completely delete `WasmEHFuncInfo.h` because it
contains the `Tag` enum. I renamed it to `WasmEHInfo.h`, because we
dont' have `WasmEHFuncInfo` class anymore.
Commit: 0abb4569da0328441f14edb14be59da08c46ccac
https://github.com/llvm/llvm-project/commit/0abb4569da0328441f14edb14be59da08c46ccac
Author: Lang Hames <lhames at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/NativeDylibManager.h
A orc-rt/include/orc-rt/sps-ci/NativeDylibManagerSPSCI.h
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/NativeDylibManager.cpp
A orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
A orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
M orc-rt/unittests/CMakeLists.txt
A orc-rt/unittests/Inputs/NativeDylibManagerTestLib.cpp
A orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
A orc-rt/unittests/NativeDylibManagerTest.cpp
Log Message:
-----------
[orc-rt] Add NativeDylibManager. (#194792)
NativeDylibManager is an orc_rt::Service that supports loading,
unloading, and lookup of symbols via the system dynamic loader's native
APIs.
The current implementation only supports the POSIX dlfcn.h APIs (dlopen,
dlclose, dlsym), but it should be straightforward to extend to Windows.
Commit: c81f88379184eff6a7bf3b92bf9899d00f695db4
https://github.com/llvm/llvm-project/commit/c81f88379184eff6a7bf3b92bf9899d00f695db4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Use isCodeGenOnly field of CodeGenInstruction. NFC (#194942)
Commit: 8d53d36cf314279e5a463a4806e2babe37fb67ee
https://github.com/llvm/llvm-project/commit/8d53d36cf314279e5a463a4806e2babe37fb67ee
Author: lrzlin <linrunze at loongson.cn>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
A llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
A llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll
M llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll
Log Message:
-----------
[LoongArch] Introduce LASX instruction patterns for vector sign/zero extensions (#193727)
This patch introduces LASX only legalization and instruction patterns
for vector sign and zero extension operations, which is basically copy
from the https://github.com/llvm/llvm-project/pull/160810 with some
minor change (e.g. deleted unused tablegen pattern).
Commit: c1a2360918328c1fb58ade910ddc617c9ce011a7
https://github.com/llvm/llvm-project/commit/c1a2360918328c1fb58ade910ddc617c9ce011a7
Author: Soowon Jeong <soowon1106 at gmail.com>
Date: 2026-04-29 (Wed, 29 Apr 2026)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/CAPI/ir.c
M mlir/test/python/ir/location.py
Log Message:
-----------
[mlir][python] expose remaining Location inspection API (#192630)
Addresses #53169. Mirrors the Python bindings pattern used for Attribute
subclasses so that Location discrimination uses `isinstance`, and fills
two small gaps at the same time.
### Approach
Previously `Location` was a single nanobind class with `is_a_file`,
`is_a_name`, etc. predicates, plus field accessors for every kind
defined on the base class. This PR introduces a `PyConcreteLocation<T>`
CRTP template (parallel to `PyConcreteAttribute<T>`) and registers one
subclass per `LocationAttr` kind: `UnknownLoc`, `FileLineColLoc`,
`NameLoc`, `CallSiteLoc`, `FusedLoc`.
TypeID-based downcasting is implemented in `PyLocation::maybeDownCast`
(using `mlirAttributeGetTypeID(mlirLocationGetAttribute(...))`) and
called at the boundaries that return Location objects: `op.location`,
`value.location`, `Location.from_attr`, and the subclass getters
themselves.
### Example
```python
from mlir.ir import Context, Module, FileLineColLoc, NameLoc, FusedLoc
with Context():
module = Module.parse("...")
for op in module.body.operations:
loc = op.location
if isinstance(loc, FileLineColLoc):
report(f"{loc.filename}:{loc.start_line}:{loc.start_col}")
elif isinstance(loc, NameLoc):
report(loc.name_str)
elif isinstance(loc, FusedLoc) and loc.metadata is not None:
report_fused(loc.locations, loc.metadata)
```
`FusedLoc.metadata` is also newly exposed (the underlying C API
`mlirLocationFusedGetMetadata` already existed but was not bound).
### Custom/downstream Location classes
`PyConcreteLocation<DerivedTy>` is marked `MLIR_PYTHON_API_EXPORTED` and
is used identically to `PyConcreteAttribute<DerivedTy>`. Downstream
projects that define their own `LocationAttr` in C++ expose a matching
Python class by declaring a subclass with the standard statics
(`isaFunction`, `pyClassName`, optional `getTypeIdFunction`) and calling
its `bind(m)` at module init; `isinstance` and automatic downcasting
then work with no further changes in the base bindings.
### Backward compatibility
Existing factories — `Location.unknown()`, `Location.file(...)`,
`Location.name(...)`, `Location.callsite(...)`, `Location.fused(...)` —
remain as aliases and now return the concrete subclass instance (so
`isinstance(Location.file(...), FileLineColLoc)` is true). No user
migration is required for construction.
The old `is_a_*` predicate methods are removed; downstream consumers
should switch to `isinstance(...)`. No in-tree users of the removed
predicates besides the existing Location tests, which have been
rewritten accordingly.
### Scope note — OpaqueLoc
OpaqueLoc is intentionally not included. It is keyed on a C++
`TypeID::get<T>()` tag that has no natural Python counterpart, and I
could not find a downstream consumer asking for Python exposure. An
earlier revision of this PR exposed it with an `id(obj)` + `ctypes.cast`
example, but that pattern is lifetime-unsafe (MLIR does not INCREF the
underlying pointer) and the C++ `getUnderlyingLocation<T>()` semantics
don't translate cleanly. Happy to add it in a follow-up once a real use
case surfaces.
### Changes
C API (`mlir/include/mlir-c/IR.h`, `mlir/lib/CAPI/IR/IR.cpp`):
- `mlirLocationIsAUnknown`, `mlirLocationUnknownGetTypeID` — other
Location kinds already had their `IsA*`/`*GetTypeID` pair.
Python (`mlir/include/mlir/Bindings/Python/IRCore.h`,
`mlir/lib/Bindings/Python/IRCore.cpp`):
- `PyConcreteLocation<T>` template and five concrete classes
- `PyLocation::maybeDownCast`
- Subclass `.get()` constructors, `.metadata` on `FusedLoc`
Tests:
- `mlir/test/python/ir/location.py` rewritten around `isinstance` and
subclass construction; adds explicit-cast-failure coverage.
- `mlir/test/CAPI/ir.c` adds `testLocation` covering the new
`mlirLocationIsAUnknown` predicate.
### Tool-use disclosure
This change was drafted with Claude (Anthropic) assistance per LLVM's
[AI Tool Use Policy](https://llvm.org/docs/AIToolPolicy.html). All code
was read, reviewed, and tested locally by me; the commit carries
`Assisted-by:` and `Co-Authored-By:` trailers accordingly.
---------
Co-authored-by: Claude (Anthropic) <noreply at anthropic.com>
Commit: bcbad84a7c56c99c0d628e2b24fac856c87bb98a
https://github.com/llvm/llvm-project/commit/bcbad84a7c56c99c0d628e2b24fac856c87bb98a
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/c.c
M clang/test/Parser/pragma-fenv_access.c
Log Message:
-----------
[clang][bytecode] Only revisit C variables with valid initializers (#194881)
We don't mark them as constexpr-unknown, so check that the initializer
can be evaluated.
Commit: 3d19371ef119ad9d93e14408b4bc51e870c2ae25
https://github.com/llvm/llvm-project/commit/3d19371ef119ad9d93e14408b4bc51e870c2ae25
Author: Rana Pratap Reddy <109514914+ranapratap55 at users.noreply.github.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/IR/calling-conv.cir
A clang/test/CIR/Lowering/calling-conv.cir
Log Message:
-----------
[CIR] Add calling_conv attribute to FuncOp with lowering support (#189345)
Adds `calling_conv` attribute to `FuncOp` with support
(`cc(amdgpu_kernel)` syntax) and LLVM lowering.
Continuation of #188715 and a partial upstreaming of
[clangir#760](https://github.com/llvm/clangir/pull/760/).
Commit: af4649fe1c92022365043ccb48d217403e54de14
https://github.com/llvm/llvm-project/commit/af4649fe1c92022365043ccb48d217403e54de14
Author: Rana Pratap Reddy <109514914+ranapratap55 at users.noreply.github.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/TargetInfo.cpp
M clang/lib/CIR/CodeGen/TargetInfo.h
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-logb-scalbn.hip
Log Message:
-----------
[CIR][AMDGPU] Adds amdgcn logb and scalebn builtins (#191344)
Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/2065
Support for lowering of `__builtin_amdgcn_logb` and `scalebn` for AMDGPU
builtins to clangIR.
Followed similar lowering from clang->llvmir:
`clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp`.
Commit: cc0a1d85e68de492a33a801838a72e63570d80de
https://github.com/llvm/llvm-project/commit/cc0a1d85e68de492a33a801838a72e63570d80de
Author: Gil Rapaport <gil.rapaport at mobileye.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/form-expressions.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/Cpp/member.mlir
Log Message:
-----------
[mlir][emitc] Deferred emission as expressions (#159975)
The translator currently implements deferred emission for certain ops.
Like expressions, these ops are emitted as part of their users but
unlike expressions, this is mandatory. Besides complicating the code
with a second inlining mechanism, deferred emission's inlining is
limited as it's not recursive.
This patch extends EmitC's expressions to deferred emission ops by (a)
marking them as CExpressions, (b) extending expression interface to mark
ops as always-inline and (c) support inlining of always-inline
CExpressions even when not packed of an `emitc.expression` op, retaining
current behavior.
Commit: 8106f3b3c29b8318bfc1c447cf9f8409198e5536
https://github.com/llvm/llvm-project/commit/8106f3b3c29b8318bfc1c447cf9f8409198e5536
Author: David Green <david.green at arm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/adc.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
M llvm/test/CodeGen/AArch64/fcmp-fp128.ll
M llvm/test/CodeGen/AArch64/shift-logic.ll
M llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
Log Message:
-----------
[AArch64][GlobalISel] Normalize and cleanup some test checks. NFC (#195016)
Commit: 9c618b731edf0dc5952ecc9de5441fc9119be099
https://github.com/llvm/llvm-project/commit/9c618b731edf0dc5952ecc9de5441fc9119be099
Author: Hemang Gadhavi <hemang.gadhavi at ibm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M lldb/source/Plugins/Process/AIX/NativeProcessAIX.cpp
M lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.cpp
M lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h
M lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp
M lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.h
M lldb/source/Plugins/Process/AIX/NativeThreadAIX.cpp
M lldb/source/Plugins/Process/AIX/NativeThreadAIX.h
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.h
M lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64.h
Log Message:
-----------
[lldb][AIX] Implement read/write handling for GPR and SPR registers (#193205)
This PR is in reference to porting LLDB on AIX. Ref discusssions: [llvm
discourse](https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640) and
https://github.com/llvm/llvm-project/issues/101657.
Complete changes together in this draft:
- https://github.com/llvm/llvm-project/pull/102601
Description:
Add support for accessing General Purpose Registers (GPRs) and Special
Purpose Registers (SPRs) for debugging both 32-bit and 64-bit binaries.
Including proper mapping and read/write handling through the register
context.
Commit: 3e8fbb278e58756f44ba0ad97f995f3f4a004467
https://github.com/llvm/llvm-project/commit/3e8fbb278e58756f44ba0ad97f995f3f4a004467
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M lldb/include/lldb/Breakpoint/BreakpointSite.h
M lldb/include/lldb/Target/Process.h
M lldb/source/Breakpoint/BreakpointSite.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/Utility/StopInfoMachException.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp
M lldb/source/Plugins/Process/scripted/ScriptedThread.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/ThreadPlanStepOverBreakpoint.cpp
Log Message:
-----------
[lldb][NFC] Move BreakpointSite::IsEnabled/SetEnabled into Process (#192964)
The Process class is the one responsible for managing the state of a
BreakpointSite inside the process. As such, it should be the one
answering questions about the state of the site.
Future patches will make this even more important by introducing a
"logical" is enabled, by delaying the moment in which breakpoints are
actually updated in the process.
The following PRs are related to the MultiBreakpoint feature:
* https://github.com/llvm/llvm-project/pull/192910
* https://github.com/llvm/llvm-project/pull/192914
* https://github.com/llvm/llvm-project/pull/192915
* https://github.com/llvm/llvm-project/pull/192919
* https://github.com/llvm/llvm-project/pull/192962
* https://github.com/llvm/llvm-project/pull/192964
* https://github.com/llvm/llvm-project/pull/192971
* https://github.com/llvm/llvm-project/pull/192988
Commit: 18060c205ba1f79c13e545cd485d1735fb4d2243
https://github.com/llvm/llvm-project/commit/18060c205ba1f79c13e545cd485d1735fb4d2243
Author: hev <wangrui at loongson.cn>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/bitsel.ll
A llvm/test/CodeGen/LoongArch/lsx/bitsel.ll
Log Message:
-----------
[LoongArch][NFC] Add tests for vector bitwise selection (#193752)
Commit: cb9ffe1d455bc64e902cd0bbce4fe01e385ff976
https://github.com/llvm/llvm-project/commit/cb9ffe1d455bc64e902cd0bbce4fe01e385ff976
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[MLIR][Arith] Add subf(-0, x) -> negf(x) canonicalization rule for SubFOp (#194245)
Arith lacks support for this fold unlike LLVM:
Example: https://godbolt.org/z/1v5jGTsh1
Proof: https://alive2.llvm.org/ce/z/Wq8ALG
Commit: 24e441428090d81ba8d9d163b65949d43f90e591
https://github.com/llvm/llvm-project/commit/24e441428090d81ba8d9d163b65949d43f90e591
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/fixed-point.cpp
Log Message:
-----------
[clang][bytecode] Fix DiscardResult handling in fixed-point operations (#195013)
Commit: 896a1fe24b0250b6a3265fc13771a850d55bec0e
https://github.com/llvm/llvm-project/commit/896a1fe24b0250b6a3265fc13771a850d55bec0e
Author: Weiwen He <60433849+he-weiwen at users.noreply.github.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/addp-shuffle.ll
Log Message:
-----------
[AArch64] Extend addp pattern to add_like(xtn, uzp2) in 128 bit result type (#194064)
Fixes #192712 along with #193075
pre-commit: https://godbolt.org/z/EWYGfP18G
Commit: a80638ed420b3c1aa6a9f2121573278d9820a81f
https://github.com/llvm/llvm-project/commit/a80638ed420b3c1aa6a9f2121573278d9820a81f
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
Log Message:
-----------
[NFC][analyzer] Remove various NodeBuilders (#194843)
This commit replaces some `NodeBuilder`s with use of
`CoreEngine::makeNode` in straightforward situations.
Part of the commit series where I gradually eliminate all use of
`NodeBuilder`s to make the logic more transparent.
Commit: 16d2bcd5a8cc76aa97639da150467d20be343331
https://github.com/llvm/llvm-project/commit/16d2bcd5a8cc76aa97639da150467d20be343331
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/OpenACC/locations.f90
M flang/test/Lower/OpenMP/location.f90
A flang/test/Lower/where-loc.f90
Log Message:
-----------
[flang][lower] fix source location in WHERE constructs (#194849)
The location of hlfir.where operations was not set correctly (left to
the location of the previous statement of construct).
Fix this and add test.
While doing so, I noticed the bridge current location was not set
consistently when entering constructs. While this usually was OK because
no code was emitting in many case before visiting an inner construct,
there was at least one case where this lead to bad location for OpenAcc
atomic. Hence I updated all construct that did not call
`setCurrentPositionAt` to do it, this seems more future proof.
Commit: b8551d94d4ce33cf16dbbe3f4f512e6ee2dce899
https://github.com/llvm/llvm-project/commit/b8551d94d4ce33cf16dbbe3f4f512e6ee2dce899
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/addr-label-diff.cpp
Log Message:
-----------
[clang][bytecode] Fix a crash with addr label diffs (#195011)
Can't call `getPtr()` on numbers.
Commit: 330a8f986a98bf4ad173288e3eae429f71563f9c
https://github.com/llvm/llvm-project/commit/330a8f986a98bf4ad173288e3eae429f71563f9c
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
Log Message:
-----------
[LV][NFC] Remove use of -print-after=... to verify IR output (#194882)
In the case of LoopVectorize/loop-scalars.ll this means we can now
remove "REQUIRES: asserts" as well.
Commit: c6b245f168e28481fbca59b1c8787cc0694c1ec5
https://github.com/llvm/llvm-project/commit/c6b245f168e28481fbca59b1c8787cc0694c1ec5
Author: Shubham Sandeep Rastogi <Shubham.Rastogi at sony.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/X86/sdag-extload-combine-crash.ll
A llvm/test/DebugInfo/X86/sdag-load-sext-trunc.ll
A llvm/test/DebugInfo/X86/sdag-load-sext.ll
A llvm/test/DebugInfo/X86/sdag-load-zext-multiple-args.ll
Log Message:
-----------
[SelectionDAG] Reland debuginfo salvage for load/ext combines (#194700)
This relands fe5d5b762ab3b92b18b56f413965abb81a459ac6, which salvages
debug info when folding load and zext/sext patterns in SelectionDAG.
Salvage debuginfo when combining load and z|s ext instrs.
SelectionDAG uses the DAGCombiner to fold a load followed by a sext to a
load and sext instruction. For example, in x86 we will see that
```
%1 = load i32, ptr @GlobArr
#dbg_value(i32 %1, !43, !DIExpression(), !52)
%2 = sext i32 %1 to i64, !dbg !53
```
is converted to:
```
%0:gr64_nosp = MOVSX64rm32 $rip, 1, $noreg, @GlobArr, $noreg, debug-instr-number 1, debug-location !51
DBG_VALUE $noreg, $noreg, !"Idx", !DIExpression(), debug-location !52
```
The `DBG_VALUE` needs to be transferred correctly to the new combined
instruction, and it needs to be appended with a `DIExpression` which
contains a `DW_OP_LLVM_convert` expression, which correctly casts the
value in the virtual register to the correct size.
This patch fixes the above described problem.
The patch also accounts for multiple DW_OP_LLVM_arg's in a DIExpression
which had caused it to break tests on the sanitizer-x86_64-linux bot but
has now been fixed, with an added testcase called
selectionDAG-load-zext-multiple-args.ll which was reduced from the
broken test itself.
fe5d5b762ab3b92b18b56f413965abb81a459ac6 exposed a crash in
tryToFoldExtOfLoad(), which is described in
https://github.com/llvm/llvm-project/issues/193475
Fix that by replacing the folded node before deleting or rewriting the
old nodes, and by transferring debug values before entering the
replacement path.
Add an X86 regression test for the extload combine crash.
Commit: 9561b079ca65e063731df4894806f4f718323cf6
https://github.com/llvm/llvm-project/commit/9561b079ca65e063731df4894806f4f718323cf6
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/max-vf-for-interleaved.ll
M llvm/test/Transforms/LoopVectorize/global_alias.ll
M llvm/test/Transforms/LoopVectorize/tbaa-nodep.ll
Log Message:
-----------
[LV][NFC] Remove instcombine from RUN lines when it has no effect (#194874)
Commit: 436fbb81758bf43bab7d0047633ac8da203b1e57
https://github.com/llvm/llvm-project/commit/436fbb81758bf43bab7d0047633ac8da203b1e57
Author: Will Hawkins <hawkinsw at obs.cr>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M lldb/docs/use/variable.rst
Log Message:
-----------
[lldb][docs] Update Variable Formatting Documentation (#193907)
Various improvements to the LLDB Variable Formatting documentation:
1. Use consistent formatting.
2. Polish wording.
3. Add examples.
Signed-off-by: Will Hawkins <hawkinsw at obs.cr>
Commit: 272812b9b45978080d1f73333451bb98938a5a3b
https://github.com/llvm/llvm-project/commit/272812b9b45978080d1f73333451bb98938a5a3b
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/unittests/Transforms/Vectorize/VPlanPatternMatchTest.cpp
Log Message:
-----------
[VPlan] Tighten m_CanonicalIV() (#194312)
Previously `m_CanonicalIV()` matched any `VPRegionValue`, which was only
correct because the canonical IV is the sole `VPRegionValue` today.
Going ahead this is not scalable and there may be more `VPRegionValue`.
Commit: c10f33e8935de001a10f46bc370dc12aa67e5674
https://github.com/llvm/llvm-project/commit/c10f33e8935de001a10f46bc370dc12aa67e5674
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/python/mlir/dialects/_ods_common.py
M mlir/python/mlir/dialects/transform/structured.py
M mlir/test/Dialect/Linalg/transform-op-fuse.mlir
M mlir/test/python/dialects/transform_structured_ext.py
Log Message:
-----------
[mlir][linalg] Fuse transform op - variadic tile sizes (#194657)
Extends the 'structured.fuse' op to accept packed handle containing
variable number of tile sizes.
Use of packed handles allows for runtime tiling decisions for improved
transform schedule flexibility and reusability.
The extension's design follows the existing approach of transform
'structured.tile_using_forall' op to more closely align their usage.
In case of tiling using nested loops, all created loops are packed into
a single return handle. For each target op, corresponding loops are
appended to the result handle.
Assisted-by: Claude
Commit: 8baf7cc34b004f27d1e1727f8c5a1de55bc07528
https://github.com/llvm/llvm-project/commit/8baf7cc34b004f27d1e1727f8c5a1de55bc07528
Author: CarolineConcatto <caroline.concatto at arm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Analysis/MemorySSA/pr43427.ll
M llvm/test/Analysis/MemorySSA/pr43438.ll
M llvm/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/guards.ll
M llvm/test/Transforms/LICM/hoist-debuginvariant.ll
A llvm/test/Transforms/LICM/hoist-inaccesiblemem-call.ll
M llvm/test/Transforms/LICM/invariant.start.ll
M llvm/test/Transforms/LICM/pr50367.ll
M llvm/test/Transforms/LICM/pr59324.ll
M llvm/test/Transforms/LICM/store-hoisting.ll
Log Message:
-----------
[LICM] Improve hoist-safety checks for dominated MemorySSA accesses (#169379)
This changes LICM's hoist-safety check in `noConflictingReadWrites()`.
When considering a `MemoryDef` for hoisting, LICM now skips in-loop
accesses that are already dominated by that `MemoryDef`:
```c++
if (!Flags.getIsSink() && MSSA->dominates(IMD, &MA))
continue;
```
Dominated accesses should not block hoisting, because they already
execute after the candidate instruction `I` and therefore already see
its effect. Non-dominated accesses can block hoisting, because they may
execute before the candidate `I` and observe a different memory state
after hoisting.
The tests are updated to cover the new behavior, including
store-hoisting, call-hoisting, guards, `llvm.invariant.start`, and
inaccessible-memory call cases, along with the corresponding MemorySSA
check updates.
Commit: 34a1888bea787d35d1df2daf595222558681cb5b
https://github.com/llvm/llvm-project/commit/34a1888bea787d35d1df2daf595222558681cb5b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M mlir/include/mlir/Transforms/Passes.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/include/mlir/Transforms/RegionUtils.h
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Transforms/CMakeLists.txt
A mlir/lib/Transforms/TrivialDeadCodeElimination.cpp
M mlir/lib/Transforms/Utils/RegionUtils.cpp
A mlir/test/Transforms/dead-code-elimination.mlir
Log Message:
-----------
[mlir] Refactor transform.apply_dce into a eliminateTriviallyDeadOps region-utils helper and expose as a Pass (#194041)
Introduce a lightweight, targeted dead-op eliminator that complements
the
existing liveness-based runRegionDCE. The algorithm is O(ops):
step 1 walks each op in reverse program order, erases it outright if
trivially dead, or recurses into nested regions when recursive cleanup
is
enabled; step 2 drives a per-region worklist that only ever holds ops
already verified dead, propagating new deadness by dropping each
operand's
use before re-checking isOpTriviallyDead on the defining op.
Unlike runRegionDCE, this does not touch dead block arguments, dead
successor operands, or dead use-def cycles. Use runRegionDCE when those
are required. An includeNestedRegions parameter lets callers restrict
simplification to the top-level region.
Switch transform.apply_dce to use the new helper, dropping a custom
worklist that had subtle invariants: SetVector dedup, linear search on
every erase, and pre-order walk with skip.
In general it is bad practice to implement complex custom logic in
Transform ops apply methods: this should be an adaptor exposing MLIR
transformations to the transform dialect; non-trivial logic deserves a
public API for reusability and proper layering.
Introduce a TrivialDeadCodeEliminationPass exposed as -trivial-dce. The
pass
removes trivially dead operations and, when removeBlocks is enabled,
unreachable blocks. It does not run liveness analysis and does not
remove
dead use-def cycles. Add recursive and removeBlocks options, both
defaulting
to true, to control whether nested regions are visited and whether
unreachable blocks are erased.
Assisted-by: Claude Code
Commit: 2c79f903048728b41c9399f0f8e822147934e4c1
https://github.com/llvm/llvm-project/commit/2c79f903048728b41c9399f0f8e822147934e4c1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M libcxx/include/__locale
M libcxx/include/ios
M libcxx/src/ios.cpp
Log Message:
-----------
[libc++] Avoid type-punning locale in ios_base (#193507)
While there is currently a comment that all members of `ios_base` must
be scalars, I see no reason that is a correct statement. However, the
only place where this is relevant is `locale __loc_`. This patch
replaces the current `void*` implementation with `union { locale __loc_
}` to simplify `ios.cpp`.
Commit: 1bba540d910732a4fff5b1d17fc5c102662a6cd2
https://github.com/llvm/llvm-project/commit/1bba540d910732a4fff5b1d17fc5c102662a6cd2
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
Log Message:
-----------
[MLIR][NVVM] Fix `inline_ptx` when there is only clobber register (#194380)
The interface crashes when there is only clobber register (read-write)
today.There isn't any PTX instruction with only clobber register but the
compiler should not crash.
Commit: 91c170321251921a649767a9a1520b546df3d640
https://github.com/llvm/llvm-project/commit/91c170321251921a649767a9a1520b546df3d640
Author: Petter Berntsson <petter.berntsson at arm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
A libc/utils/docgen/sys/ipc.yaml
Log Message:
-----------
[libc][docs] Add sys/ipc.h POSIX header documentation (#122006) (#194340)
Add sys/ipc.h implementation-status docs to llvm-libc.
Commit: 6dcb422a18e02acf7489f6dc68fa3e607017b918
https://github.com/llvm/llvm-project/commit/6dcb422a18e02acf7489f6dc68fa3e607017b918
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp
Log Message:
-----------
[clang][bytecode] Reject uninitialized bases in builtin_bit_cast (#194625)
Like the current interpreter does. Also use the bytecode interpreter in
the test in SemaCXX/.
Commit: 124ab73043b236bd1c8e269d7a8467d6fba66756
https://github.com/llvm/llvm-project/commit/124ab73043b236bd1c8e269d7a8467d6fba66756
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__cxx03/cinttypes
M libcxx/include/cinttypes
R libcxx/include/inttypes.h
M libcxx/include/module.modulemap.in
Log Message:
-----------
[libc++] Remove libc++'s own inttypes.h (#193716)
The header does three things:
- it defines `__STDC_FORMAT_MACROS` for compatibility with glibc
versions we don't support anymore
- it includes `<stdint.h>`, which is already required to be included by
the C standard
- it `#undef`s two macros which might be defined by the libc. We don't
provide a `<stdint.h>` header ourselves, which might provide these
macros as well, so these are already not defined by any libcs we
support.
So this header should be safe to remove.
Commit: 4354248d10fbf053189ed94dfab9657af8c545af
https://github.com/llvm/llvm-project/commit/4354248d10fbf053189ed94dfab9657af8c545af
Author: Fabrice de Gans <Steelskin at users.noreply.github.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
llvm: Use add_link_options for stack size flags (#195034)
Previously, LLVM was directly editing `CMAKE_EXE_LINKER_FLAGS`. This is
a user-facing CMake cache variable not meant to be modified by project
code. This was causing issues for downstream consumers building
non-C/C++ targets as part of the LLVM build.
Modern CMake provides `add_link_options()`, a cleaner way to set linker
flags that propagate to every target in a directory tree.
Generator expressions and the `LINKER:` prefix syntax ensure that this
is only applied to executable targets with the proper language and
linker argument wrapping.
Commit: 317417e9bc38e095730c6e01022d509fb3cfd02a
https://github.com/llvm/llvm-project/commit/317417e9bc38e095730c6e01022d509fb3cfd02a
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
Log Message:
-----------
[SelectionDAG][AArch64] Legalize vector.[de]interleave6 (#193723)
With #192972 and #192677 merged, [de]interleave6 can also benefit from
the existing legalization work from #141513
Commit: b689f8b7c6e56ee0127f98d2e613b6aa2d7601b2
https://github.com/llvm/llvm-project/commit/b689f8b7c6e56ee0127f98d2e613b6aa2d7601b2
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/or-exit-cond.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-andor-selectform.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-andor.ll
A llvm/test/Transforms/IndVarSimplify/or-exit-cond.ll
Log Message:
-----------
[SCEV] Limit ControlsOnlyExit logic to BinOps with neutral elements. (#194831)
As far as I can tell, ControlsOnlyExit is used during reasoning to
assume
that we stay in the loop as long as the condition is true/false, and are
guaranteed to exit otherwise.
But unless I am missing something, a sub-condition of an AND/OR never
solely controls the exit, whether we exit always depends on both
conditions.
Pass false to ControlsOnlyExit, as otherwise we would incorrectly assume
that we must exit if either conditions is true, when we would only exit
if both are true.
For now, ControlsOnlyExit is only used for the neutral element case, it
may be worth removing this.
Alive2 proof of IndVars mis-compile: https://alive2.llvm.org/ce/z/kWs4hE
PR: https://github.com/llvm/llvm-project/pull/194831
Commit: 39e30cc8a1fa7be2f6d0ff607969ac0a46219924
https://github.com/llvm/llvm-project/commit/39e30cc8a1fa7be2f6d0ff607969ac0a46219924
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/include/llvm/Support/KnownFPClass.h
M llvm/lib/Support/KnownFPClass.cpp
Log Message:
-----------
[KnowFPClass] Refactor fmul & fdiv (NFC) (#191651)
- Remove `0 * Inf -> NaN` redundant check and a nan setting.
The reason:
```rust
1. Inf * Y -> {Inf, NaN}
2. 0 * Y -> {Zero, NaN}
3. 0 * Inf -> NaN
```
But after `1.` and `2.` we already have `{Inf, NaN} ∩ {Zero, NaN} ->
NaN`
So `3.` is redundant and [can be
removed](https://github.com/llvm/llvm-project/pull/191651/changes#diff-eacbd8c8620db92a00453be14b3b433c618946ad7b57c10b039437641e9777c4L389):
```diff
// +/-0 * +/-inf = nan
- if ((KnownLHS.isKnownAlways(fcZero | fcNan) &&
- KnownRHS.isKnownAlways(fcInf | fcNan)) ||
- (KnownLHS.isKnownAlways(fcInf | fcNan) &&
- KnownRHS.isKnownAlways(fcZero | fcNan)))
- Known.knownNot(~fcNan);
```
- Group repeated twice sign inferring into `propagateXorSign` helper
- Add more conventional comments
Commit: f32da7bc5bc75fc078a590ef71b2429fc176aa6e
https://github.com/llvm/llvm-project/commit/f32da7bc5bc75fc078a590ef71b2429fc176aa6e
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/lib/Dialect/SPIRV/IR/SPIRVTosaOps.cpp
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
Log Message:
-----------
[mlir][spirv] Tighten SPIR-V TOSA convolution verification (#194592)
Add verifier coverage for SPIR-V TOSA convolution ops against the TOSA
shape and type constraints.
This adds shared TableGen shape predicates for Conv2D, Conv3D,
DepthwiseConv2D and TransposeConv2D, including batch/channel/bias
relationships. It also constrains integer convolution weights so i8 and
i16 inputs use i8 weights, matching the SPIR-V TOSA representation.
Add custom verifiers for the convolution output shape formulas,
including stride divisibility for regular convolutions and out_pad
bounds for TransposeConv2D. Tighten pad, stride and dilation attributes
to use non-negative or positive i32 attribute constraints where
required.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: 63ee54a53209f2b3f186ba216707b2441e6294cb
https://github.com/llvm/llvm-project/commit/63ee54a53209f2b3f186ba216707b2441e6294cb
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M libcxx/include/__ostream/print.h
M libcxx/include/print
A libcxx/test/benchmarks/format/print.bench.cpp
A libcxx/test/libcxx/input.output/iostream.format/print.fun/output_unicode_windows.pass.cpp
R libcxx/test/libcxx/input.output/iostream.format/print.fun/vprint_unicode_windows.pass.cpp
Log Message:
-----------
[libc++] Refactor std::print to allow for constant folding of the format part (#185459)
```
---------------------------------------------------------
Benchmark old new
---------------------------------------------------------
std::print("Hello, World!") 43.6 ns 9.88 ns
```
Commit: 780a1821b102ac95eee36183da7785984e824947
https://github.com/llvm/llvm-project/commit/780a1821b102ac95eee36183da7785984e824947
Author: hev <wangrui at loongson.cn>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/bitsel.ll
M llvm/test/CodeGen/LoongArch/lsx/bitsel.ll
Log Message:
-----------
[LoongArch] Add patterns for vector bitwise selection (#193753)
Add instruction selection patterns for VBITSEL_V/XVBITSEL_V and
VBITSELI_B/XVBITSELI_B to match the canonical bitwise select idiom:
`(a & b) | (~a & c)`
This enables the backend to generate dedicated bitwise select
instructions instead of separate AND/ANDN/OR sequences.
Commit: a94ad60e664bfef25a2d33e67beae7393a8dcb24
https://github.com/llvm/llvm-project/commit/a94ad60e664bfef25a2d33e67beae7393a8dcb24
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
Log Message:
-----------
[AMDGPU] Preserve old MSBs when handling SETREG (#191352)
Commit: b2dda8cd34c39cd899b5fed1c6a6e56ad39906c6
https://github.com/llvm/llvm-project/commit/b2dda8cd34c39cd899b5fed1c6a6e56ad39906c6
Author: NeKon69 <nobodqwe at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
Log Message:
-----------
[LifetimeSafety] Add placement new support (#194030)
Allows flow from placement new closely resembling standard library form.
Comes as part of the completion of #164963.
Commit: f966490e30698f4cceb184cf28f6b5162338ef57
https://github.com/llvm/llvm-project/commit/f966490e30698f4cceb184cf28f6b5162338ef57
Author: Dark Steve <Prasoon.Mishra at amd.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
Log Message:
-----------
[AMDGPU] Extend max3/min3 tree-reduction combine to cover ternary chains (#194845)
The tree-reduction combine for min/max currently trigger on shapes where
both children of a node are same-opcode. This patch extends it to also
recognize cases where only one child is same-opcode and one-use like
max(max(a, b), c) feeding another max.
For example, with R = max(max(A, B), C) where A, B, and C are each
ternary chains of the form max(max(x, y), z), the current predicate does
not recognize the ternary-chain interiors as still combinable, so the
higher-level rules fire eagerly and produce max3 nodes with 2-op maxes
inside them. With the extended predicate, each ternary chain is allowed
to fold into a max3 first, after which the higher levels reduce cleanly
without leaving stranded 2-op maxes behind.
Adds six regression tests covering a 2-level ternary chain, a mixed
ternary+binary shape and vector examples.
Fix: LCOMPILER-2166
Commit: f7d40320a00dbdc2eafc986a06da21809516ae9f
https://github.com/llvm/llvm-project/commit/f7d40320a00dbdc2eafc986a06da21809516ae9f
Author: nataliakokoromyti <nataliakokoromyti at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/ObjCopy/ConfigManager.cpp
Log Message:
-----------
[ObjCopy] Reject compress-debug-sections for non-ELF (#191314)
`--compress-debug-sections` is currently an ELF-only option in the
[docs](https://llvm.org/docs/CommandGuide/llvm-objcopy.html#cmdoption-llvm-objcopy-compress-debug-sections)
but in `llvm-objcopy`, non-ELF backends were silently ignoring it, while
`--decompress-debug-sections` already
[reports](https://github.com/llvm/llvm-project/blob/89446086eaed6f07e2c122396570f2985cec62e5/llvm/lib/ObjCopy/ConfigManager.cpp#L32)
unsupported-option error. This PR makes behavior consistent by treating
`--compress-debug-sections` and `--compress-sections` as unsupported for non-ELF formats too.
Commit: a8eb65a909ee7858bbc596447e26d3a7c8c3adb7
https://github.com/llvm/llvm-project/commit/a8eb65a909ee7858bbc596447e26d3a7c8c3adb7
Author: gretay-amd <gretay.amd at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
Log Message:
-----------
[AMDGPU][NFC] Use LaneMaskConstants for waterfall loops in AMDGPURegBankLegalizeHelper (#190792)
Use `LaneMaskConstants` for generating waterfall loops in
`AMDGPURegBankLegalizeHelper`.
No Functionality Change.
Commit: f7e133dfedb0ece98bce63db0c06507423b11d73
https://github.com/llvm/llvm-project/commit/f7e133dfedb0ece98bce63db0c06507423b11d73
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M .ci/all_requirements.txt
M lldb/test/CMakeLists.txt
M lldb/test/requirements.txt
Log Message:
-----------
[lldb] Add Python cryptography package as new test dependency (#192434)
HTTPS tests for SymbolLocatorSymStore need the Python cryptography package
Commit: 312d8823c61693fe097dd8c9104a37847775e772
https://github.com/llvm/llvm-project/commit/312d8823c61693fe097dd8c9104a37847775e772
Author: Lang Hames <lhames at gmail.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/COFF.h
M llvm/lib/ExecutionEngine/JITLink/COFF.cpp
M llvm/lib/ExecutionEngine/JITLink/COFFLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/COFFLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/unittests/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/unittests/ExecutionEngine/JITLink/COFFLinkGraphTests.cpp
Log Message:
-----------
[JITLink][COFF] Move GetImageBaseSymbol utility into public header. (#195041)
This utility may be useful for people writing
LinkGraphLinkingLayer::Plugins for COFF LinkGraphs, so this commit moves
it a public header where it can easily be reused
(llvm/ExecutionEngine/JITLink/COFF.h).
Also adds unit tests for the utility.
Commit: 08bafa396a3c21c615da117a828c73393cb20014
https://github.com/llvm/llvm-project/commit/08bafa396a3c21c615da117a828c73393cb20014
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/ctor-dtor-lowering.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_empty.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_intel.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_no_return.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/cooperative_matrix.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/trivial.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/masked-gather-scatter.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/vector-of-pointers-ptrtoint.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll
M llvm/test/CodeGen/SPIRV/legalization/icmp_extended_int.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
M llvm/test/CodeGen/SPIRV/pointers/nested-struct-opaque-pointers.ll
Log Message:
-----------
[NFC][SPIR-V] Re-enable spirv-val on tests that are passing validation (#195022)
Commit: dd99506d33a0ddceeed3e8bbd548babe38a49233
https://github.com/llvm/llvm-project/commit/dd99506d33a0ddceeed3e8bbd548babe38a49233
Author: Elio <xiongzile at bytedance.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
A clang/test/CIR/CodeGenCXX/virtual-base-cast.cpp
Log Message:
-----------
[CIR] Combined virtual + non-virtual base offset (#192617)
Refer: https://github.com/llvm/llvm-project/issues/192330
---------
Co-authored-by: Zile Xiong <xiongzile99 at gmail.com>
Commit: d50dd86a3ea374001fc3d8858e2140373b707843
https://github.com/llvm/llvm-project/commit/d50dd86a3ea374001fc3d8858e2140373b707843
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
Log Message:
-----------
AMDGPU/GlobalISel: Fix G_STRICT_FMUL f64 selection on GFX12 (#195050)
Commit: 2dbff02fad7e12ed3b15c72a2cb1a68e89c630c4
https://github.com/llvm/llvm-project/commit/2dbff02fad7e12ed3b15c72a2cb1a68e89c630c4
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/phi-to-phi.ll
Log Message:
-----------
[LoopInterchange] Fix handling of PHI which refers to another PHI (#194364)
In the transformation phase, at first LoopInterchange moves several
instructions in the inner loop into the new latch block. The
instructions used as incoming values to the induction variables from the
latch block are the targets of this movement. Previously, this process
could result in an infinite loop when a PHI node refers to another PHI
node, as in the following example:
```
%i = phi i64 [ 0, %entry ], [ %i.inc, %latch ]
%j = phi i64 [ 0, %entry ], [ %i, %latch ]
```
The root cause was that `%i` enqueued for processing because it is used
by `%j`.
This patch fixes the issue by preventing induction variables from being
enqueued into the movement list.
Fix #193733
Commit: d13c6584ddbf6dece24f6d2e8ed53cc495615236
https://github.com/llvm/llvm-project/commit/d13c6584ddbf6dece24f6d2e8ed53cc495615236
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/if-pred-not-when-safe.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
Log Message:
-----------
[LV][NFC] Remove unused -simplifycfg-*** option from tests (#195044)
The -simplifycfg-require-and-preserve-domtree=1 option used in two tests
had no effect.
Commit: 4fa68d749c33b4809017d01b699bc281d8a0a813
https://github.com/llvm/llvm-project/commit/4fa68d749c33b4809017d01b699bc281d8a0a813
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-04-30 (Thu, 30 Apr 2026)
Changed paths:
M .ci/all_requirements.txt
M clang-tools-extra/clang-tidy/bugprone/MoveForwardingReferenceCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/modularize/CoverageChecker.cpp
M clang-tools-extra/modularize/ModularizeUtilities.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/move-forwarding-reference.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/TargetInfo.cpp
M clang/lib/CIR/CodeGen/TargetInfo.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/test/AST/ByteCode/addr-label-diff.cpp
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/fixed-point.cpp
A clang/test/CIR/CodeGenCXX/virtual-base-cast.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-logb-scalbn.hip
A clang/test/CIR/IR/calling-conv.cir
A clang/test/CIR/Lowering/calling-conv.cir
M clang/test/CIR/Transforms/ternary.cir
M clang/test/CodeGen/ms-annotation.c
M clang/test/Parser/pragma-fenv_access.c
M clang/test/Sema/ms-annotation.c
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/OpenACC/locations.f90
M flang/test/Lower/OpenMP/location.f90
A flang/test/Lower/where-loc.f90
M libc/docs/CMakeLists.txt
M libc/docs/dev/undefined_behavior.rst
M libc/docs/headers/index.rst
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/thread.cpp
M libc/src/__support/threads/thread.h
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_join_test.cpp
A libc/utils/docgen/sys/ipc.yaml
M libcxx/include/CMakeLists.txt
M libcxx/include/__cxx03/cinttypes
M libcxx/include/__locale
M libcxx/include/__ostream/print.h
M libcxx/include/cinttypes
R libcxx/include/inttypes.h
M libcxx/include/ios
M libcxx/include/module.modulemap.in
M libcxx/include/print
M libcxx/src/ios.cpp
A libcxx/test/benchmarks/format/print.bench.cpp
A libcxx/test/libcxx/input.output/iostream.format/print.fun/output_unicode_windows.pass.cpp
R libcxx/test/libcxx/input.output/iostream.format/print.fun/vprint_unicode_windows.pass.cpp
M lldb/docs/use/variable.rst
M lldb/include/lldb/Breakpoint/BreakpointSite.h
M lldb/include/lldb/Target/Process.h
M lldb/source/Breakpoint/BreakpointSite.cpp
M lldb/source/Plugins/Process/AIX/NativeProcessAIX.cpp
M lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.cpp
M lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h
M lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp
M lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.h
M lldb/source/Plugins/Process/AIX/NativeThreadAIX.cpp
M lldb/source/Plugins/Process/AIX/NativeThreadAIX.h
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.h
M lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64.h
M lldb/source/Plugins/Process/Utility/StopInfoMachException.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp
M lldb/source/Plugins/Process/scripted/ScriptedThread.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/ThreadPlanStepOverBreakpoint.cpp
M lldb/test/CMakeLists.txt
M lldb/test/requirements.txt
M lldb/tools/yaml2macho-core/yaml2macho.cpp
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/MachineFunction.h
R llvm/include/llvm/CodeGen/WasmEHFuncInfo.h
A llvm/include/llvm/CodeGen/WasmEHInfo.h
M llvm/include/llvm/DWP/DWP.h
M llvm/include/llvm/DWP/DWPStringPool.h
A llvm/include/llvm/DWP/ELFWriter.h
M llvm/include/llvm/ExecutionEngine/JITLink/COFF.h
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Support/KnownFPClass.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinkerDeclContext.cpp
M llvm/lib/DWP/CMakeLists.txt
M llvm/lib/DWP/DWP.cpp
A llvm/lib/DWP/ELFWriter.cpp
M llvm/lib/ExecutionEngine/JITLink/COFF.cpp
M llvm/lib/ExecutionEngine/JITLink/COFFLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/COFFLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/ObjCopy/ConfigManager.cpp
M llvm/lib/Support/KnownFPClass.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/lib/Transforms/Instrumentation/MemProfInstrumentation.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/MemorySSA/pr43427.ll
M llvm/test/Analysis/MemorySSA/pr43438.ll
A llvm/test/Analysis/ScalarEvolution/or-exit-cond.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-andor-selectform.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-andor.ll
M llvm/test/CodeGen/AArch64/adc.ll
M llvm/test/CodeGen/AArch64/addp-shuffle.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
M llvm/test/CodeGen/AArch64/fcmp-fp128.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/shift-logic.ll
M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
M llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
A llvm/test/CodeGen/LoongArch/lasx/bitsel.ll
A llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
A llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll
M llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll
A llvm/test/CodeGen/LoongArch/lsx/bitsel.ll
M llvm/test/CodeGen/SPIRV/ctor-dtor-lowering.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_empty.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_intel.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_no_return.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/cooperative_matrix.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/trivial.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/masked-gather-scatter.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/vector-of-pointers-ptrtoint.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll
M llvm/test/CodeGen/SPIRV/legalization/icmp_extended_int.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
M llvm/test/CodeGen/SPIRV/pointers/nested-struct-opaque-pointers.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
M llvm/test/CodeGen/WebAssembly/function-info.mir
M llvm/test/CodeGen/WebAssembly/multivalue-dont-move-def-past-use.mir
A llvm/test/CodeGen/X86/elf-section-properties.ll
A llvm/test/CodeGen/X86/sdag-extload-combine-crash.ll
A llvm/test/DebugInfo/X86/sdag-load-sext-trunc.ll
A llvm/test/DebugInfo/X86/sdag-load-sext.ll
A llvm/test/DebugInfo/X86/sdag-load-zext-multiple-args.ll
A llvm/test/Transforms/IndVarSimplify/or-exit-cond.ll
M llvm/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/guards.ll
M llvm/test/Transforms/LICM/hoist-debuginvariant.ll
A llvm/test/Transforms/LICM/hoist-inaccesiblemem-call.ll
M llvm/test/Transforms/LICM/invariant.start.ll
M llvm/test/Transforms/LICM/pr50367.ll
M llvm/test/Transforms/LICM/pr59324.ll
M llvm/test/Transforms/LICM/store-hoisting.ll
A llvm/test/Transforms/LoopInterchange/phi-to-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/max-vf-for-interleaved.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/global_alias.ll
M llvm/test/Transforms/LoopVectorize/if-pred-not-when-safe.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/tbaa-nodep.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
A llvm/test/Verifier/elf-section-properties.ll
A llvm/test/tools/dsymutil/X86/odr-simple-template-names-mixed.test
A llvm/test/tools/dsymutil/X86/odr-simple-template-names.test
M llvm/test/tools/llvm-dwp/WebAssembly/simple_dwo.s
M llvm/tools/llvm-dwp/CMakeLists.txt
M llvm/tools/llvm-dwp/llvm-dwp.cpp
M llvm/unittests/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/unittests/ExecutionEngine/JITLink/COFFLinkGraphTests.cpp
M llvm/unittests/Transforms/Vectorize/VPlanPatternMatchTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DWP/BUILD.gn
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/Transforms/Passes.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/include/mlir/Transforms/RegionUtils.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTosaOps.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Transforms/CMakeLists.txt
A mlir/lib/Transforms/TrivialDeadCodeElimination.cpp
M mlir/lib/Transforms/Utils/RegionUtils.cpp
M mlir/python/mlir/dialects/_ods_common.py
M mlir/python/mlir/dialects/transform/structured.py
M mlir/test/CAPI/ir.c
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/EmitC/form-expressions.mlir
M mlir/test/Dialect/Linalg/transform-op-fuse.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/Cpp/member.mlir
A mlir/test/Transforms/dead-code-elimination.mlir
M mlir/test/python/dialects/transform_structured_ext.py
M mlir/test/python/ir/location.py
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/NativeDylibManager.h
A orc-rt/include/orc-rt/sps-ci/NativeDylibManagerSPSCI.h
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/NativeDylibManager.cpp
A orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
A orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
M orc-rt/unittests/CMakeLists.txt
A orc-rt/unittests/Inputs/NativeDylibManagerTestLib.cpp
A orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
A orc-rt/unittests/NativeDylibManagerTest.cpp
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/kparzysz/dsa-conflicts
Compare: https://github.com/llvm/llvm-project/compare/2f964578b2af...4fa68d749c33
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