[all-commits] [llvm/llvm-project] 63c052: [RISCV] Use BufferSize = 0 for ProcResGroup in SiF...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 63c0520082767bd9006d7c97c71d0284df160921
      https://github.com/llvm/llvm-project/commit/63c0520082767bd9006d7c97c71d0284df160921
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-04-29 (Wed, 29 Apr 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
    M llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir

  Log Message:
  -----------
  [RISCV] Use BufferSize = 0 for ProcResGroup in SiFive7 scheduling models (#194754)

As it turns out, even if a `ProcResGroup` consists of in-order pipes, as
long as its (the group's) BufferSize is not zero, Machine Scheduler will
not use in-order scheduling on instructions that consume it. Since
BufferSize also defaults to -1 for `ProcResGroup`, we have been
scheduling the resource consumption of SiFive7's `PipeAB` (scalar pipes)
and `VA1OrVA2` (vector pipes) in an out-of-order fashion!

Co-authored-by: Min Hsu <min.hsu at sifive.com>



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