[all-commits] [llvm/llvm-project] 0d97b5: [CIR][AArch64] Lower NEON zip1/2 elements intrinsi...

[Jiahao Guo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d97b5a084f93b4a48f93895baedcf9ab998ec85
      https://github.com/llvm/llvm-project/commit/0d97b5a084f93b4a48f93895baedcf9ab998ec85
  Author: Jiahao Guo <eoonguo at gmail.com>
  Date:   2026-04-29 (Wed, 29 Apr 2026)

  Changed paths:
    M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
    M clang/test/CodeGen/AArch64/neon-perm.c
    A clang/test/CodeGen/AArch64/neon/perm.c
    M clang/test/CodeGen/AArch64/poly64.c

  Log Message:
  -----------
  [CIR][AArch64] Lower NEON zip1/2 elements intrinsics (#194311)

### Summary

part of : https://github.com/llvm/llvm-project/issues/185382

This is a follow up : https://github.com/llvm/llvm-project/pull/193658

Lower zip1 and zip2 intrinsics in
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#zip-elements

All the intrinsics are handled inline in
`llvm-project/build/lib/clang/23/include/arm_neon.h` like:
```
#ifdef __LITTLE_ENDIAN__
__ai __attribute__((target("neon"))) int8x8_t vzip1_s8(int8x8_t __p0, int8x8_t __p1) {
  int8x8_t __ret;
  __ret = __builtin_shufflevector(__p0, __p1, 0, 8, 1, 9, 2, 10, 3, 11);
  return __ret;
}
#else
__ai __attribute__((target("neon"))) int8x8_t vzip1_s8(int8x8_t __p0, int8x8_t __p1) {
  int8x8_t __ret;
  int8x8_t __rev0;  __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_8);
  int8x8_t __rev1;  __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_8);
  __ret = __builtin_shufflevector(__rev0, __rev1, 0, 8, 1, 9, 2, 10, 3, 11);
  __ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_8);
  return __ret;
}
#endif
```
So no additional special lowering logic is needed.



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