[all-commits] [llvm/llvm-project] 81545f: [RISC-V][RVY] Add a DataLayout component for CHERI...

[Alexander Richardson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 81545fa56c2b9d9a022c91e6ef8a51a27543e325
      https://github.com/llvm/llvm-project/commit/81545fa56c2b9d9a022c91e6ef8a51a27543e325
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2026-04-28 (Tue, 28 Apr 2026)

  Changed paths:
    M llvm/lib/TargetParser/TargetDataLayout.cpp
    A llvm/test/CodeGen/RISCV/rvy/datalayout.ll

  Log Message:
  -----------
  [RISC-V][RVY] Add a DataLayout component for CHERI capabilities

This adds a new pointer address space to the data layout when RVY is
enabled, making use of the new 'e' flag for pointers with
[external state](https://github.com/llvm/llvm-project/pull/105735).
I chose address space 200 since that is what has been used in the
downstream CHERI forks for the past decade and therefore makes it slightly
easier to upstream tests, etc. but am happy to use any other value if that
is preferred. We can look at the ABI name parameter to detect
pure-capability ABIs, so this does not support the "hybrid" CHERI case that
is supported downstream where capability registers are supported (i.e.
the AS200 pointer attributes exist in the data layout), but the default
address spaces are still integers instead of AS200.
to handle the "hybrid" case where only some pointers use Y registers.

Reviewed By: topperc, lenary

Pull Request: https://github.com/llvm/llvm-project/pull/177249



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