[all-commits] [llvm/llvm-project] 378b41: [clang][AArch64][SVE2p3][SME2p3] Add intrinsics fo...

[Amilendra Kodithuwakku via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 378b411cf20051e3c3b654eab4347523f7da603f
      https://github.com/llvm/llvm-project/commit/378b411cf20051e3c3b654eab4347523f7da603f
  Author: Amilendra Kodithuwakku <amilendra.kodithuwakku at arm.com>
  Date:   2026-04-28 (Tue, 28 Apr 2026)

  Changed paths:
    M clang/include/clang/Basic/arm_sve.td
    A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_qrshr.c
    A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_qshr.c
    M clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
    A clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
    A clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_qshrn.cpp
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-qrshr.ll
    A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-qshr.ll

  Log Message:
  -----------
  [clang][AArch64][SVE2p3][SME2p3] Add intrinsics for v9.7a shift operations (#186087)

Add the following new clang intrinsics based on the ACLE specification
https://github.com/ARM-software/acle/pull/428 (Add alpha support for 9.7
data processing intrinsics)

Multi-vector saturating rounding shift right narrow and interleave
instructions
- SQRSHRN
- svint8_t svqrshrn_s8(svint16x2_t, uint64_t) / svint8_t
svqrshrn_n_s8_s16_x2(svint16x2_t, uint64_t)

- UQRSHRN
- svuint8_t svqrshrn_u8(svuint16x2_t, uint64_t) / svuint8_t
svqrshrn_n_u8_u16_x2(svuint16x2_t, uint64_t)

- SQRSHRUN
- svuint8_t svqrshrun_u8(svint16x2_t, uint64_t) / svuint8_t
svqrshrun_n_u8_s16_x2(svint16x2_t, uint64_t)

Multi-vector saturating shift right narrow and interleave
- SQSHRN
- svint8_t svqshrn_s8(svint16x2_t, uint64_t) / svint8_t
svqshrn_n_s8_s16_x2(svint16x2_t, uint64_t)
- svint16_t svqshrn_s16(svint32x2_t, uint64_t) / svint16_t
svqshrn_n_s16_s32_x2(svint32x2_t, uint64_t)

- UQSHRN
- svuint8_t svqshrn_u8(svuint16x2_t, uint64_t) / svuint8_t
svqshrn_n_u8_u16_x2(svuint16x2_t, uint64_t)
- svuint16_t svqshrn_u16(svuint32x2_t, uint64_t) / svuint16_t
svqshrn_n_u16_u32_x2(svuint32x2_t, uint64_t)

- SQSHRUN
- svuint8_t svqshrun_u8(svint16x2_t, uint64_t) / svuint8_t
svqshrun_n_u8_s16_x2(svint16x2_t, uint64_t)
- svuint16_t svqshrun_u16(svint32x2_t, uint64_t) / svuint16_t
svqshrun_n_u16_s32_x2(svint32x2_t, uint64_t)



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