[all-commits] [llvm/llvm-project] 4f6b1b: [LangRef][AMDGPU] Specify that syncscope can cause...

[Fabian Ritter via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f6b1b01f62f1bcce3192c60905904b3e965f128
      https://github.com/llvm/llvm-project/commit/4f6b1b01f62f1bcce3192c60905904b3e965f128
  Author: Fabian Ritter <fabian.ritter at amd.com>
  Date:   2026-04-28 (Tue, 28 Apr 2026)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst
    M llvm/docs/LangRef.rst

  Log Message:
  -----------
  [LangRef][AMDGPU] Specify that syncscope can cause atomic operations to race (#189015)

Targets should be able to specify that the syncscope of atomic operations
influences whether they participate in data races with each other.

For example, in AMDGPU, we want (and already implement) the load in the
following case to be in a data race (i.e., return `undef` according to the
current definition), because there is an atomic store with workgroup syncscope
executing in a different workgroup:

```
; workgroup 0:
  store atomic i32 1, ptr %p syncscope("workgroup") monotonic, align 4

; workgroup 1:
  store atomic i32 2, ptr %p syncscope("workgroup") monotonic, align 4
  load atomic i32, ptr %p syncscope("workgroup") monotonic, align 4
```

This is consistent with the behavior of, e.g., [heterogeneous-race-free (HRF)
memory models](https://research.cs.wisc.edu/multifacet/papers/asplos14_hrf.pdf) and the [HSA memory model](https://hsafoundation.com/standards/).

Related RFC: https://discourse.llvm.org/t/rfc-clarifying-llvm-irs-concurrent-memory-model/90480



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