[all-commits] [llvm/llvm-project] fa8ec3: [PowerPC] Further refactor atomic loads

[Kai Nacke via All-commits]

  Branch: refs/heads/users/redstar/ppcatomicload2
  Home:   https://github.com/llvm/llvm-project
  Commit: fa8ec3bfd815e04e7ca79dfe631d9743b1276c68
      https://github.com/llvm/llvm-project/commit/fa8ec3bfd815e04e7ca79dfe631d9743b1276c68
  Author: Kai Nacke <kai.peter.nacke at ibm.com>
  Date:   2026-04-27 (Mon, 27 Apr 2026)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td

  Log Message:
  -----------
  [PowerPC] Further refactor atomic loads

Depending on the availability of the word-part feature, different code
is generated for 1 and 2 byte atomic loads. This change moves the decision
to use the word-part feature from C++ into TableGen patterns. This is done
via:

 - move code from `EmitPartwordAtomicBinary()` into new function
   'signExtendOperandIfUnknown()'
 - decouple functions `EmitPartwordAtomicBinary()` and `EmitAtomicBinary()`
 - remove the size from the name of the pseudo instructions; instead,
   introduce a pseudo instruction which is used in case the word-part
   feature is missing
 - update the handling of the pseudo instruction insertion accordingly

A side effect of this change is the implementation requires 11 pseudo
instructions less.



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