[all-commits] [llvm/llvm-project] 7b43dc: [AArch64] Add disjoint or tests for rshrn and radd...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Mon Apr 27 11:00:03 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpvectorize-operand-chains-of-non-vectorizable-instructions
Home: https://github.com/llvm/llvm-project
Commit: 7b43dcd755e4d0cb18326f81080daa642ff4e630
https://github.com/llvm/llvm-project/commit/7b43dcd755e4d0cb18326f81080daa642ff4e630
Author: David Green <david.green at arm.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
Log Message:
-----------
[AArch64] Add disjoint or tests for rshrn and raddhn. NFC (#194252)
These should already be OK, as the os disjoint or connot round up.
Commit: fbac55b82be9bf849d8a9c2514c01cb24a2a264f
https://github.com/llvm/llvm-project/commit/fbac55b82be9bf849d8a9c2514c01cb24a2a264f
Author: JP Hafer <146973677+jph-13 at users.noreply.github.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
A llvm/test/CodeGen/AArch64/scvtf-div-mul-combine.ll
Log Message:
-----------
[AArch64] Optimize vector fmul(sitofp/uitofp, 1/2^N) -> scvtf/ucvtf (#141480)
When a vector integer-to-float conversion is followed by a multiply with a
reciprocal power-of-two constant, we can fold both operations into a single
SCVTF or UCVTF instruction with a fixed-point shift operand.
For example, `fmul(sitofp(v2i32 x), <0.5, 0.5>)` becomes `scvtf.2s v0, v0, #1`.
This is a reworked version with several improvements over the original
submission:
- Rewrite the C++ operand matcher to share implementation with the existing
`SelectCVTFixedPointVec` (MOVIshift, FMOV, and DUP handling with correct
truncation for f16)
- Add `uitofp`/`ucvtf` patterns via a `CVTFRecipPat` multiclass
- Add full GlobalISel support (`GIComplexOperandMatcher` + renderer)
Supported vector types: `v2f32`, `v4f32`, `v2f64`, `v4f16`, `v8f16`.
Fixes #94909
Commit: 694f1b425ae370e5fc615038dba90cb1cfcadd30
https://github.com/llvm/llvm-project/commit/694f1b425ae370e5fc615038dba90cb1cfcadd30
Author: Christoph Grüninger <foss at grueninger.de>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
Remove GitHub Action seanmiddleditch/gha-setup-ninja (#194218)
>From the GitHubAction
[README](https://github.com/seanmiddleditch/gha-setup-ninja/blob/master/README.md):
"This action is no longer necessary, as ninja is now
included on all default GitHub runner instances."
Commit: 4e6d01dd5bc6d10166e8b8f1fbf36c862ca04e10
https://github.com/llvm/llvm-project/commit/4e6d01dd5bc6d10166e8b8f1fbf36c862ca04e10
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
[libcxx][Github] Bump libcxx runners to the next runner set (#194212)
To pick up some recent container changes that add additional tools for
the LLVM libc build.
Commit: a562a10f7379c158a858be0cabf52d9dca5fd1c4
https://github.com/llvm/llvm-project/commit/a562a10f7379c158a858be0cabf52d9dca5fd1c4
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPSessionManager.cpp
M lldb/tools/lldb-dap/EventHelper.cpp
Log Message:
-----------
lldb-dap: Fix race condition in event threads creation (#194012)
Move the registration of the SBListener to before
the event threads (`ProgressEventThread` and `EventThread`) start
This prevents a race condition where a stop event
could be missed if it was sent immediately after thread creation, which
would lead to a deadlock. It is most likely to happen under heavy CPU
load with test that fails early like
TestDAP_commands::test_command_directive_abort_on_error_init_commands.
Relevant logs.
```sh
# Event thread deadlock.
0x00007348BC000BE0 Listener('lldb-dap.progress.listener')::GetEventInternal, timeout = 1000000 us, event_mask = 0
0x00005b72419d1640 Broadcaster("lldb-dap")::BroadcastEvent (event_sp = 0x5b7241eebb60 Event: broadcaster = 0x5b72418e0df0 (lldb-dap), type = 0x00000001, data = <NULL>, unique=false) hijack = 0x0000000000000000
0x00005B7241898440 Listener('lldb.Debugger')::GetEventInternal, timeout = 1000000 us, event_mask = 0
0x7348bc000be0 Listener::GetEventInternal() timed out for lldb-dap.progress.listener
0x00007348BC000BE0 Listener('lldb-dap.progress.listener')::GetEventInternal, timeout = 1000000 us, event_mask = 0
```
```sh
# Progress thread deadlock.
0x000057798AB6B440 Listener('lldb.Debugger')::GetEventInternal, timeout = <infinite>, event_mask = 0
0x000057798aca4640 Broadcaster("lldb-dap")::BroadcastEvent (event_sp = 0x57798b0b9d80 Event: broadcaster = 0x57798abb3df0 (lldb-dap), type = 0x00000001, data = <NULL>, unique=false) hijack = 0x0000000000000000
0x57798ab6b440 Listener('lldb.Debugger')::AddEvent (event_sp = {0x57798b0b9d80})
0x57798ab6b440 'lldb.Debugger' Listener::FindNextEventInternal(broadcaster=(nil), event_type_mask=0x00000000, remove=1) event 0x57798b0b9d80
0x000057798aca4640 Broadcaster("lldb-dap")::BroadcastEvent (event_sp = 0x57798b1be800 Event: broadcaster = 0x57798abb3df0 (lldb-dap), type = 0x00000002, data = <NULL>, unique=false) hijack = 0x0000000000000000
0x000078023C000BE0 Listener('lldb-dap.progress.listener')::GetEventInternal, timeout = <infinite>, event_mask = 0
```
Commit: 8f65ad583a019cde822b19cf24b0df68a5242792
https://github.com/llvm/llvm-project/commit/8f65ad583a019cde822b19cf24b0df68a5242792
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/load.ll
Log Message:
-----------
[ConstantFolding] Fold byte loads from constant globals (#194074)
Handle byte types in `FoldReinterpretLoadFromConst` and
`ConstantFoldLoadFromUniformValue` so loads from constant globals fold.
Commit: 3b20615594360fdb0f0e328d0d83ae572474b370
https://github.com/llvm/llvm-project/commit/3b20615594360fdb0f0e328d0d83ae572474b370
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/VPlan/widen-canonical-iv-register-pressure.ll
A llvm/test/Transforms/LoopVectorize/X86/widen-canonical-iv-register-pressure.ll
Log Message:
-----------
[LV] Add test cases where wide IV can cause spills. (#194260)
Add test cases showing cases where replacing VPWidenCanonicalIVRecipe
with VPWidenIntOrFPinductionPHIRecipe is profitable/not profitable due
to introducing spills.
Commit: 544d003630475c65f6d85d1edb4467e9d7a16c0f
https://github.com/llvm/llvm-project/commit/544d003630475c65f6d85d1edb4467e9d7a16c0f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
Log Message:
-----------
[VPlan] Use RUN_VPLAN_PASS for later VPlan transforms. (#194261)
Convert a number of later VPlan transform invocations to use
RUN_VPLAN_PASS. Enables more accurate transform printing, as well as
extra verification.
This should migrate all remaining transforms that can be moved without
changes.
Commit: 28c4c25c0cdf4bb41059fb48927f0f866b72bd5a
https://github.com/llvm/llvm-project/commit/28c4c25c0cdf4bb41059fb48927f0f866b72bd5a
Author: Midhunesh <midhunesh.p at ibm.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_dlsym.h
Log Message:
-----------
[Asan]Add align argument to Realloc() (#194255)
Add align argument to the function Realloc() to ensure original
allocation alignment through realloc
Commit: 4ef52fe4652810ca816250b00c996d65672dd2d0
https://github.com/llvm/llvm-project/commit/4ef52fe4652810ca816250b00c996d65672dd2d0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libcxx] Remove package installation for generic-llvm-libc (#194259)
Now that these packages are installed by default in the container image,
we no longer need to install them each time we do a build.
Commit: 13cee9be088057f198e08ee7217ed2af08cfd825
https://github.com/llvm/llvm-project/commit/13cee9be088057f198e08ee7217ed2af08cfd825
Author: martin0413133 <129967631+martin0413133 at users.noreply.github.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
Log Message:
-----------
[sanitizer] Fix race condition in GetNamedMappingFd with decorate_pro… (#190981)
…c_maps=1
Multi-threaded programs crash randomly when
ASAN_OPTIONS=decorate_proc_maps=1 is enabled due to filename collision
in /dev/shm.
Root Cause:
All threads use the same filename format '/dev/shm/<PID> [name]',
causing race conditions where one thread deletes a file created by
another thread, resulting in ENOENT errors.
Solution:
Add thread ID (TID) to the filename to ensure uniqueness:
- Old format: /dev/shm/<PID> [name]
- New format: /dev/shm/<PID>.<TID> [name]
This ensures each thread has a unique filename, eliminating the race
condition.
Testing:
- Original version: 30% crash rate (6 crashes in 20 runs)
- Fixed version: 0% crash rate (0 crashes in 50 runs)
Fixes #190604
Commit: 57494cc7b4e8b59714ee9e312812d8421f41d27c
https://github.com/llvm/llvm-project/commit/57494cc7b4e8b59714ee9e312812d8421f41d27c
Author: Thurston Dang <thurston at google.com>
Date: 2026-04-26 (Sun, 26 Apr 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
Log Message:
-----------
Revert "[sanitizer] Fix race condition in GetNamedMappingFd with decorate_pro…" (#194271)
Reverts llvm/llvm-project#190981 due to buildbot failure
(https://lab.llvm.org/buildbot/#/builders/66/builds/29993):
```
SanitizerCommon-asan-i386-Linux :: Linux/decorate_proc_maps.cpp
```
Commit: 652700b4cb3c87294f2d78cb87df5e394e589984
https://github.com/llvm/llvm-project/commit/652700b4cb3c87294f2d78cb87df5e394e589984
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
Log Message:
-----------
Reland "[sanitizer] Fix race condition in GetNamedMappingFd with decorate_pro…"" (#194273)
Reverts llvm/llvm-project#194271
Relands llvm/llvm-project#190981.
ThreadID is u64, format must be `%llu`.
Commit: 09306f776fc04272e3ef8a5fdb09b06a84713ffd
https://github.com/llvm/llvm-project/commit/09306f776fc04272e3ef8a5fdb09b06a84713ffd
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_add, vp_mul, vp_sub (#194173)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off 3 intrinsics from #179622. These are expanded and
removed in lockstep so we don't break the multiply-accumulate patterns.
Commit: ef09defc0f4d2a0e52e4d4bd2239088241310051
https://github.com/llvm/llvm-project/commit/ef09defc0f4d2a0e52e4d4bd2239088241310051
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
Log Message:
-----------
[test][AMDGPU] Precommit test for Back-propagate wqm for sources of side-effect instruction (#193394)
Commit: e042f67503e5cbf0480b3c24719c3a57dde1453b
https://github.com/llvm/llvm-project/commit/e042f67503e5cbf0480b3c24719c3a57dde1453b
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
A llvm/test/CodeGen/LoongArch/stackslot.mir
Log Message:
-----------
[LoongArch] Override `isLoadFromStackSlot/isStoreToStackSlot` to expose more optimizations (#164561)
Commit: db572086d0bb11b59004b2f27bfad03669a9c7db
https://github.com/llvm/llvm-project/commit/db572086d0bb11b59004b2f27bfad03669a9c7db
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/CodeGen/X86/machine-block-hash.mir
Log Message:
-----------
[X86] Mark machine-block-hash.mir as XFAIL on big-endian hosts (#194279)
Test introduced in #193107 assumes `stable_hash_combine` is stable,
but it turns out it's not true.
Commit: 41236fb837ecf9fbf632d158833ec5edac509799
https://github.com/llvm/llvm-project/commit/41236fb837ecf9fbf632d158833ec5edac509799
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/test/Transforms/GVN/tbaa.ll
Log Message:
-----------
[GVN] Propagate isMemorySSAEnabled() into ValueTable (#193938)
`GVNPass::runImpl()` calls `VN.setMemorySSA(MSSA)` with a single
argument. The second parameter of `ValueTable::setMemorySSA()`,
`MSSAEnabled`, defaults to `false`, so `ValueTable::IsMSSAEnabled`
remains false even when the pass is configured with
`-enable-gvn-memoryssa=1` or `-passes='gvn<memoryssa>'`.
The MemorySSA-backed value-numbering paths in
`ValueTable::lookupOrAddCall()` and `ValueTable::computeLoadStoreVN()`
are gated on `IsMSSAEnabled`, making them unreachable from runImpl() on
main today.
This patch forwards isMemorySSAEnabled() as the second argument to
setMemorySSA(), so selecting the MemorySSA backend actually enables
MemorySSA-aware value numbering.
Commit: 2a09db4d6a6ab6281b8b52f5057fe89fe0935d23
https://github.com/llvm/llvm-project/commit/2a09db4d6a6ab6281b8b52f5057fe89fe0935d23
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
Log Message:
-----------
AMDGPU: Back-propagate wqm for sources of side-effect instruction (#193395)
For readfirstlane instruction, as it would get undefined value if exec
is zero. To handle the case that only helper lanes execute the parent
block, we let the readfirstlane to execute under wqm. But this is not
enough. If the parent block was also executed by non-helper lanes, we
also need to make sure its sources were calculated under wqm. Otherwise,
if the instruction that generate the source of readfirstlane was
executed under exact mode, the value would contain garbage data in help
lane. The garbage data in helper lane maybe returned by the
readfirstlane running under wqm.
To fix this issue, we need to enforce the back-propagation of wqm for
instructions like readfirstlane. This was only done if the instruction
was possibly in the middle of wqm region (by checking OutNeeds).
Commit: 504930b655af9a49c0596b2aa68f1b763a599bab
https://github.com/llvm/llvm-project/commit/504930b655af9a49c0596b2aa68f1b763a599bab
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/CodeGen/X86/machine-block-hash.mir
Log Message:
-----------
[X86] Remove update_mir_test_checks.py NOTE (#194278)
The test checks printer output, not MIR.
It was probably copy-pasted in #193107 from other test.
Commit: 1f9c611b0997205568f226e0f0ecd22cb96e4f77
https://github.com/llvm/llvm-project/commit/1f9c611b0997205568f226e0f0ecd22cb96e4f77
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/Transforms/LoopFusion/double_loop_nest_inner_guard.ll
M llvm/test/Transforms/LoopFusion/triple_loop_nest_inner_guard.ll
Log Message:
-----------
[LoopFusion][NFC] UTC gen some tests (#193755)
Some variables need rename as UTC normalizes IR value names. Also,
remove dead variable `%M` and `%N` from
`double_loop_nest_inner_guard.ll`
Commit: 4d2d6a0d92e068a367168706fb768f9dd1c0ad8a
https://github.com/llvm/llvm-project/commit/4d2d6a0d92e068a367168706fb768f9dd1c0ad8a
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fpext.ll
M llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
Log Message:
-----------
[LoongArch] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector (#164943)
On 64-bit targets the generic legalize will use an i64 load and a
scalar_to_vector for us. But on 32-bit targets, i64 isn't legal, and the
generic legalizer will end up emitting two 32-bit loads. This patch uses
f64 to avoid the splitting entirely and the redundant int->fp
conversion.
Commit: 4ab33dc39b569f2e33eeec24c2c5c9ae013fe5ea
https://github.com/llvm/llvm-project/commit/4ab33dc39b569f2e33eeec24c2c5c9ae013fe5ea
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_select (#194199)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off vp.select from #179622
Commit: bee932f0c98d720b66994cb6500d227d219110b8
https://github.com/llvm/llvm-project/commit/bee932f0c98d720b66994cb6500d227d219110b8
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
A llvm/test/CodeGen/NVPTX/unknown-intrinsic.ll
Log Message:
-----------
[NVPTX] Improve error diagnostic when handling unknown intrinsics (#191194)
Following up on #146726, it may be desirable to gracefully fail the
compilation in the presence of unknown NVVM intrinsics, which
cannot be lowered by the NVPTX backend, rather than silently
emitting invalid PTX.
Commit: 30c5cfd5b78010146bfd06d19083dfa9c76bbc1a
https://github.com/llvm/llvm-project/commit/30c5cfd5b78010146bfd06d19083dfa9c76bbc1a
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_is_fpclass (#193222)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off vp_is_fpclass from #179622.
Commit: 9b787812e1700800fc927f104c5911aebdaec6eb
https://github.com/llvm/llvm-project/commit/9b787812e1700800fc927f104c5911aebdaec6eb
Author: Chaitanya <Krishna.Sankisa at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add lowering for amdgcn_div_scale builtins (#192931)
Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/2050
This PR adds support for lowering of _builtin_amdgcn_div_scale* amdgpu
builtins to clangIR.
Followed similar lowering from reference clang->llvmir in
clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp.
Commit: 58f2c189c4232351bd22dfdbb7ab45e084406cca
https://github.com/llvm/llvm-project/commit/58f2c189c4232351bd22dfdbb7ab45e084406cca
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
A llvm/test/Transforms/InstCombine/shift-sub.ll
Log Message:
-----------
[InstCombine] Fold shift of a constant into a reverse shift (#192982)
C1 << (C2 - X) -> (C1 << C2) >> X
C1 << (C2 ^ X) -> (C1 << C2) >> X (if equivalent to the above)
C1 >> (C2 - X) -> (C1 >> C2) << X (right shift modes match)
C1 >> (C2 ^ X) -> (C1 >> C2) << X (if equivalent to the above)
Proof: https://alive2.llvm.org/ce/z/q-4soi
Commit: 8119f1854948b50358bbfaea08f207f51970f06c
https://github.com/llvm/llvm-project/commit/8119f1854948b50358bbfaea08f207f51970f06c
Author: Khem Raj <khem.raj at oss.qualcomm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M libcxxabi/src/cxa_personality.cpp
Log Message:
-----------
libcxxabi: declare __gnu_unwind_frame in cxa_personality (#189787)
ARM EHABI builds of libcxxabi fail with clang-22+ because
cxa_personality.cpp calls __gnu_unwind_frame without a visible
declaration, triggering:
error: use of undeclared identifier '__gnu_unwind_frame'
Add an extern "C" forward declaration before the EHABI unwind helper so
the source compiles correctly.
Signed-off-by: Khem Raj <khem.raj at oss.qualcomm.com>
Commit: f57f184f87d1caedc778bb1f1a972757083e998d
https://github.com/llvm/llvm-project/commit/f57f184f87d1caedc778bb1f1a972757083e998d
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Semantics/tools.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Semantics/tools.cpp
M flang/test/Lower/OpenMP/target-map-complex.f90
M flang/test/Lower/c-interoperability.f90
A flang/test/Lower/host_module_variable_instantiation.f90
A flang/test/Lower/proc_pointer_hidden_by_generic.f90
Log Message:
-----------
[flang] only instantiate required symbols from parent modules (#193689)
Currently lowering is instantiating (creating
fir.address_of/hlfir.declare) for all module variables from host module
and submodules (for instance, in the new
host_module_variable_instantiation.f90 test, a fir.address_of was
generated the unused var2 inside the procedure foo).
This created a lot of noise (and in the worst cases, compile time
performance issues), and also some extra complexity at least for OpenACC
where the IR acc routine ended up referencing globals that are no
actually needed, creating the need to copy them on the GPU or to have
custom logic to ignore the globals.
This patch addresses this by doing a visit of the parse tree to detect
the required symbols and only instantiate those.
Commit: 13e98d834101efd1794cdd026377c508293ee21b
https://github.com/llvm/llvm-project/commit/13e98d834101efd1794cdd026377c508293ee21b
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Core/BinaryContext.cpp
M clang/lib/Parse/ParseStmtAsm.cpp
M clang/tools/driver/cc1as_main.cpp
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
M lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp
M llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h
M llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCDisassembler/Disassembler.cpp
M llvm/lib/Object/ModuleSymbolTable.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/M68k/M68kMCInstLower.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
M llvm/tools/llvm-dwp/llvm-dwp.cpp
M llvm/tools/llvm-exegesis/lib/DisassemblerHelper.cpp
M llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
M llvm/tools/llvm-mc/llvm-mc.cpp
M llvm/tools/llvm-mca/llvm-mca.cpp
M llvm/tools/llvm-ml/Disassembler.cpp
M llvm/tools/llvm-ml/llvm-ml.cpp
M llvm/tools/llvm-objdump/MachODump.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
M llvm/tools/sancov/sancov.cpp
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/unittests/CodeGen/MachineOperandTest.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
M llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
M llvm/unittests/MC/AMDGPU/Disassembler.cpp
M llvm/unittests/MC/DwarfDebugFrameCIE.cpp
M llvm/unittests/MC/DwarfLineTableHeaders.cpp
M llvm/unittests/MC/DwarfLineTables.cpp
M llvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp
M llvm/unittests/MC/SystemZ/SystemZMCDisassemblerTest.cpp
M llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp
M llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp
M llvm/unittests/tools/llvm-mca/MCATestBase.cpp
M mlir/lib/Target/LLVM/ROCDL/Target.cpp
Log Message:
-----------
[MC] Take MCAsmInfo by reference in MCContext and TargetMachine. NFC (#194280)
Both MCContext::MCContext and TargetMachine::getMCAsmInfo treat
MCAsmInfo as a pointer that must be non-null. Make the contract
explicit:
* MCContext's constructor takes `const MCAsmInfo &MAI`.
* TargetMachine::getMCAsmInfo returns `const MCAsmInfo &`.
Make this change now since the MCContext ctor has recently been updated.
Commit: 796d2ec4165a063ab9d1512a769978313dc18bc7
https://github.com/llvm/llvm-project/commit/796d2ec4165a063ab9d1512a769978313dc18bc7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
M llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/PowerPC/masked-sdiv.ll
M llvm/test/CodeGen/PowerPC/masked-srem.ll
M llvm/test/CodeGen/PowerPC/masked-udiv.ll
M llvm/test/CodeGen/PowerPC/masked-urem.ll
M llvm/test/CodeGen/RISCV/rvv/incorrect-extract-subvector-combine.ll
M llvm/test/CodeGen/X86/dag-topological-sort.ll
M llvm/test/CodeGen/X86/pr134602.ll
Log Message:
-----------
[DAG] visitAND - attempt to fold (and buildvector(), buildvector()) -> buildvector() (#193987)
See if we can fold all elements of an AND of buildvectors: AND(-1,X) -> X, AND(0,X) -> 0, etc.
Companion to ##183032
Commit: cab0c0dd79b20ae1114a0b40f6756ab6d7c3b70b
https://github.com/llvm/llvm-project/commit/cab0c0dd79b20ae1114a0b40f6756ab6d7c3b70b
Author: Varad Rahul Kamthe <133588066+varadk27 at users.noreply.github.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[MLIR][NVVM] Add movmatrix Op (#193995)
Add `movmatrix` to MLIR NVVM dialect, which moves a row-major matrix across all threads in a warp and writes the
transposed elements to the destination.
Commit: dc19e4b0b6c9a10633958046d2e27b597ba7e37e
https://github.com/llvm/llvm-project/commit/dc19e4b0b6c9a10633958046d2e27b597ba7e37e
Author: Hao Ren <123687754+moomoohorse321 at users.noreply.github.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
Log Message:
-----------
[mlir][NVGPUToNVVM] Support BF16 mma.sync lowering (#194203)
Let NVGPUToNVVM to recognize BF16 MMA operand element types
Pack `vector<2xbf16>` fragments to `i32` before emitting
`nvvm.mma.sync`.
This matches the PTX operand encoding for `m16n8k16` BF16 MMA
instructions.
Add a conversion test for `nvgpu.mma.sync` `bf16xbf16` to `f32`
lowering.
Co-authored-by: Hao Ren <rhao8608 at gmail.com>
Commit: 2c39855fb790df3f75c9272311b6a8ecbb603a17
https://github.com/llvm/llvm-project/commit/2c39855fb790df3f75c9272311b6a8ecbb603a17
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sanitize_vec_pow.ll
Log Message:
-----------
[AArch64] Sanitise pow inputs using a target DAG combine (#192958)
Sometimes we see LLVM IR like this:
%pow = call fast <4 x float> @llvm.pow.v4f32(...)
%fcmp = fcmp fast ...
%res = select <4 x i1> %fcmp, <4 x float> %val, <4 x float> %pow
where the pow intrinsic is called unconditionally, but only certain
lanes of the result are used. In fact, LLVM actively encourages code
like this due to the intrinsic being marked as safe to speculatively
execute. However, we know when using certain vector libraries like
ArmPL that this can be very costly if the unused lanes would take
the pow call down an expensive path. For example, if an input to
pow is a special value (inf, NaN, -0) then it triggers slow special
case handling, and ultimately the result is going to be ignored
anyway. For this reason we prefer to sanitise the pow input to
use 'safe' values when we know the result is going to be discarded.
The above example LLVM IR would then look like
%fcmp = fcmp fast ...
%sel = select <4 x i1>, <4 x float> splat(float 1.0), ...
%pow = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %sel, ...)
%res = select <4 x i1> %fcmp, <4 x float> %val, <4 x float> %pow
where the value 1.0 is chosen due to the fact pow is known to always
return 1.0 for all powers.
Commit: 6b25ae4fed5f7bd75c2b1bc011aa3d5de3bd29c2
https://github.com/llvm/llvm-project/commit/6b25ae4fed5f7bd75c2b1bc011aa3d5de3bd29c2
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang-tools-extra/clangd/Config.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M llvm/include/llvm/ADT/FoldingSet.h
M llvm/include/llvm/ADT/STLExtras.h
M llvm/include/llvm/ADT/StableHashing.h
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/lib/Support/FoldingSet.cpp
M llvm/unittests/Support/xxhashTest.cpp
Log Message:
-----------
[ADT] Fix IWYU for hashing-adjacent files (#194297)
Add explicit includes so these files keep building after we trim
transitive includes from xxhash.h.
For example, FoldingSet.cpp calls llvm::uninitialized_copy, which is
declared in llvm/ADT/STLExtras.h and today reaches the file only
transitively.
Also drop the vestigial `#include "llvm/ADT/Hashing.h"` from
llvm/ADT/STLExtras.h — no name from Hashing.h is used there.
Commit: 3d893f3e232236749ed1988667d039369b3c98bf
https://github.com/llvm/llvm-project/commit/3d893f3e232236749ed1988667d039369b3c98bf
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
M llvm/test/Transforms/LoopVectorize/hints-trans.ll
M llvm/test/Transforms/LoopVectorize/scalable-trunc-min-bitwidth.ll
Log Message:
-----------
[LV][NFC] Remove instsimplify pass run from all tests (#193722)
The instsimplify pass was only giving minor incidental improvements that
aren't essential to what is being tested.
Commit: 7189c4bb83d90c383741a9480fceca9c7bf74b27
https://github.com/llvm/llvm-project/commit/7189c4bb83d90c383741a9480fceca9c7bf74b27
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/veclib-llvm.pow.ll
Log Message:
-----------
[AArch64][NFC] Fix veclib-llvm.pow.ll test to run all pre-isel passes (#193996)
Commit: 89894b67484694aeaaec9c6bac6a09d71c347e6f
https://github.com/llvm/llvm-project/commit/89894b67484694aeaaec9c6bac6a09d71c347e6f
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_cmsghdr.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/sys-socket-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_cmsghdr.h
M libc/include/sys/socket.yaml
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/sendmsg_recvmsg_test.cpp
Log Message:
-----------
[libc] Add struct cmsghdr and associated macros (#193756)
The macros are the main source of subtlety. The interesting aspects are:
- some implementations CMSG_ALIGN the size of struct cmsghdr, but this
is a noop. Instead of doing that, I added an assertion in the test.
- POSIX permits CMSG_NXTHDR to return null if the buffer has no space
for the data array, and this behavior differs between implementations.
This implementation does not do that in order to match CMSG_FIRSTHDR,
which doesn't have such an option.
- some implementations redirect the CMSG_NXTHDR macro to an (extern or
static inline) function. I implemented this inside the macro to avoid
having to define a (private ?) entry point for that function.
---------
Co-authored-by: Jeff Bailey <jbailey at raspberryginger.com>
Commit: 166c2418cf3e9c976f59e079e6a3400cc3c44c4b
https://github.com/llvm/llvm-project/commit/166c2418cf3e9c976f59e079e6a3400cc3c44c4b
Author: Adrian Kuegel <akuegel at google.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Add linkopts to adjust for changes in 9ec6788 (#194314)
We need to link against crypt32.lib to avoid linker errors on Windows.
Commit: 1fee6a1e04de55ec218f9f38cbf2f60fc43acd26
https://github.com/llvm/llvm-project/commit/1fee6a1e04de55ec218f9f38cbf2f60fc43acd26
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/new-delete.cpp
Log Message:
-----------
[clang][bytecode] Ignore GetPtrDerivedPop on non-record pointers (#194005)
Now that we do this for `GetPtrBase`, we need to do it here, too. This
broke in the attached test case, but fully fixing it requires some
seemingly unrelated changes to `delete` handling.
Commit: 521f55348a345952522b2ad14f9b4885c48a3f86
https://github.com/llvm/llvm-project/commit/521f55348a345952522b2ad14f9b4885c48a3f86
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 89894b6 (#194321)
This fixes 89894b67484694aeaaec9c6bac6a09d71c347e6f.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 3aed0816fed922391ed0638f67ea8b6d09bebbdc
https://github.com/llvm/llvm-project/commit/3aed0816fed922391ed0638f67ea8b6d09bebbdc
Author: Usha Gupta <usha.gupta at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
A llvm/test/Transforms/AggressiveInstCombine/fold-split-ctlz.ll
A llvm/test/Transforms/AggressiveInstCombine/fold-split-cttz.ll
Log Message:
-----------
[AggressiveInstCombine] Fold split-width i32 cttz/ctlz patterns into wide i64 intrinsics (#192296)
This patch teaches `AggressiveInstCombine ` to recognize and fold common split-width i32 cttz/ctlz intrinsic calls into a single full-width i64
cttz/ctlz intrinsic.
For ex:
```
define i32 @src(i64 %val) {
%lo = trunc i64 %val to i32
%cmp = icmp eq i32 %lo, 0
%shr = lshr i64 %val, 32
%hi = trunc i64 %shr to i32
%cttz_hi = call i32 @llvm.cttz.i32(i32 %hi, i1 true)
%hi_plus32 = or i32 %cttz_hi, 32
%cttz_lo = call i32 @llvm.cttz.i32(i32 %lo, i1 true)
%result = select i1 %cmp, i32 %hi_plus32, i32 %cttz_lo
ret i32 %result
}
define i32 @tgt(i64 %val) {
%cttz64 = call i64 @llvm.cttz.i64(i64 %val, i1 false)
%result = trunc i64 %cttz64 to i32
ret i32 %result
}
```
and similarly for ctlz intrinsic.
Alive proof for the 2 folds added by this patch.
cttz:
https://alive2.llvm.org/ce/z/-s14-s
ctlz:
https://alive2.llvm.org/ce/z/WfQepH
Commit: 295a7a9f75b839394b49d4ec59b2df33b30cd4fd
https://github.com/llvm/llvm-project/commit/295a7a9f75b839394b49d4ec59b2df33b30cd4fd
Author: Julian Brown <julian.brown at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M openmp/runtime/src/kmp_taskdeps.cpp
M openmp/runtime/src/kmp_tasking.cpp
Log Message:
-----------
[OpenMP] Make loop index unsigned in __kmpc_omp_task_with_deps/__kmp_omp_task
NFC.
Co-authored-by: Adrian Munera <adrian.munera at bsc.es>
Reviewers: ro-i
Pull Request: https://github.com/llvm/llvm-project/pull/194044
Commit: 5e42f09a6f001ad60ff85bbc0f54290d86033912
https://github.com/llvm/llvm-project/commit/5e42f09a6f001ad60ff85bbc0f54290d86033912
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/c.c
Log Message:
-----------
[clang][bytecode] Reject non-number values in Rem op (#194309)
Commit: aa04bcfd2f368405490a6ef45a8b7d6fd6ee964c
https://github.com/llvm/llvm-project/commit/aa04bcfd2f368405490a6ef45a8b7d6fd6ee964c
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/test/Dialect/MemRef/elide-reinterpret-cast.mlir
Log Message:
-----------
[memref] Simplify loads from reinterpret_cast of 1D contiguous memrefs (#188459)
Rewrite `memref.load` operations whose source is a `reinterpret_cast` that
represents a rank reshape of a 1D contiguous `memref` with a single non-unit
dimension.
Assisted-by: ChatGPT (refine implementation + tests). I reviewed all code and
tests before submission.
## Example
Before:
```mlir
%reinterpret_cast = memref.reinterpret_cast %src
to offset: [0], sizes: [1, 1, 999], strides: [999, 999, 1]
: memref<999xi64> to memref<1x1x999xi64>
%0 = memref.load %reinterpret_cast[%c0, %c0, %i]
: memref<1x1x999xi64>
```
After:
```mlir
%0 = memref.load %src[%i] : memref<999xi64>
```
## Motivation
This simplifies the IR, makes indexing explicit, and reduces indirection,
which in turn improves downstream transformations and lowerings (e.g. EmitC).
## Scope
This rewrite is intentionally narrow:
- Applies only to rank-expansion and rank-collapsing of a contiguous 1D buffer
(at most one non-unit dimension).
- Requires `reinterpret_cast` with zero offset and fully static sizes and
strides.
- Requires the non-unit dimension to be at a boundary (first or last).
- Requires any dropped indices (from size-1 dimensions) to be statically zero.
It does **not** handle:
- general `memref.reinterpret_cast` with arbitrary strides or offsets
- multiple non-unit dimensions
- cases where index dropping would change semantics
For example:
```mlir
%reinterpret_cast = memref.reinterpret_cast %src
to offset: [0], sizes: [1, 1, 1, 108], strides: [108, 108, 108, 1]
: memref<1x108xf32> to memref<1x1x1x108xf32>
%0 = memref.load %reinterpret_cast[%c0, %c1, %c0, %c0]
: memref<1x1x1x108xf32>
```
The pattern would skip `%c1` when forming the indices for the replacement load,
since it cuts the dimensions that were added to the left, including the
dimension where the non-zero index is:
```mlir
%0 = memref.load %src[%c0, %c0]
: memref<1x108xf32>
```
causing the rewrite to discard a non-zero index on a size-1 dimension, which is
not semantics-preserving.
## Correctness
In the accepted cases, the cast is a pure view that does not alter memory
layout. Size-1 dimensions do not contribute to address computation, and the
single non-unit dimension determines the access.
Dropping indices for size-1 dimensions (or inserting zeros when collapsing
rank) preserves the computed address. The rewrite is only applied when such
indices are statically zero, ensuring in-bounds semantics.
Therefore, the rewritten load is equivalent to the original load through the
`reinterpret_cast`
Commit: 8a8d26fe77dc76864aa86171a4bcf0c645b16013
https://github.com/llvm/llvm-project/commit/8a8d26fe77dc76864aa86171a4bcf0c645b16013
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
Log Message:
-----------
[RISCV] Support reinterpret cast intrinisc for OFP8 (#191626)
spec: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/433
stacked on: https://github.com/llvm/llvm-project/pull/191349
Commit: 5e318e6ca95e9826b1b277574385b2c7c75a0caf
https://github.com/llvm/llvm-project/commit/5e318e6ca95e9826b1b277574385b2c7c75a0caf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineKSHIFT - pull out common operands. NFC. (#194326)
Minor refactor before adding additional folds.
Commit: 31ea083c6b70a79706ba88dfea393d3834f65370
https://github.com/llvm/llvm-project/commit/31ea083c6b70a79706ba88dfea393d3834f65370
Author: Chandana Mudda <quic_csinderi at quicinc.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/WindowScheduler.cpp
A llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
Log Message:
-----------
Handle IMPLICIT_DEF in TripleMBB for WindowScheduler (#179190)
Previously, IMPLICIT_DEF instructions were not copied into the
triple-MBB region used by the WindowScheduler. This left the
machine-level liveness inconsistent with the triplicated code and could
trigger a LiveIntervals assertion:
LiveIntervals::HMEditor::updateRange: Assertion `LR.verify()' failed.
Copy IMPLICIT_DEF into the triple region so that the triplicated block
has a consistent set of defs and LiveIntervals can update ranges
correctly.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 94e0fd0988bb091960116a7aecc72f5e74161069
https://github.com/llvm/llvm-project/commit/94e0fd0988bb091960116a7aecc72f5e74161069
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Sema/SemaCoroutine.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures-co_await-assertion-failure.cpp
M clang/test/Analysis/more-dtors-cfg-output.cpp
M clang/test/CodeGenCXX/ubsan-coroutines.cpp
M clang/test/CodeGenCoroutines/coro-params.cpp
M clang/test/CodeGenCoroutines/coro-promise-dtor.cpp
M clang/test/Lexer/cxx-features.cpp
M clang/test/Modules/coro-await-elidable.cppm
M clang/test/PCH/coroutines.cpp
M clang/test/Parser/cxx20-coroutines.cpp
M clang/test/SemaCXX/addr-label-in-coroutines.cpp
M clang/test/SemaCXX/co_await-ast.cpp
M clang/test/SemaCXX/coroutine-alloc-2.cpp
M clang/test/SemaCXX/coroutine-alloc-3.cpp
M clang/test/SemaCXX/coroutine-alloc-4.cpp
M clang/test/SemaCXX/coroutine-allocs.cpp
M clang/test/SemaCXX/coroutine-builtins.cpp
M clang/test/SemaCXX/coroutine-dealloc.cpp
M clang/test/SemaCXX/coroutine-final-suspend-noexcept.cpp
M clang/test/SemaCXX/coroutine-no-valid-dealloc.cpp
M clang/test/SemaCXX/coroutine-noreturn.cpp
M clang/test/SemaCXX/coroutine-promise-ctor.cpp
M clang/test/SemaCXX/coroutine-rvo.cpp
M clang/test/SemaCXX/coroutine-traits-undefined-template.cpp
M clang/test/SemaCXX/coroutine-unevaluate.cpp
M clang/test/SemaCXX/coroutine-vla.cpp
A clang/test/SemaCXX/coroutine-win32x86.cpp
M clang/test/SemaCXX/coroutine_handle-address-return-type.cpp
M clang/test/SemaCXX/coroutines.cpp
M clang/test/SemaCXX/cxx20-delayed-typo-correction-crashes.cpp
M clang/test/SemaCXX/cxx2b-deducing-this-coro.cpp
M clang/test/SemaCXX/thread-safety-coro.cpp
M clang/test/SemaCXX/warn-throw-out-noexcept-coro.cpp
M clang/test/SemaCXX/warn-unused-parameters-coroutine.cpp
M clang/www/cxx_status.html
Log Message:
-----------
[Clang] No longer advertise support for coroutines on x86 windows. (#193456)
There are a large number of long standing issues with coroutines on
x86_32 windows as discussed here
https://github.com/llvm/llvm-project/issues/59382
- #59382
- #58556
- #58543
- #56989
- #193161
- #136481
As such this patches
- No longer defines `__cpp_impl_coroutine` on that platform
- Warn when using coroutines on that platform
The reason to not plainly error is that it would break too much valid
valid code, ie there are people who probably use coroutines sucessfully.
And we also want to keep testing on that platform, up until the point we
were to pull support completely.
Hopefully this is all temporary and someone will feel compelled to
improve the situation enough that we can unceremoniously revert this
patch.
Commit: 48ee9c82f27e170e9cada55ca40e757a391829ef
https://github.com/llvm/llvm-project/commit/48ee9c82f27e170e9cada55ca40e757a391829ef
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M flang/test/Lower/pointer-initial-target-2.f90
M flang/test/Lower/pointer-initial-target.f90
M flang/test/Lower/pointer-references.f90
M flang/test/Lower/pointer-results-as-arguments.f90
M flang/test/Lower/pointer-runtime.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 49) (#194276)
Tests converted from test/Lower: pointer-initial-target-2.f90,
pointer-initial-target.f90, pointer-references.f90,
pointer-results-as-arguments.f90, pointer-runtime.f90
Commit: 6d89cd85942cc5f702267855ab2788e43c072961
https://github.com/llvm/llvm-project/commit/6d89cd85942cc5f702267855ab2788e43c072961
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
A llvm/test/CodeGen/AArch64/sve-masked-ldst-alias-analysis.ll
Log Message:
-----------
[LLVM][SelectionDAG] Don't assume masked loads access all lanes in memory. (#192706)
When creating the initial DAG for masked loads we are using the result
type to define LocationSize. However, being a masked load we do not know
which, if any, memory locations will be read.
Fixes https://github.com/llvm/llvm-project/issues/180251
Commit: 8d060c0222a5cfa3b0fd875d48cf09b6c2dd4a5d
https://github.com/llvm/llvm-project/commit/8d060c0222a5cfa3b0fd875d48cf09b6c2dd4a5d
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/lib/Dialect/SPIRV/IR/SPIRVTosaOps.cpp
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
Log Message:
-----------
[mlir][spirv] Tighten SPIR-V TOSA pool constraints (#193515)
Tighten AvgPool2D and MaxPool2D verification by constraining kernel,
stride, and pad attributes and by checking the input/output NHWC
relationship.
Add verification tests for batch/channel mismatches, non-divisible
pooled shapes, pad-vs-kernel failures, and incorrect output shapes.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: c12ce4215408ddf83c338a4797b05dd0084b8d06
https://github.com/llvm/llvm-project/commit/c12ce4215408ddf83c338a4797b05dd0084b8d06
Author: Łukasz Plewa <lukasz.plewa at intel.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M offload/liboffload/API/Device.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/plugins-nextgen/level_zero/dynamic_l0/L0DynWrapper.cpp
M offload/plugins-nextgen/level_zero/dynamic_l0/level_zero/ze_api.h
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/tools/deviceinfo/llvm-offload-device-info.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
Log Message:
-----------
[offload] Add floating-point support detection queries (#193233)
Add device info queries to detect support for half-, single-, and
double-precision floating-point formats.
For the AMDGPU, CUDA, and Host plugins, add the new queries alongside
the existing capability reporting without changing current behavior.
For the Level Zero plugin, implement floating-point support detection
and capability querying.
Commit: bd7cd403dbb3c6698c9edddc288e58c16aa88a36
https://github.com/llvm/llvm-project/commit/bd7cd403dbb3c6698c9edddc288e58c16aa88a36
Author: Amina Chabane <amina.chabane at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M bolt/lib/Passes/CMOVConversion.cpp
M bolt/test/AArch64/unsupported-passes.test
Log Message:
-----------
[BOLT][AArch64] Refuse to run CMOVConversion pass (#193998)
`--cmov-conversion` is unsupported in AArch64 as
convertMoveToConditionalMove() is only overriden for X86.
- Add a guard for non-X86
- Update unsupported-passes.test with expected error
Commit: 27ebc844f542c93991675a22dcd813020963819f
https://github.com/llvm/llvm-project/commit/27ebc844f542c93991675a22dcd813020963819f
Author: Alexandre Ganea <aganea at havenstudios.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M clang/test/DebugInfo/Generic/codeview-buildinfo.c
Log Message:
-----------
[clang][CodeView] Prevent the input name from appearing in LF_BUILDINFO (#194140)
The implicit contract of an `LF_BUILDINFO` record (represented in LLVM
by
[`BuildInfoRecord`](https://github.com/llvm/llvm-project/blob/6f0b55ec55f3e5e1ccc0d6b0d04a307479218768/llvm/include/llvm/DebugInfo/CodeView/TypeRecord.h#L667))
is that its `CommandLine` field should not contain the input source file
— a separate `SourceFile` field is reserved for that.
When the command-line flattening was moved from `llvm/` to `clang/` in
#106369, the comparison value used to identify and strip the source
positional was switched from `MainSourceFile->getFilename()` (the full
input path resolved by clang) to `CodeGenOpts.MainFileName` (just the
basename, set via `-main-file-name`). As a result, when the driver is
invoked with an absolute source path the cc1 positional is that absolute
path and no longer matches `MainFileName`, so the source filename leaks
into `CommandLine` as a trailing positional cc1 argument.
This is a regression in Clang 20. It breaks downstream tooling such as
Live++, whose unity-splitting feature relies on the embedded command
line being the cc1 invocation minus the source. Reported in #193900.
This PR restores the previous behavior by passing the resolved frontend
input path(s) to `flattenClangCommandLine` and including them in the
equality check that strips the source positional. The basename match
against `MainFileName` is kept for the relative-input case. A regression
test (and a symmetric relative-path test) is added to
`clang/test/DebugInfo/Generic/codeview-buildinfo.c`.
Should fix #193900.
Commit: f60c5d989cf13e80acc576f638c2e7dd400a0aff
https://github.com/llvm/llvm-project/commit/f60c5d989cf13e80acc576f638c2e7dd400a0aff
Author: Łukasz Plewa <lukasz.plewa at intel.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
Log Message:
-----------
[offload] fix compilation issue caused by #193233 (#194350)
Commit: a51597f35f91ed5c25a391d5e965bfb6fe9a5ae2
https://github.com/llvm/llvm-project/commit/a51597f35f91ed5c25a391d5e965bfb6fe9a5ae2
Author: Nathan Gauër <brioche at google.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGBuilder.h
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
A clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
A clang/test/CodeGenHLSL/resources/cbuffer_struct_passing.hlsl
A clang/test/CodeGenHLSL/resources/cbuffer_struct_passing.logical.hlsl
Log Message:
-----------
[HLSL] Handle logical pointer for array assign (#193227)
This commits adds SPIR-V testing on an existing test (almost-NFC on DXIL
testing). It also copies it and invokes Clang using the experimental
logical pointer flag.
Adding this flag shows a missing case in the frontend, handled with this
commit.
Due to the difference in index handling between the structured.gep and
legacy one, the Cbuffer load codegen had to be rewritten. It's a bit
more naive, as we get one gep per level, but this will be handled by
optimizations later on.
Commit: aafba1dbdbee3ddeffca595c1d7550eb766c5178
https://github.com/llvm/llvm-project/commit/aafba1dbdbee3ddeffca595c1d7550eb766c5178
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-target-generic-spmd.mlir
Log Message:
-----------
[MLIR][OpenMP] Remove Generic-SPMD early detection (#150922)
This patch removes logic from MLIR to attempt identifying Generic
kernels that could be executed in SPMD mode.
This optimization is done by the OpenMPOpt pass for Clang and is only
required here to circumvent missing support for the new DeviceRTL APIs
used in MLIR to LLVM IR translation that Clang doesn't currently use
(e.g. `kmpc_distribute_static_loop` ). Removing checks in MLIR avoids
duplicating the logic that should be centralized in the OpenMPOpt pass.
Additionally, offloading kernels currently compiled through the OpenMP
dialect fail to run parallel regions properly when in Generic mode. By
disabling early detection, this issue becomes apparent for a range of
kernels where this was masked by having them run in SPMD mode.
Commit: 7b62dd1aeec5bcc7c4b8a8344966750b7d95250e
https://github.com/llvm/llvm-project/commit/7b62dd1aeec5bcc7c4b8a8344966750b7d95250e
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OpenMP][OMPIRBuilder] Add device shared memory allocation support (#150923)
This patch adds the `__kmpc_alloc_shared` and `__kmpc_free_shared`
DeviceRTL functions to the list of those the OMPIRBuilder is able to
create.
Commit: 3c39478e8b0b6d0e91a70c5887ea27ac90c2ed8c
https://github.com/llvm/llvm-project/commit/3c39478e8b0b6d0e91a70c5887ea27ac90c2ed8c
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/omptarget-device-shared-memory.mlir
Log Message:
-----------
[MLIR][OpenMP] Support allocations of device shared memory (#150924)
This patch updates the allocation of some reduction and private
variables within target regions to use device shared memory rather than
private memory. This is a prerequisite to produce working Generic
kernels containing parallel regions.
In particular, the following situations result in the usage of device
shared memory (only when compiling for the target device if they are
placed inside of a target region representing a Generic kernel):
- Reduction variables on `teams` constructs.
- Private variables on `teams` and `distribute` constructs that are
reduced or used inside of a `parallel` region.
Currently, there is no support for delayed privatization on `teams`
constructs, so private variables on these constructs won't currently be
affected. When support is added, if it uses the existing
`allocatePrivateVars` and `cleanupPrivateVars` functions, usage of
device shared memory will be introduced automatically.
Commit: 82f254992bbb822639cbe14d55df3bf5de65fa6a
https://github.com/llvm/llvm-project/commit/82f254992bbb822639cbe14d55df3bf5de65fa6a
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/Transforms/Utils/CodeExtractor.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Transforms/IPO/HotColdSplitting.cpp
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
Log Message:
-----------
[OpenMP][OMPIRBuilder] Use device shared memory for arg structures (#150925)
Argument structures are created when sections of the LLVM IR
corresponding to an OpenMP construct are outlined into their own
function. For this, stack allocations are used.
This patch modifies this behavior when compiling for a target device and
outlining `parallel`-related IR, so that it uses device shared memory
instead of private stack space. This is needed in order for threads to
have access to these arguments.
Commit: d463a276fcd68b3f0a070e69600fbfcb3aa2fa6e
https://github.com/llvm/llvm-project/commit/d463a276fcd68b3f0a070e69600fbfcb3aa2fa6e
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
Log Message:
-----------
[OpenMP][OMPIRBuilder] Support parallel in Generic kernels (#150926)
This patch introduces codegen logic to produce a wrapper function
argument for the `__kmpc_parallel_51` DeviceRTL function needed to
handle arguments passed using device shared memory in Generic mode.
Commit: 333f636c9af90fd77bc6669a74f8bd9e2832640b
https://github.com/llvm/llvm-project/commit/333f636c9af90fd77bc6669a74f8bd9e2832640b
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
A offload/test/offloading/fortran/target-generic-loops.f90
A offload/test/offloading/fortran/target-spmd-loops.f90
Log Message:
-----------
[OpenMPOpt] Make parallel regions reachable from new DeviceRTL loop functions (#150927)
This patch updates the OpenMP optimization pass to know about the new
DeviceRTL functions for loop constructs.
This change marks these functions as potentially containing parallel
regions, which fixes a current bug with the state machine rewrite
optimization. It previously failed to identify parallel regions located
inside of the callbacks passed to these new DeviceRTL functions, causing
the resulting code to skip executing these parallel regions.
As a result, Generic kernels produced by Flang that contain parallel
regions now work properly.
One known related issue not fixed by this patch is that the presence of
calls to these functions will prevent the SPMD-ization of Generic
kernels by OpenMPOpt. Previously, this was due to assuming there was no
parallel region. This is changed by this patch, but instead we now mark
it temporarily as unsupported in an SPMD context. The reason is that,
without additional changes, code intended for the main thread of the
team located outside of the parallel region would not be guarded
properly, resulting in race conditions and generally invalid behavior.
Commit: b5c755144d665750e5c60849c6612848bf2905d6
https://github.com/llvm/llvm-project/commit/b5c755144d665750e5c60849c6612848bf2905d6
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/Transforms/Utils/CodeExtractor.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Transforms/IPO/HotColdSplitting.cpp
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
M mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir
M mlir/test/Target/LLVMIR/omptarget-region-device-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-target-private-allocatable.mlir
Log Message:
-----------
[OMPIRBuilder] Add support for explicit deallocation points (#154752)
In this patch, some OMPIRBuilder codegen functions and callbacks are
updated to work with arrays of deallocation insertion points. The
purpose of this is to enable the replacement of `alloca`s with other
types of allocations that require explicit deallocations in a way that
makes it possible for `CodeExtractor` instances created during
OMPIRBuilder finalization to also use them.
The OpenMP to LLVM IR MLIR translation pass is updated to properly store
and forward deallocation points together with their matching allocation
point to the OMPIRBuilder.
Currently, only the `DeviceSharedMemCodeExtractor` uses this feature to
get the `CodeExtractor` to use device shared memory for intermediate
allocations when outlining a parallel region inside of a Generic kernel
(code path that is only used by Flang via MLIR, currently). However,
long term this might also be useful to refactor finalization of
variables with destructors, potentially reducing the use of callbacks
and simplifying privatization and reductions.
Instead of a single deallocation point, lists of those are used. This is
to cover cases where there are multiple exit blocks originating from a
single entry. If an allocation needing explicit deallocation is placed
in the entry block of such cases, it would need to be deallocated before
each of the exits.
Commit: f6012dd7884822a0428384f1e0a90e61e7380b1f
https://github.com/llvm/llvm-project/commit/f6012dd7884822a0428384f1e0a90e61e7380b1f
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[MLIR][OpenMP] Refactor omp.target_allocmem to allow reuse, NFC (#161861)
This patch moves tablegen definitions that could be used for all kinds
of heap allocations out of `omp.target_allocmem` and into a new
`OpenMP_HeapAllocClause` that can be reused.
Descriptions are updated to follow the format of most other operations
and the custom verifier for `omp.target_allocmem` is removed as it only
made a redundant check on its result type.
Commit: 568e1ad61abe03da5a8b2d573067895bbdb380e9
https://github.com/llvm/llvm-project/commit/568e1ad61abe03da5a8b2d573067895bbdb380e9
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
A mlir/test/Target/LLVMIR/omptarget-device-shared-mem.mlir
Log Message:
-----------
[Flang][MLIR][OpenMP] Add explicit shared memory (de-)allocation ops (#161862)
This patch introduces the `omp.alloc_shared_mem` and
`omp.free_shared_mem` operations to represent explicit allocations and
deallocations of shared memory across threads in a team, mirroring the
existing `omp.target_allocmem` and `omp.target_freemem`.
The `omp.alloc_shared_mem` op goes through the same Flang-specific
transformations as `omp.target_allocmem`, so that the size of the buffer
can be properly calculated when translating to LLVM IR.
The corresponding runtime functions produced for these new operations
are `__kmpc_alloc_shared` and `__kmpc_free_shared`, which previously
could only be created for implicit allocations (e.g. privatized and
reduction variables).
Commit: d6061d297d3c4f462a84bd77f182d191d982ac5d
https://github.com/llvm/llvm-project/commit/d6061d297d3c4f462a84bd77f182d191d982ac5d
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/test/Fir/basic-program.fir
M mlir/docs/Passes.md
M mlir/include/mlir/Dialect/OpenMP/Transforms/Passes.h
M mlir/include/mlir/Dialect/OpenMP/Transforms/Passes.td
M mlir/lib/Dialect/OpenMP/CMakeLists.txt
A mlir/lib/Dialect/OpenMP/IR/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
A mlir/lib/Dialect/OpenMP/Transforms/StackToShared.cpp
A mlir/test/Dialect/OpenMP/stack-to-shared.mlir
Log Message:
-----------
[Flang][OpenMP] Add pass to replace allocas with device shared memory (#161863)
This patch introduces a new Flang OpenMP MLIR pass, only ran for target
device modules, that identifies `fir.alloca` operations that should use
device shared memory and replaces them with pairs of
`omp.alloc_shared_mem` and `omp.free_shared_mem` operations.
This works in conjunction to the MLIR to LLVM IR translation pass'
handling of privatization, mapping and reductions in the OpenMP dialect
to properly select the right memory space for allocations based on where
they are made and where they are used.
This pass, in particular, handles explicit stack allocations in MLIR,
whereas the aforementioned translation pass takes care of implicit ones
represented by entry block arguments.
Commit: fad06a418b4f89510a390c215218f1ab8de0ecad
https://github.com/llvm/llvm-project/commit/fad06a418b4f89510a390c215218f1ab8de0ecad
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M flang/test/Integration/OpenMP/target-use-device-nested.f90
M flang/test/Integration/OpenMP/threadprivate-target-device.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-constant-alloca-raise.mlir
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
A mlir/test/Target/LLVMIR/openmp-target-private-shared-mem.mlir
A offload/test/offloading/fortran/target-generic-outlined-loops.f90
Log Message:
-----------
[MLIR][OpenMP][OMPIRBuilder] Improve shared memory checks (#161864)
This patch refines checks to decide whether to use device shared memory
or regular stack allocations. In particular, it adds support for
parallel regions residing on standalone target device functions.
The changes are:
- Shared memory is introduced for `omp.target` implicit allocations,
such as those related to privatization and mapping, as long as they are
shared across threads in a nested parallel region.
- Standalone target device functions are interpreted as being part of a
Generic kernel, since the fact that they are present in the module after
filtering means they must be reachable from a target region.
- Prevent allocations whose only shared uses inside of an `omp.parallel`
region are as part of a `private` clause from being moved to device
shared memory.
Commit: c94db1af36c2f66d71cd0c492068937eee641e56
https://github.com/llvm/llvm-project/commit/c94db1af36c2f66d71cd0c492068937eee641e56
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
A mlir/include/mlir/Dialect/OpenMP/Utils/Utils.h
M mlir/lib/Dialect/OpenMP/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/Transforms/StackToShared.cpp
A mlir/lib/Dialect/OpenMP/Utils/CMakeLists.txt
A mlir/lib/Dialect/OpenMP/Utils/Utils.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[MLIR][OpenMP] Unify device shared memory logic, NFCI (#182856)
This patch creates a utils library for the OpenMP dialect with functions
used by MLIR to LLVM IR translation as well as the stack-to-shared pass
to determine which allocations must use local stack memory or device
shared memory.
Commit: cf30e4b5c2d55e217ade2483c4672f2488da48df
https://github.com/llvm/llvm-project/commit/cf30e4b5c2d55e217ade2483c4672f2488da48df
Author: Jack Styles <jack.styles at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.h
A llvm/test/CodeGen/AArch64/aarch64-no-mov-spill-chain.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
Log Message:
-----------
[AArch64] Enable Spillage Copy Elimination by default (#186093)
In times of high register pressure, the greedy register allocator can
emit large eviction chains that consist of many `mov` instructions. The
Spillage Copy Elimination pass handles this, by finding these chains and
decreasing their impact. Take a mov chain such as the following where
`x8` is used for an 8-byte Folded Reload:
```
mov x7, x6
mov x6, x5
mov x5, x4
mov x4, x3
mov x3, x2
mov x2, x1
mov x1, x30
mov x30, x8
< use x8 >
mov x8, x30
mov x30, x1
mov x1, x2
mov x2, x3
mov x3, x4
mov x4, x5
mov x5, x6
mov x6, x7
```
Becomes:
```
mov x7, x6
mov x6, x8
< use x8 >
mov x8, x6
mov x6, x7
```
This provides performance benefits for long mov chains, where we are no
longer needing to copy these values between registers.
This does introduce compile time regressions, as was originally noted in
the initial review. From my testing, this was around 0.17% on average
using LLVM Test Suite.
Further information:
Original Review: https://reviews.llvm.org/D122118
Compile Time Regression information from original review:
http://llvm-compile-time-tracker.com/compare.php?from=781eabeb40b8e47e3a46b0b927784e63f0aad9ab&to=0af2744a89bf0ed05e83ac1ed9d21d6d74cdfeca&stat=instructions%3Au
Assisted-by: codex (Generation of new test)
Commit: 889708eed861b4218fda5a085b47f37b6b73b739
https://github.com/llvm/llvm-project/commit/889708eed861b4218fda5a085b47f37b6b73b739
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
A clang/lib/CIR/CodeGen/CIRGenOpenMPRuntime.cpp
A clang/lib/CIR/CodeGen/CIRGenOpenMPRuntime.h
M clang/lib/CIR/CodeGen/CMakeLists.txt
A clang/test/CIR/CodeGenOpenMP/emit-device-functions.cpp
Log Message:
-----------
[CIR][OpenMP] Enable emission of target functions (#193204)
This PR allows generation of target device functions for OpenMP. It also
handles filtering out host functions that do not contain target regions.
Assisted-by: Cursor / claude-4.6-opus-high
Commit: 8116e869531490f28ecaa3bcaac1fe644b545e0e
https://github.com/llvm/llvm-project/commit/8116e869531490f28ecaa3bcaac1fe644b545e0e
Author: CHANDRA GHALE <chandra.nitdgp at gmail.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M flang/lib/Lower/OpenMP/Utils.cpp
A flang/test/Lower/OpenMP/tile-parallel-do.f90
Log Message:
-----------
[Flang][OpenMP] Fix crash lowering parallel do with nested tile construct (#193955)
This fixes a crash in OpenMP lowering for cases like `!$omp parallel do
with nested !$omp tile sizes(...)` .
The loop-walk logic now correctly steps through intermediate OpenMP
transformation wrappers to find the actual do construct, instead of
assuming it is directly nested.
Fixes :
[https://github.com/llvm/llvm-project/issues/193256](https://github.com/llvm/llvm-project/issues/193256)
sample reproducer :
[https://godbolt.org/z/b7zecYEMT](https://godbolt.org/z/b7zecYEMT)
Co-authored-by: Chandra Ghale <ghale at pe34genoa.hpc.amslabs.hpecorp.net>
Commit: ef867c03d77cc5c11845ab3ac2392c124271a9cf
https://github.com/llvm/llvm-project/commit/ef867c03d77cc5c11845ab3ac2392c124271a9cf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/CodeGen/X86/vselect-avx.ll
Log Message:
-----------
[X86] vselect-avx.ll - regenerate asm comments (#194353)
Commit: 902814afe11799e2b90a9879658e1356b3ff6aff
https://github.com/llvm/llvm-project/commit/902814afe11799e2b90a9879658e1356b3ff6aff
Author: Raphael Isemann <rise at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M lldb/test/API/lang/objc/modules-auto-import/TestModulesAutoImport.py
M lldb/test/API/lang/objc/modules-auto-import/main.m
Log Message:
-----------
[lldb][test] Modernize TestModulesAutoImport (#194357)
This replaces all the custom test setup logic with the newer test
utilities. Not technically NFC as the newer checks are more strict.
Commit: 6ac432bdc8122a945e69b39d7a0368b3947b769d
https://github.com/llvm/llvm-project/commit/6ac432bdc8122a945e69b39d7a0368b3947b769d
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M .gitignore
Log Message:
-----------
[llvm][.gitignore] Ignore .agents directory (#194236)
The `.agents` directory is a common convention for storing coding agent
related stuff like rules and skills, recognized by major coding agents
like Claude Code, Codex, GitHub Copilot, OpenCode, etc. Ignore this
directory to avoid accidentally commiting these coding agent related
content to the repo.
Commit: ba3d7a59016b0ecae7eb5249bbcf289e3e189c55
https://github.com/llvm/llvm-project/commit/ba3d7a59016b0ecae7eb5249bbcf289e3e189c55
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll
R llvm/test/CodeGen/X86/gc-empty-basic-blocks.mir
Log Message:
-----------
[NewPM] Wire up gc-empty-basic-blocks into pipeline (#194179)
Same setup as the old pipeline and resolves a testing TODO now that we
have a full pipeline for x86.
Commit: d48c8411dfe6a611a7b8b2b3e53b2da85270a82e
https://github.com/llvm/llvm-project/commit/d48c8411dfe6a611a7b8b2b3e53b2da85270a82e
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes c94db1a (#194359)
This fixes c94db1af36c2f66d71cd0c492068937eee641e56.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: e028d938d542d00f0fe90f50d561868cc7c68fde
https://github.com/llvm/llvm-project/commit/e028d938d542d00f0fe90f50d561868cc7c68fde
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
A llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll
Log Message:
-----------
AMDGPU: Fix instruction size for madmk/madak (#194361)
This caused the revert of #191461
Commit: 9b2411da20d78653fdc93972e26700aef2f7dfe9
https://github.com/llvm/llvm-project/commit/9b2411da20d78653fdc93972e26700aef2f7dfe9
Author: Andrey Grabezhnoy <andrey.grabezhnoy at intel.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/and-xor-or.ll
M llvm/test/Transforms/InstCombine/binop-and-shifts.ll
Log Message:
-----------
[InstCombine] Require one-use intermediate binop in foldBinOpShiftWithShift (#194341)
foldBinOpShiftWithShift rewrites
binop(shift(X,C) op Mask, shift(Y,C))
to
binop(shift(X+Y,C), Mask).
Both shifts are matched with m_OneUse, but the enclosing binop that
wraps (shift(X,C), Mask) is not. When that binop has additional users
the rewrite cannot eliminate the originals and only adds new
instructions. The reproducer in the issue shows this: a shared base
with several downstream consumers gets duplicated on each one, so the
fold grows the IR instead of shrinking it.
Wrap the outer m_c_BinOp in m_OneUse so the fold only fires when the
binop can actually be replaced. Mirrors the one-use discipline already
applied to both shifts in the same matcher.
Fixes #194007.
Commit: 5f0f269d5f835a07d74a2428e7e372c60b4c048f
https://github.com/llvm/llvm-project/commit/5f0f269d5f835a07d74a2428e7e372c60b4c048f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
Log Message:
-----------
[MemRef] Fix -Wunused-function (#194366)
areIndicesInBounds is only used within an assert statement, so mark it
[[maybe_unused]] so that the compiler does not otherwise warn in
non-assertion builds.
Commit: 8242576869985db73d44ac537208744dceb93503
https://github.com/llvm/llvm-project/commit/8242576869985db73d44ac537208744dceb93503
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseCXXInlineMethods.cpp
M clang/test/SemaCXX/lambda-unevaluated.cpp
Log Message:
-----------
[Clang] prevent crash in delayed default-argument lambda captures (#176749)
Fixes #176534
---
This patch resolves a crash when parsing delayed default arguments that
contain lambda expressions.
```cpp
struct S {
void f(int x, int = sizeof([x] { return x; }()));
};
```
When late-parsing default arguments that contain lambdas, `Sema` builds
a `FunctionScopes` stack containing only the lambda scope
(`FunctionScopes.size()` equals 1), however, `tryCaptureVariable`
expects an enclosing function scope outside the lambda scope
https://github.com/llvm/llvm-project/blob/41e231cae38028473dd327e8de5f65792b521ffe/clang/lib/Sema/SemaExpr.cpp#L19473-L19474
https://github.com/llvm/llvm-project/blob/41e231cae38028473dd327e8de5f65792b521ffe/clang/lib/Sema/SemaExpr.cpp#L19518
Scope capture handling logic decrements `FunctionScopesIndex` to align
declaration contexts
https://github.com/llvm/llvm-project/blob/41e231cae38028473dd327e8de5f65792b521ffe/clang/lib/Sema/SemaExpr.cpp#L19696
and later relies on it when traversing and accessing outer scopes
https://github.com/llvm/llvm-project/blob/41e231cae38028473dd327e8de5f65792b521ffe/clang/lib/Sema/SemaExpr.cpp#L19522-L19524
preserving the function scope in the late-parsing path prevents invalid
traversal during lambda capture handling
Commit: 06ddfcf0ca9cdb1481fff3cff6f73d5c26d45ffe
https://github.com/llvm/llvm-project/commit/06ddfcf0ca9cdb1481fff3cff6f73d5c26d45ffe
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M libunwind/src/AddressSpace.hpp
M libunwind/src/DwarfParser.hpp
Log Message:
-----------
[libunwind] fix build errors on x32 and mips n32 (#194310)
Commit: cc2b2f548622805a883201bfd7732d863636ecac
https://github.com/llvm/llvm-project/commit/cc2b2f548622805a883201bfd7732d863636ecac
Author: Petter Berntsson <petter.berntsson at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
A libc/utils/docgen/sys/sem.yaml
Log Message:
-----------
[libc][docs] Add sys/sem.h POSIX header documentation (#122006) (#194358)
Add sys/sem.h implementation-status docs to llvm-libc.
Commit: 4f50fe9298c9587aabf3698a1c79ff83d54fc702
https://github.com/llvm/llvm-project/commit/4f50fe9298c9587aabf3698a1c79ff83d54fc702
Author: Joe Nash <joseph.nash at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOPDInstructions.td
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd_unused_operands.txt
Log Message:
-----------
[AMDGPU][MC] Permit unneeded VOPD mov operands to be non-zero (#194060)
Use ? instead of 0 in the tablegen definitions for VOPD containing
v_mov. This enables the instruction to be disassembled regardless of
what bits are in those fields, which helps diagnose broken code.
Previously, the disassembler would reject these.
Commit: 40a303d94644891829fd5b399a24c59b788a917e
https://github.com/llvm/llvm-project/commit/40a303d94644891829fd5b399a24c59b788a917e
Author: Fushj <fsjzzu at 126.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
A llvm/test/ExecutionEngine/Interpreter/test-interp-variable-arguments.ll
Log Message:
-----------
[llvm][lli] fix lli crash when run variable arguments function as a interpret (#173719)
Run `lli` comand with the flag `-force-interpreter=true` to execute LLVM
bitcode, if `lli` run `variable arguments` function in the bitcode, it
will crash.
Fix #173718
Commit: 0193af47d2b78a58d5019bb1db35be8877975b41
https://github.com/llvm/llvm-project/commit/0193af47d2b78a58d5019bb1db35be8877975b41
Author: Kevin Sala Penades <salapenades1 at llnl.gov>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
Log Message:
-----------
[offload] Fix use of AsyncInfoWrapper's finalize function (#194098)
The expected use is to forward the error from the asynchronous
operation's issuing (e.g., launchImpl) directly into the
AsyncInfoWrapper::finalize(). The check of the error is already
performed inside that function. No need to forward a dummy success error
code.
Commit: 74734782b42b640db1c6995e2d88388a5435fbfe
https://github.com/llvm/llvm-project/commit/74734782b42b640db1c6995e2d88388a5435fbfe
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
Log Message:
-----------
[Clang][HLSL] Fix -Wunused-variable (#194374)
Inline the variable definition into the assert given it is side effect
free and the variable name does not make the code much more clear.
Commit: c6de992abfd3ad76345f013b0f4dd5dfef3f0bc5
https://github.com/llvm/llvm-project/commit/c6de992abfd3ad76345f013b0f4dd5dfef3f0bc5
Author: Amilendra Kodithuwakku <amilendra.kodithuwakku at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_addqp.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_addsubp.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_subp.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-addqp.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-addsubp.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-subp.ll
Log Message:
-----------
[Clang][AArch64][SVE2p3][SME2p3] Add intrinsics for v9.7a add/add-and-subtract/subtract pairwise operations (#187527)
Add the following new clang intrinsics based on the ACLE specification
https://github.com/ARM-software/acle/pull/428 (Add alpha support for 9.7
data processing intrinsics)
- ADDQP (Add pairwise within quadword vector segments)
- svint8_t svaddqp_s8(svint8_t, svint8_t) / svint8_t svaddqp(svint8_t,
svint8_t)
- svuint8_t svaddqp_u8(svuint8_t, svuint8_t) / svuint8_t
svaddqp(svuint8_t, svuint8_t)
- svint16_t svaddqp_s16(svint16_t, svint16_t) / svint16_t
svaddqp(svint16_t, svint16_t)
- svuint16_t svaddqp_u16(svuint16_t, svuint16_t) / svuint16_t
svaddqp(svuint16_t, svuint16_t)
- svint32_t svaddqp_s32(svint32_t, svint32_t) / svint32_t
svaddqp(svint32_t, svint32_t)
- svuint32_t svaddqp_u32(svuint32_t, svuint32_t) / svuint32_t
svaddqp(svuint32_t, svuint32_t)
- svint64_t svaddqp_s64(svint64_t, svint64_t) / svint64_t
svaddqp(svint64_t, svint64_t)
- svuint64_t svaddqp_u64(svuint64_t, svuint64_t) / svuint64_t
svaddqp(svuint64_t, svuint64_t)
- ADDSUBP (Add and subtract pairwise)
- svint8_t svaddsubp_s8(svint8_t, svint8_t) / svint8_t
svaddsubp(svint8_t, svint8_t)
- svuint8_t svaddsubp_u8(svuint8_t, svuint8_t) / svuint8_t
svaddsubp(svuint8_t, svuint8_t)
- svint16_t svaddsubp_s16(svint16_t, svint16_t) / svint16_t
svaddsubp(svint16_t, svint16_t)
- svuint16_t svaddsubp_u16(svuint16_t, svuint16_t) / svuint16_t
svaddsubp(svuint16_t, svuint16_t)
- svint32_t svaddsubp_s32(svint32_t, svint32_t) / svint32_t
svaddsubp(svint32_t, svint32_t)
- svuint32_t svaddsubp_u32(svuint32_t, svuint32_t) / svuint32_t
svaddsubp(svuint32_t, svuint32_t)
- svint64_t svaddsubp_s64(svint64_t, svint64_t) / svint64_t
svaddsubp(svint64_t, svint64_t)
- svuint64_t svaddsubp_u64(svuint64_t, svuint64_t) / svuint64_t
svaddsubp(svuint64_t, svuint64_t)
- SUBP (Subtract pairwise)
- svint8_t svsubp_s8(svbool_t, svint8_t, svint8_t) / svint8_t
svsubp(svbool_t, svint8_t, svint8_t)
- svuint8_t svsubp_u8(svbool_t, svuint8_t, svuint8_t) / svuint8_t
svsubp(svbool_t, svuint8_t, svuint8_t)
- svint16_t svsubp_s16(svbool_t, svint16_t, svint16_t) / svint16_t
svsubp(svbool_t, svint16_t, svint16_t)
- svuint16_t svsubp_u16(svbool_t, svuint16_t, svuint16_t) / svuint16_t
svsubp(svbool_t, svuint16_t, svuint16_t)
- svint32_t svsubp_s32(svbool_t, svint32_t, svint32_t) / svint32_t
svsubp(svbool_t, svint32_t, svint32_t)
- svuint32_t svsubp_u32(svbool_t, svuint32_t, svuint32_t) / svuint32_t
svsubp(svbool_t, svuint32_t, svuint32_t)
- svint64_t svsubp_s64(svbool_t, svint64_t, svint64_t) / svint64_t
svsubp(svbool_t, svint64_t, svint64_t)
- svuint64_t svsubp_u64(svbool_t, svuint64_t, svuint64_t) / svuint64_t
svsubp(svbool_t, svuint64_t, svuint64_t)
Commit: 4e6d3722fca73c97367720180a8d547057fda380
https://github.com/llvm/llvm-project/commit/4e6d3722fca73c97367720180a8d547057fda380
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
Log Message:
-----------
[LiveDebugValues] Use std::sort for register sorting in collectIDsForRegs (#194339)
VarLocBasedLDV::collectIDsForRegs sorts a SmallVector<Register> using
array_pod_sort which is a thin wrapper around qsort. That shows up as a hotspot
in compile-time profiles under __GI___qsort_r.
Switching this to an explicit-comparator llvm::sort call, which takes the
std::sort path instead improves compile-time with no change to code-size.
CTMark geomean:
- stage1-O0-g: -0.41%
- stage1-aarch64-O0-g: -0.58%
- stage2-O0-g: -0.40%
http://llvm-compile-time-tracker.com/compare.php?from=347aa3f6fbcc48cd752d02aa581b74c33d18dd41&to=cca8df56a576682510733c4c1b6fc12556e2dd7c&stat=instructions%3Au
Commit: 0a58d0ceb530a9caffd7126fe9c4bb98a79de1ac
https://github.com/llvm/llvm-project/commit/0a58d0ceb530a9caffd7126fe9c4bb98a79de1ac
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/test/AST/ByteCode/cxx17.cpp
M clang/test/SemaCXX/cxx17-compat.cpp
Log Message:
-----------
[SystemZ] z/OS only accept C initialization (#194023)
The TLS support only accept compile constant expressions (both C and
C++) on z/OS. Add #if to skip these tests on z/OS.
Commit: 97dc0fcbceea0871ab86ecf6d534be42b42bc7d3
https://github.com/llvm/llvm-project/commit/97dc0fcbceea0871ab86ecf6d534be42b42bc7d3
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
A llvm/test/Transforms/OpenMP/spirv_ctor.ll
Log Message:
-----------
[Attributor] Support SPIR-V address spaces (#192725)
Right now Attributor assumes that if the the target is a GPU is can use
a single set of address space numerical values to determine the local
address space, but that's not true in general, so add SPIR-V support,
which uses different values.
This fixes an instruction incorrectly being marked as dead and optimized
out for an OpenMP SPIR-V offloading example.
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 555140f8bfd296948198ac8bd2f07692c132ded6
https://github.com/llvm/llvm-project/commit/555140f8bfd296948198ac8bd2f07692c132ded6
Author: sujianIBM <98488060+sujianIBM at users.noreply.github.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/utils/lit/tests/shtest-ulimit-nondarwin.py
Log Message:
-----------
[z/OS] Mark shtest-ulimit-nondarwin.py unsupported on zos. (#194016)
This PR marks llvm/utils/lit/tests/shtest-ulimit-nondarwin.py
unsupported on z/OS.
Commit: dd383b46106587f85cd4f82a4f67d05ea9ae37bd
https://github.com/llvm/llvm-project/commit/dd383b46106587f85cd4f82a4f67d05ea9ae37bd
Author: sujianIBM <98488060+sujianIBM at users.noreply.github.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/utils/lit/lit/TestingConfig.py
Log Message:
-----------
[z/OS] Add passing env vars in lit on z/OS. (#194017)
This PR adds passing environment variables in lit/TestingConfig.py on
z/OS.
Commit: 314c655470b03a8112b2a0107c99a61076852cca
https://github.com/llvm/llvm-project/commit/314c655470b03a8112b2a0107c99a61076852cca
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
A lldb/test/API/functionalities/multi-breakpoint/Makefile
A lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
A lldb/test/API/functionalities/multi-breakpoint/main.c
M lldb/tools/debugserver/source/JSON.h
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/tools/debugserver/source/RNBRemote.h
Log Message:
-----------
[debugserver] Implement MultiBreakpoint (#192914)
This implements the packet as described in
https://github.com/llvm/llvm-project/pull/192910
The following PRs are related to the MultiBreakpoint feature:
* https://github.com/llvm/llvm-project/pull/192910
* https://github.com/llvm/llvm-project/pull/192914
* https://github.com/llvm/llvm-project/pull/192915
* https://github.com/llvm/llvm-project/pull/192919
* https://github.com/llvm/llvm-project/pull/192962
* https://github.com/llvm/llvm-project/pull/192964
* https://github.com/llvm/llvm-project/pull/192971
* https://github.com/llvm/llvm-project/pull/192988
Commit: 8e0011a2c686c371cf21fa05ff2ae955017e6e1d
https://github.com/llvm/llvm-project/commit/8e0011a2c686c371cf21fa05ff2ae955017e6e1d
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/Transforms/FunctionAttrs/nosync.ll
Log Message:
-----------
[FunctionAttrs] Remove declaration check lines (NFC) (#194384)
These are annoying, because they get dropped by UTC. We're not
inferring attributes on declarations anyway.
Commit: a94c11640bf228d68cb68be927ad2f8eccc16145
https://github.com/llvm/llvm-project/commit/a94c11640bf228d68cb68be927ad2f8eccc16145
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/Transforms/GlobalOpt/ctor-memset.ll
M llvm/test/Transforms/GlobalOpt/pr54572.ll
Log Message:
-----------
[GlobalOpt] Regenerate test checks (NFC) (#194385)
Commit: 5ee1495ab6529ba2ae8d4af98d5c42ab96d3441d
https://github.com/llvm/llvm-project/commit/5ee1495ab6529ba2ae8d4af98d5c42ab96d3441d
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/test/Parser/static_assert.cpp
Log Message:
-----------
[Clang] fix parser recovery for invalid static_assert string messages (#187859)
Fixes #187690
---
This PR fixes parser recovery for invalid `static_assert` declarations
with string literal messages. The parser now stops the message lookahead
on `;` and `eof`, so invalid inputs are diagnosed as parse errors.
Commit: 78eccec0db8a7739151c6de12de0e130c820e20d
https://github.com/llvm/llvm-project/commit/78eccec0db8a7739151c6de12de0e130c820e20d
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm-transcendentals.mlir
M mlir/test/Target/LLVMIR/nvvm/transcendentals.mlir
Log Message:
-----------
[MLIR][NVVM] Add `nvvm.log2` OP (#193789)
Implement `nvvm.log2` with ftz flag
Commit: bc7e916974e9f2b17d4575db07d5a1adce98d120
https://github.com/llvm/llvm-project/commit/bc7e916974e9f2b17d4575db07d5a1adce98d120
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
A llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
Log Message:
-----------
AMDGPU: Address fixme for v_mac_f16 rounding mode (#194360)
This should use the f16/f64 rounding mode
Commit: c2ab7f2130bbd5fa8bb4a13e34454b91d4aa1d8f
https://github.com/llvm/llvm-project/commit/c2ab7f2130bbd5fa8bb4a13e34454b91d4aa1d8f
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
Log Message:
-----------
[lldbremote][NFC] Factor out code handling breakpoint packets (#192915)
This commit extracts the code handling breakpoint packets into a helper
function that can be used by a future implementation of the
MultiBreakpointPacket.
It is meant to be purely NFC.
There are two functions handling breakpoint packets (`handle_Z` and
`handle_z`) with a lot of repeated code. This commit did not attempt to
merge the two, as that would make the diff much larger due to subtle
differences in the error message produced by the two. The only
deduplication done is in the code processing a GDBStoppointType, where a
helper struct (`BreakpointKind`) and function
(`std::optional<BreakpointKind> getBreakpointKind(GDBStoppointType
stoppoint_type)`) was created.
The following PRs are related to the MultiBreakpoint feature:
* https://github.com/llvm/llvm-project/pull/192910
* https://github.com/llvm/llvm-project/pull/192914
* https://github.com/llvm/llvm-project/pull/192915
* https://github.com/llvm/llvm-project/pull/192919
* https://github.com/llvm/llvm-project/pull/192962
* https://github.com/llvm/llvm-project/pull/192964
* https://github.com/llvm/llvm-project/pull/192971
* https://github.com/llvm/llvm-project/pull/192988
Commit: 57754e0965361493bb47ddd9a332519318dc40ff
https://github.com/llvm/llvm-project/commit/57754e0965361493bb47ddd9a332519318dc40ff
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/arm_sve.td
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
A clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
A clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
A clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve-b16mm.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p2_AND_f16mm.c
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/neon-matmul-f16.ll
A llvm/test/CodeGen/AArch64/neon-matmul-f16f32mm.ll
A llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-bf16.ll
A llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-f16.ll
Log Message:
-----------
[AArch64][clang][llvm] Add ACLE Armv9.7 matrix multiply-accumulate intrinsics (#193017)
Implement new ACLE matrix multiply-accumulate intrinsics for Armv9.7:
```c
// 16-bit floating-point matrix multiply-accumulate.
// Only if __ARM_FEATURE_SVE_B16MM
// Variant also available for _f16 if (__ARM_FEATURE_SVE2p2 && __ARM_FEATURE_F16MM).
svbfloat16_t svmmla[_bf16](svbfloat16_t zda, svbfloat16_t zn, svbfloat16_t zm);
// Half-precision matrix multiply accumulating to single-precision instruction.
// Requires the +f16f32mm architecture extension.
float32x4_t vmmlaq_f32_f16(float32x4_t r, float16x8_t a, float16x8_t b);
// Non-widening half-precision matrix multiply instruction.
// Requires the +f16mm architecture extension.
float16x8_t vmmlaq_f16_f16(float16x8_t r, float16x8_t a, float16x8_t b);
```
Commit: 85935241b74f332a2d8c616510b7ef74ebe6a1ac
https://github.com/llvm/llvm-project/commit/85935241b74f332a2d8c616510b7ef74ebe6a1ac
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Semantics/canonicalize-acc.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Lower/OpenACC/Todo/do-loops-to-acc-loops-todo.f90
M flang/test/Semantics/OpenACC/acc-canonicalization-validity.f90
M flang/test/Semantics/OpenACC/acc-loop.f90
Log Message:
-----------
[flang][semantics][openacc] Allow collapse clauses on do concurrent (#192488)
This PR generalizes the semantic checking for collapse clauses to work
on `do concurrent` and fixes two bugs exposed along the way:
- The first was that `collapse (n)` where n < the number of nested loops
was giving an assertion violation.
- The second was do concurrent index variables were causing an assertion
violation because they hadn't been declared before looking them up.
The lowering is implemented as a TODO which will happen in a following
diff.
Commit: 5e451509b6e26a06b86d665d852a15c7e0a4c8ea
https://github.com/llvm/llvm-project/commit/5e451509b6e26a06b86d665d852a15c7e0a4c8ea
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M offload/test/offloading/ctor_dtor.cpp
Log Message:
-----------
[offload][lit] Enable ctor_dtor.cpp on Intel GPUs (#194389)
It was fixed with https://github.com/llvm/llvm-project/pull/192725 and
https://github.com/llvm/llvm-project/pull/192730.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: c183492e609b57b4181de6c3f15c897f78d13ace
https://github.com/llvm/llvm-project/commit/c183492e609b57b4181de6c3f15c897f78d13ace
Author: sstwcw <su3e8a96kzlver at posteo.net>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestComments.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Recognize more braced initializers (#192299)
new
```C++
a = {x * x, x * x};
```
old
```C++
a = {x * x, x *x};
```
Fixes #57442.
The patch makes the program treat a brace following an equal sign a
braced initializer.
The patch changes these tests.
- In UnderstandsSingleLineComments and CommentsInStaticInitializers, the
comment in the formatted code used to be on a separate line, now it is
on the same line as the brace. The new behavior is consistent with
comment in braced lists that are correctly identified. Here is the
code for it from the test LayoutCxx11BraceInitializers and the
function mustBreakBefore.
```C++
// In braced lists, the first comment is always assumed to belong to the
// first element. Thus, it can be moved to the next or previous line as
// appropriate.
verifyFormat("function({// First element:\n"
" 1,\n"
" // Second element:\n"
" 2});",
"function({\n"
" // First element:\n"
" 1,\n"
" // Second element:\n"
" 2});");
if (Right.is(tok::comment)) {
return Left.isNoneOf(BK_BracedInit, TT_CtorInitializerColon) &&
Right.NewlinesBefore > 0 && Right.HasUnescapedNewline;
}
```
- In FormatsBracedListsInColumnLayout, the style is configured to one
which allows a trailing comment in the first line.
Commit: 6b81cdb4d99c23106df7232f45aad7b0eff4e43c
https://github.com/llvm/llvm-project/commit/6b81cdb4d99c23106df7232f45aad7b0eff4e43c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/identity-reuses-with-poisons.ll
Log Message:
-----------
[SLP]Fix crash in getReorderingData on all-poison reuse-mask slice
When the reuse-shuffle mask is iterated in Sz-sized parts and a part is
entirely PoisonMaskElem, `Val` stays at PoisonMaskElem (-1) and the
subsequent `UsedVals.test(Val)` trips the SmallBitVector OOB assertion.
Bail out of reordering in that case.
Fixes #194315
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/194392
Commit: b629f86f4f7b691fae18353a6ae3babe2ce9e9ec
https://github.com/llvm/llvm-project/commit/b629f86f4f7b691fae18353a6ae3babe2ce9e9ec
Author: LumioseSil <gfunni234 at gmail.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/test/CodeGen/ARM/vbits.ll
M llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
Log Message:
-----------
[ARM] hasAndNot in ARM supports vectors (#193614)
NEON and MVE have vector bic.
Commit: 4974ae5be557ab12a19748f0deff0713dd34957e
https://github.com/llvm/llvm-project/commit/4974ae5be557ab12a19748f0deff0713dd34957e
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
Log Message:
-----------
[lldb-server] Fix constexpr-if-else static assert (#194394)
Some old compilers complained about the `static_assert(false)` pattern.
Fixes https://lab.llvm.org/buildbot/#/builders/163/builds/39139
Commit: ec59f15927cccd303a5d096856f8ddb07697404e
https://github.com/llvm/llvm-project/commit/ec59f15927cccd303a5d096856f8ddb07697404e
Author: Volodymyr Turanskyy <Volodymyr.Turanskyy at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/test/Driver/baremetal.cpp
Log Message:
-----------
[clang][Driver][BareMetal] Add profile library to the command line when needed (#191847)
Now that libclang_rt.profile.a supports bare-metal targets, follow other
drivers and add libclang_rt.profile.a in the BareMetal driver to the
command line automatically when needed, e.g. when
-fprofile-instr-generate is provided.
Commit: 77a360663d640d1426e6181c17f127d8877b014a
https://github.com/llvm/llvm-project/commit/77a360663d640d1426e6181c17f127d8877b014a
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/Rematerializer.cpp
Log Message:
-----------
[CodeGen] Fix incorrect index in rematerialization tracking (#194387)
When deleting the last rematerialization of a register, we should delete
the rematerializer's remat tracking map's entry that corresponds to the
index of the *original* register, not the rematerialized register.
The existing typo has no impact on correctness at the moment because
entries with rematerialized register indices are never created (so there
is nothing to erase), and having an empty set in a value does not break
any code invariant; it just wastes memory.
Assisted-by: Claude Code
Commit: bd47069d8120c3c855a0446ef13c786517ff5c91
https://github.com/llvm/llvm-project/commit/bd47069d8120c3c855a0446ef13c786517ff5c91
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
Log Message:
-----------
Reapply "AMDGPU: Implement getInstSizeVerifyMode" (#194026) (#194362)
This reverts commit 72ca372fa7c9029d2b7a77c59a4cc24530e99e43.
Commit: 6df5ced6c4a6878da98346c8ad69ab11d76b4280
https://github.com/llvm/llvm-project/commit/6df5ced6c4a6878da98346c8ad69ab11d76b4280
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/lib/Dialect/OpenMP/Transforms/StackToShared.cpp
Log Message:
-----------
[MLIR][OpenMP] Fix sanitizer issue related to stack-to-shared pass (#194397)
The OpenMP dialect stack-to-shared pass could try to access attributes
from a deleted operation. This updates it to get that information from
the operation created to replace it.
Commit: f5bb397d204dbe14eea2b7e20337accc1a375c6f
https://github.com/llvm/llvm-project/commit/f5bb397d204dbe14eea2b7e20337accc1a375c6f
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
Log Message:
-----------
[MLIR][XeGPU] Fix Layout collapse dims out of bounds (#193661)
Fix a bug in LayoutAttr::collapseDims() implementation.
---------
Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
Commit: 8e8113fcb1bf54e7ea92151f8fb4b78fb79d3026
https://github.com/llvm/llvm-project/commit/8e8113fcb1bf54e7ea92151f8fb4b78fb79d3026
Author: jay0x <90309873+blazie2004 at users.noreply.github.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Semantics/OpenMP/workshare06.f90
Log Message:
-----------
[Flang][OpenMP] Allow Fortran BLOCK construct inside WORKSHARE region (#193352)
**Problem**
Flang incorrectly rejects Fortran BLOCK constructs inside OpenMP
WORKSHARE regions. This fixes the semantic check to recursively validate
the contents of BLOCK constructs instead of rejecting them.
The Fortran BLOCK construct (F2008) is a transparent scoping wrapper
that does not affect execution semantics. When a BLOCK appears inside a
WORKSHARE region, the restriction on allowed statements should apply to
the contents of the BLOCK, not the BLOCK construct itself.
**Fix**
The function CheckWorkshareBlockStmts (check-omp-structure.cpp) loops
through each statement inside a WORKSHARE region and checks if it's
allowed.
Before this fix, it only recognized:
```
Assignments, FORALL, WHERE statements
OpenMP constructs (ATOMIC, CRITICAL, PARALLEL)
When it saw a Fortran BLOCK, it didn't recognize it and threw an error.
```
When we see a BLOCK construct, instead of rejecting it, we "look inside"
and check if the statements inside the BLOCK are valid. This is done by
calling the same function recursively on the BLOCK's contents.
Issue : [192930](https://github.com/llvm/llvm-project/issues/192930)
---------
Co-authored-by: Jay Satish Kumar Patel <kumarpat at pe31.hpc.amslabs.hpecorp.net>
Commit: 67deb547101fa909eb8f3fbedabd2f2baa6180b1
https://github.com/llvm/llvm-project/commit/67deb547101fa909eb8f3fbedabd2f2baa6180b1
Author: Amilendra Kodithuwakku <amilendra.kodithuwakku at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_svabal.c
M clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-abal.ll
Log Message:
-----------
[Clang][AArch64][SVE2p3][SME2p3] Add intrinsics for v9.7a Two-way signed/unsigned absolute difference sum and accumulate long ops (#188972)
Add the following new clang intrinsics based on the ACLE specification
https://github.com/ARM-software/acle/pull/428 (Add alpha support for 9.7
data processing intrinsics)
SABAL (Two-way signed absolute difference sum and accumulate long)
- svint16_t svabal[_s16](svint16_t, svint8_t, svint8_t) / svint16_t
svabal[_n_s16](svint16_t, svint8_t, int8_t)
- svint32_t svabal[_s32](svint32_t, svint16_t, svint16_t) / svint32_t
svabal[_n_s32](svint32_t, svint16_t, int16_t)
- svint64_t svabal[_s64](svint64_t, svint32_t, svint32_t) / svint64_t
svabal[_n_s64](svint64_t, svint32_t, int32_t)
UABAL (Two-way unsigned absolute difference sum and accumulate long )
- svuint16_t svabal[_u16](svuint16_t, svuint8_t, svuint8_t) / svuint16_t
svabal[_n_u16](svuint16_t, svuint8_t, uint8_t)
- svuint32_t svabal[_u32](svuint32_t, svuint16_t, svuint16_t) /
svuint32_t svabal[_n_u32](svuint32_t, svuint16_t, uint16_t)
- svuint64_t svabal[_u64](svuint64_t, svuint32_t, svuint32_t) /
svuint64_t svabal[_n_u64](svuint64_t, svuint32_t, uint32_t)
Commit: 39e73ebff7fcccbfa064b1c73a33d91e44efa54e
https://github.com/llvm/llvm-project/commit/39e73ebff7fcccbfa064b1c73a33d91e44efa54e
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/partial-reduction-sub-fp.ll
Log Message:
-----------
[DAGcombine] Recognize fneg on RHS for partial_reduce_fmla (#193994)
PR #186809 recognized the negation on the fmul() expression, but after
instcombine the fneg is moved to the RHS operand, so with #186809 the
negation would not be recognized by the combine.
https://godbolt.org/z/YfoYshz78
Commit: ef18c253321fa5c0ca9f2200b9bd1f954a2b6d34
https://github.com/llvm/llvm-project/commit/ef18c253321fa5c0ca9f2200b9bd1f954a2b6d34
Author: Jakob Linke <jakob at linke.cx>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/include/clang/AST/ASTFwd.h
M clang/include/clang/AST/ASTTypeTraits.h
M clang/include/clang/AST/DynamicRecursiveASTVisitor.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/lib/AST/ASTTypeTraits.cpp
M clang/lib/AST/DynamicRecursiveASTVisitor.cpp
M clang/unittests/Tooling/CMakeLists.txt
A clang/unittests/Tooling/RecursiveASTVisitorTests/OffsetOfExpr.cpp
Log Message:
-----------
[Clang][RAV] Visit components of __builtin_offsetof designators (#194122)
`RecursiveASTVisitor` previously only traversed the type operand of an
`OffsetOfExpr,` ignoring the field/identifier/base/array-index
components of the designator. This meant tools built on RAV (clang-tidy,
clangd, indexers, ...) silently missed every field reference inside
`__builtin_offsetof(T, a.b.c)`.
Add a `TraverseOffsetOfNode / VisitOffsetOfNode` pair following the same
pattern used for `ConceptReference`, `ObjCProtocolLoc`, and friends. The
`DEF_TRAVERSE_STMT` for `OffsetOfExpr` now invokes
`TraverseOffsetOfNode` for each component; array index expressions
continue to be reached via the existing children() traversal. Default
visitation is a no-op, so the change is opt-in for consumers and
behavior-preserving otherwise.
Also expose `OffsetOfNode` as a `DynTypedNode` kind via `ASTTypeTraits`
so that downstream machinery (`SelectionTree`, parent maps, matchers)
can reference these nodes uniformly.
The same gap exists for Designator inside `DesignatedInitExpr` and can
follow this recipe in a follow-up.
Related: https://github.com/llvm/llvm-project/pull/192953. The current
PR enables precise component resolves in clangd (support to be added in
a followup).
Commit: 2e5f8b2e12955bba4ef9e04a678ff079f809fa94
https://github.com/llvm/llvm-project/commit/2e5f8b2e12955bba4ef9e04a678ff079f809fa94
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M libc/config/linux/x86_64/headers.txt
M libc/include/CMakeLists.txt
A libc/include/sys/ucontext.h
Log Message:
-----------
[libc] Add sys/ucontext.h header (#194329)
POSIX historically provided <sys/ucontext.h> as an alias for
<ucontext.h>. Some software still includes the sys/ path. Added the
header as a simple wrapper that includes <ucontext.h>, gated to x86_64
alongside the existing ucontext support.
Commit: 395a56301ddc0ad641fb0dbcef7184f72640fe9d
https://github.com/llvm/llvm-project/commit/395a56301ddc0ad641fb0dbcef7184f72640fe9d
Author: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR] Vector-Saturating-shift-left intrinsics (#190728)
Part of #185382
1. Added NEON::BI__builtin_neon_vqshlud_n_s64:
2. Added NEON::BI__builtin_neon_vqshld_n_u64:
3. Added NEON::BI__builtin_neon_vqshld_u_u64:
Commit: 2a83068537786696d4950ce694e7d34480631f48
https://github.com/llvm/llvm-project/commit/2a83068537786696d4950ce694e7d34480631f48
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/PowerPC/P10InstrResources.td
M llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCMacroFusion.def
M llvm/lib/Target/PowerPC/PPCRegisterClasses.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/PowerPC/PPCScheduleP7.td
Log Message:
-----------
[PowerPC] Enable using HwMode for instructions (#191051)
The HwMode is already used for operands representing an effective
address. It can also be used for general purpose registers but this is
not clear from the naming. This change
- introduces the hw-mode dependent register class `GxRC`, and the
associated register operands
- removes register class `ptr_rc_idx_by_hwmode`, and replaces the only
use with `gxrc`
- uses the `EQV` instruction as an example how to use the new class
Commit: e33bac0f2c4ccbabe1d58ee82e0985c8e780d606
https://github.com/llvm/llvm-project/commit/e33bac0f2c4ccbabe1d58ee82e0985c8e780d606
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M lldb/include/lldb/Utility/StringExtractorGDBRemote.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
M lldb/source/Utility/StringExtractorGDBRemote.cpp
M lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
Log Message:
-----------
[lldbremote] Implement support for MultiBreakpoint packet (#192919)
This is fairly straightforward, thanks to the helper functions created
in the previous commit.
The following PRs are related to the MultiBreakpoint feature:
* https://github.com/llvm/llvm-project/pull/192910
* https://github.com/llvm/llvm-project/pull/192914
* https://github.com/llvm/llvm-project/pull/192915
* https://github.com/llvm/llvm-project/pull/192919
* https://github.com/llvm/llvm-project/pull/192962
* https://github.com/llvm/llvm-project/pull/192964
* https://github.com/llvm/llvm-project/pull/192971
* https://github.com/llvm/llvm-project/pull/192988
Commit: 4f3bed19b0aaff893ef0f0329eccda9016cd2f3d
https://github.com/llvm/llvm-project/commit/4f3bed19b0aaff893ef0f0329eccda9016cd2f3d
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/DirectX/DirectXIRPasses/PointerTypeAnalysis.cpp
A llvm/test/CodeGen/DirectX/global-variable.ll
A llvm/test/tools/dxil-dis/opaque-pointers-var.ll
Log Message:
-----------
[DirectX] Emit unresolved ptr as i8* (#192086)
We cannot use dxilOpaquePtrReservedName in this test as that is the
wrong type for the null initializer.
Commit: b5f3c12c02d8384868845f5bd82f171947917d15
https://github.com/llvm/llvm-project/commit/b5f3c12c02d8384868845f5bd82f171947917d15
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVPassRegistry.def
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
A llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.h
M llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.cpp
A llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
A llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareFunctions.ll
M llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareGlobals-predicate-id-string.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareGlobals.ll
M llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll
Log Message:
-----------
[SPIR-V][NewPM] Register SPIRVPrepareFunctions and SPIRVPrepareGlobals with the new pass manager (#194024)
Rename the legacy pass IDs to spirv-prepare-functions and
spirv-prepare-globals for consistency with the other SPIR-V passes and
add opt-driven lit tests for both passes
Commit: 0b8f8264d687d75165dffa6f2cd80f715a864b86
https://github.com/llvm/llvm-project/commit/0b8f8264d687d75165dffa6f2cd80f715a864b86
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
Log Message:
-----------
[PowerPC] Simplify implementation of atomis loads (#191044)
The code for atomic loads is verbose. There are 10 different operations
and 4 memory sizes to support, which means 40 pseudo instructions are
used, with all the details repeated. This PR changes the following:
- Use a loop over the operations and the sizes to create the pseudo
instruction
- Adds the memory size as last operand to the pseudo instruction
- Updates the C++ code to take advantage of the memory size in the
pseudo instruction
Commit: e52e9e33fc0c11172ac4b9c22793e269b538404d
https://github.com/llvm/llvm-project/commit/e52e9e33fc0c11172ac4b9c22793e269b538404d
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/test/Dialect/SPIRV/IR/types.mlir
Log Message:
-----------
[mlir][spirv] Add CoopMatrix type tests for fp8 and bf16 element types (#193805)
Commit: 4d20831a6562ecc5e0b87d5785b2911060c3ab41
https://github.com/llvm/llvm-project/commit/4d20831a6562ecc5e0b87d5785b2911060c3ab41
Author: Brendan Dahl <brendan.dahl at gmail.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
Log Message:
-----------
[WebAssembly] Support f16x8.demote_f32x4_zero (#193564)
Add support for the f16x8.demote_f32x4_zero instruction. This
instruction converts a v4f32 vector to a v4f16 and pads the result with
zeros to fill the 128-bit register.
This enables efficient lowering of fptrunc operations from v4f32 to
v4f16 when the result is zero-extended or when only the low lanes are
needed. A DAG combine is included to recognize these patterns and fold
them into the new instruction.
Commit: 35fffe03aefcdc088d3bc0c1410d179ca33b8fd4
https://github.com/llvm/llvm-project/commit/35fffe03aefcdc088d3bc0c1410d179ca33b8fd4
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
Log Message:
-----------
[mlir][spirv] Add missing capabilities for CoopMatrix in TypeExtensionVisitor (#193803)
This adds missing capabilities when CoopMatrix is used with bf16 and
fp8.
Assisted-by: Codex
Commit: 1b065445a6b81c00d7a816d64708731ad8807f70
https://github.com/llvm/llvm-project/commit/1b065445a6b81c00d7a816d64708731ad8807f70
Author: adams381 <adams at nvidia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGenBuiltins/builtin-float.c
Log Message:
-----------
[CIR] Emit frexp, modf, and powi builtins as library calls (#193795)
`__builtin_frexpf`, `__builtin_modf`, `__builtin_powi`, and related
builtins were incorrectly falling through to the `__builtin_isnan`
handler in `emitBuiltinExpr`, which calls `createBoolToInt` /
`createIsFPClass`. This produced a `cir.cast` with an integer result
type when the actual return type is floating-point, failing CIR
verification.
Break out of the switch so these builtins fall through to the
`isLibFunction()` path, which emits them as regular library calls.
Made with [Cursor](https://cursor.com)
Commit: d071e4b765dfadc1472b97d09f5014c92ab27ead
https://github.com/llvm/llvm-project/commit/d071e4b765dfadc1472b97d09f5014c92ab27ead
Author: adams381 <adams at nvidia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
A clang/test/CIR/CodeGen/try-no-throwing-calls.cpp
Log Message:
-----------
[CIR] Fix eraseOp assertion in TryOp flattening with unreachable handlers (#193615)
When a try block has catch handlers but no throwing calls, the handler
regions are unreachable and the TryOp is erased. However, ops inside the
handler regions may reference values that were inlined from the try body
into the parent block, causing an assertion in `eraseOp` ("expected that
op has no uses").
This drops all defined value uses from handler regions before erasing
the TryOp.
Made with [Cursor](https://cursor.com)
Commit: 916cd558c10bf520dd0c1bdd3849fa6163b53795
https://github.com/llvm/llvm-project/commit/916cd558c10bf520dd0c1bdd3849fa6163b53795
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/test/CodeGenCXX/mangle-requires.cpp
Log Message:
-----------
[Clang] Avoid an extra `FunctionPrototypeScope` for lambda trailing requires-clauses (#194068)
`ParseTrailingRequiresClause` currently always creates a synthetic
`FunctionPrototypeScope`. This is needed for ordinary function
declarators
whose prototype scope has already ended, but it is wrong for lambda
trailing
requires-clauses because they are parsed while the lambda prototype
scope is
still active.
The extra counted scope gives parameters in nested requires-expressions
an
incorrect function scope depth. Split the synthetic prototype-scope
setup from
the trailing requires-clause parser so the lambda path can parse the
clause in
the existing prototype scope.
Fixes: #123854
Fixes: #100774
Commit: cf4f678f0448803be0fb98545336ca902352bc65
https://github.com/llvm/llvm-project/commit/cf4f678f0448803be0fb98545336ca902352bc65
Author: Ivan R. Ivanov <iivanov at nvidia.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M offload/plugins-nextgen/common/src/PluginInterface.cpp
Log Message:
-----------
[Offload] Make kernel dynamic memory handling more generic (#194403)
Make sure we do not get unexpected NumThreads and NumBlocks values when
launching non-bare kernels, and generalize the computation of the
dynamic block memory allocation to handle multi-dimensional blocks.
The DynBlockMem fallback is never used in a non-bare context where
`NumBlocks[1]` and `NumBlocks[2]` are not 1 so the code was correct, but
this patch makes sure that assumption is made explicit, and also
future-proofs the code in case we decide to allow multi-dimensional
blocks for fallback dyn block mem in some path.
Commit: 71d63d61072166d7ba744464db8781389a3474c9
https://github.com/llvm/llvm-project/commit/71d63d61072166d7ba744464db8781389a3474c9
Author: Alex Langford <alangford at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M lldb/test/API/functionalities/inline-sourcefile/Makefile
Log Message:
-----------
[lldb][test] Fix Makefile for TestInlineSourceFiles.py (#194078)
The test did not build hidden.o with a custom target triple when
specified. Use CFLAGS from Makefile.rules to fix.
Commit: fb4ce472adb9f65acb150d4e2db5446524458b90
https://github.com/llvm/llvm-project/commit/fb4ce472adb9f65acb150d4e2db5446524458b90
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/DirectX/CMakeLists.txt
M llvm/lib/Target/DirectX/DXILWriter/CMakeLists.txt
M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h
M llvm/lib/Target/DirectX/DXILWriter/DXILValueEnumerator.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILValueEnumerator.h
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
M llvm/lib/Target/DirectX/DirectXIRPasses/CMakeLists.txt
A llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
A llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.h
M llvm/unittests/Target/DirectX/CMakeLists.txt
Log Message:
-----------
[DirectX] Add DXILDebugInfo pass (#191254)
The pass is enabled for DXILBitcodeWriter and ValueEnumerator to
transform LLVM IR and provide data required to lower it to DXIL.
There are 3 ways how DXILDebugInfo pass can change lowering to DXIL:
1. Transform LLVM IR directly in DXILDebugInfoPass::run. This works well
when the target IR does not break any invariants of LLVM IR.
2. Add extra metadata for ValueEnumerator to process with MDExtra map.
When ValueEnumerator enumerates a Key of MDExtra, it also follows the
Value and all its operands.
3. Replace a metadata for ValueEnumerator with a another metadata. When
ValueEnumerator enumerates a Key of MDReplace, or when the writer uses
getMetadataID, the corresponding value of MDReplace map is returned
instead.
Co-authored-by: Andrew Savonichev <andrew.savonichev at gmail.com>
Commit: 5fb8cb1508eef28f7ee7612e335bb907bcf8ead5
https://github.com/llvm/llvm-project/commit/5fb8cb1508eef28f7ee7612e335bb907bcf8ead5
Author: Alex Langford <alangford at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M lldb/test/API/macosx/arm-pointer-metadata-cfa-dwarf-expr/Makefile
Log Message:
-----------
[lldb][test] Fix Makefile for TestArmPointerMetadataCFADwarfExpr.py (#194075)
The makefile did not respect custom target triples. Fixed by using
CFLAGS from Makefile.rules.
Commit: 0065d2e62be6f5f732bf32ecb1fe7f24a0de86e5
https://github.com/llvm/llvm-project/commit/0065d2e62be6f5f732bf32ecb1fe7f24a0de86e5
Author: Alex Langford <alangford at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M lldb/test/API/functionalities/valobj_errors/Makefile
Log Message:
-----------
[lldb][test] Fix Makefile for TestValueObjectErrors.py (#194071)
This test does not respect custom triples. hidden.c is intended to be
built with no debug info, so pass `-g0` after CFLAGS.
Commit: 1c62578d1a051dd63f5d2594ca0d85eac13d5c3d
https://github.com/llvm/llvm-project/commit/1c62578d1a051dd63f5d2594ca0d85eac13d5c3d
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Transforms/InstCombine/RISCV/riscv-vmv-v-x.ll
Log Message:
-----------
[RISCV] Fix inf-loop on equal num-elts in vmv.v.x fold (#194410)
Commit: d9b7786e74f8decbbd286f2495309f4e6d488f95
https://github.com/llvm/llvm-project/commit/d9b7786e74f8decbbd286f2495309f4e6d488f95
Author: David Green <david.green at arm.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
M llvm/test/CodeGen/AArch64/neon-saba.ll
Log Message:
-----------
[AArch64] Addition tests for add_like Or of saba. NFC (#194416)
Commit: b39057a228804e7f920a04e466dc2e97e2e75442
https://github.com/llvm/llvm-project/commit/b39057a228804e7f920a04e466dc2e97e2e75442
Author: Raphael Isemann <rise at apple.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
R lldb/test/API/functionalities/dead-strip/cmds.txt
R lldb/test/API/functionalities/load_unload/cmds.txt
R lldb/test/API/lang/c/array_types/cmds.txt
R lldb/test/API/lang/c/global_variables/cmds.txt
R lldb/test/API/lang/cpp/class_types/cmds.txt
R lldb/test/API/lang/cpp/namespace/cmds.txt
R lldb/test/API/lang/cpp/stl/cmds.txt
R lldb/test/API/macosx/order/cmds.txt
Log Message:
-----------
[lldb][test] Delete obsolete cmds.txt (#194390)
Last time I asked about these files someone mentioned they were once
used to replay a test.
However, I think by now these files are mostly out of sync with their
tests and few people anyway know these files exist in the first place.
Commit: 8d9299cd7af594767485c5d73b5a103b949b7700
https://github.com/llvm/llvm-project/commit/8d9299cd7af594767485c5d73b5a103b949b7700
Author: Joshua Cranmer <joshua.cranmer at intel.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/AsmParser/LLLexer.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/test/Assembler/2006-09-28-CrashOnInvalid.ll
A llvm/test/Assembler/float-literals.ll
A llvm/test/Assembler/invalid-call-float-literal.ll
A llvm/test/Assembler/invalid-uselistorder_bb-float-literal.ll
M llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
M llvm/unittests/AsmParser/AsmParserTest.cpp
Log Message:
-----------
[AsmParser] Revamp how floating-point literals work in LLVM IR. (#190641)
This adds support for the following kinds of formats:
* Hexadecimal literals like 0x1.fp13
* Special values +inf/-inf, +qnan/-qnan
* NaN values with payloads like +nan(0x1)
Additionally, the floating-point hexadecimal format that records the
bitpattern exactly no longer requires the 0xL or 0xK or similar code for
the floating-point type. The current hexadecimal syntax is retained for
the moment, but it is expected to be ripped out after the next release
of LLVM.
These changes were discussed in an RFC at
https://discourse.llvm.org/t/rfc-floating-point-literals-in-llvm-ir/82974.
Commit: 18053e3c6ac0c57a43d9b5db5d5a7db9675ef364
https://github.com/llvm/llvm-project/commit/18053e3c6ac0c57a43d9b5db5d5a7db9675ef364
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-with-multi-used-expanded.ll
Log Message:
-----------
[SLP]Bail out on non-schedulable expanded binop with multi-use operand
In tryScheduleBundle's DoesNotRequireScheduling path, an expanded binop
(shl X, 1 modeled as add X, X) doubles the dependency count of the
duplicated operand. Unlike the regular scheduling path, this branch does
not clear stale operand ScheduleData dependencies, so when that operand
has more uses than this bundle member the schedule's decrement count
exceeds calculateDependencies' increment count and UnscheduledDeps goes
negative, hitting "Expected valid number of unscheduled deps".
Fixes #194303.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/194420
Commit: 4bab7ea656a03bf8e58ec3b2e25f664f4fb57b45
https://github.com/llvm/llvm-project/commit/4bab7ea656a03bf8e58ec3b2e25f664f4fb57b45
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-27 (Mon, 27 Apr 2026)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M .gitignore
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Passes/CMOVConversion.cpp
M bolt/test/AArch64/unsupported-passes.test
M clang-tools-extra/clangd/Config.h
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTFwd.h
M clang/include/clang/AST/ASTTypeTraits.h
M clang/include/clang/AST/DynamicRecursiveASTVisitor.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Parse/Parser.h
M clang/lib/AST/ASTTypeTraits.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/DynamicRecursiveASTVisitor.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
A clang/lib/CIR/CodeGen/CIRGenOpenMPRuntime.cpp
A clang/lib/CIR/CodeGen/CIRGenOpenMPRuntime.h
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuilder.h
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Parse/ParseCXXInlineMethods.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseStmtAsm.cpp
M clang/lib/Sema/SemaCoroutine.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx17.cpp
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures-co_await-assertion-failure.cpp
M clang/test/Analysis/more-dtors-cfg-output.cpp
A clang/test/CIR/CodeGen/try-no-throwing-calls.cpp
A clang/test/CIR/CodeGenBuiltins/builtin-float.c
A clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
A clang/test/CIR/CodeGenOpenMP/emit-device-functions.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
A clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
A clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_addqp.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_addsubp.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_subp.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_svabal.c
A clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
M clang/test/CodeGenCXX/mangle-requires.cpp
M clang/test/CodeGenCXX/ubsan-coroutines.cpp
M clang/test/CodeGenCoroutines/coro-params.cpp
M clang/test/CodeGenCoroutines/coro-promise-dtor.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
A clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
A clang/test/CodeGenHLSL/resources/cbuffer_struct_passing.hlsl
A clang/test/CodeGenHLSL/resources/cbuffer_struct_passing.logical.hlsl
M clang/test/DebugInfo/Generic/codeview-buildinfo.c
M clang/test/Driver/baremetal.cpp
M clang/test/Lexer/cxx-features.cpp
M clang/test/Modules/coro-await-elidable.cppm
M clang/test/PCH/coroutines.cpp
M clang/test/Parser/cxx20-coroutines.cpp
M clang/test/Parser/static_assert.cpp
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve-b16mm.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p2_AND_f16mm.c
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
A clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3.cpp
M clang/test/SemaCXX/addr-label-in-coroutines.cpp
M clang/test/SemaCXX/co_await-ast.cpp
M clang/test/SemaCXX/coroutine-alloc-2.cpp
M clang/test/SemaCXX/coroutine-alloc-3.cpp
M clang/test/SemaCXX/coroutine-alloc-4.cpp
M clang/test/SemaCXX/coroutine-allocs.cpp
M clang/test/SemaCXX/coroutine-builtins.cpp
M clang/test/SemaCXX/coroutine-dealloc.cpp
M clang/test/SemaCXX/coroutine-final-suspend-noexcept.cpp
M clang/test/SemaCXX/coroutine-no-valid-dealloc.cpp
M clang/test/SemaCXX/coroutine-noreturn.cpp
M clang/test/SemaCXX/coroutine-promise-ctor.cpp
M clang/test/SemaCXX/coroutine-rvo.cpp
M clang/test/SemaCXX/coroutine-traits-undefined-template.cpp
M clang/test/SemaCXX/coroutine-unevaluate.cpp
M clang/test/SemaCXX/coroutine-vla.cpp
A clang/test/SemaCXX/coroutine-win32x86.cpp
M clang/test/SemaCXX/coroutine_handle-address-return-type.cpp
M clang/test/SemaCXX/coroutines.cpp
M clang/test/SemaCXX/cxx17-compat.cpp
M clang/test/SemaCXX/cxx20-delayed-typo-correction-crashes.cpp
M clang/test/SemaCXX/cxx2b-deducing-this-coro.cpp
M clang/test/SemaCXX/lambda-unevaluated.cpp
M clang/test/SemaCXX/thread-safety-coro.cpp
M clang/test/SemaCXX/warn-throw-out-noexcept-coro.cpp
M clang/test/SemaCXX/warn-unused-parameters-coroutine.cpp
M clang/tools/driver/cc1as_main.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestComments.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Tooling/CMakeLists.txt
A clang/unittests/Tooling/RecursiveASTVisitorTests/OffsetOfExpr.cpp
M clang/www/cxx_status.html
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_dlsym.h
M compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/include/flang/Semantics/tools.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Semantics/canonicalize-acc.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/tools.cpp
M flang/test/Fir/basic-program.fir
M flang/test/Integration/OpenMP/target-use-device-nested.f90
M flang/test/Integration/OpenMP/threadprivate-target-device.f90
M flang/test/Lower/OpenACC/Todo/do-loops-to-acc-loops-todo.f90
M flang/test/Lower/OpenMP/target-map-complex.f90
A flang/test/Lower/OpenMP/tile-parallel-do.f90
M flang/test/Lower/c-interoperability.f90
A flang/test/Lower/host_module_variable_instantiation.f90
M flang/test/Lower/pointer-initial-target-2.f90
M flang/test/Lower/pointer-initial-target.f90
M flang/test/Lower/pointer-references.f90
M flang/test/Lower/pointer-results-as-arguments.f90
M flang/test/Lower/pointer-runtime.f90
A flang/test/Lower/proc_pointer_hidden_by_generic.f90
M flang/test/Semantics/OpenACC/acc-canonicalization-validity.f90
M flang/test/Semantics/OpenACC/acc-loop.f90
A flang/test/Semantics/OpenMP/workshare06.f90
M libc/config/linux/x86_64/headers.txt
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_cmsghdr.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/sys-socket-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_cmsghdr.h
M libc/include/sys/socket.yaml
A libc/include/sys/ucontext.h
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/sendmsg_recvmsg_test.cpp
A libc/utils/docgen/sys/sem.yaml
M libcxx/utils/ci/run-buildbot
M libcxxabi/src/cxa_personality.cpp
M libunwind/src/AddressSpace.hpp
M libunwind/src/DwarfParser.hpp
M lldb/include/lldb/Utility/StringExtractorGDBRemote.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
M lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
M lldb/source/Utility/StringExtractorGDBRemote.cpp
R lldb/test/API/functionalities/dead-strip/cmds.txt
M lldb/test/API/functionalities/inline-sourcefile/Makefile
R lldb/test/API/functionalities/load_unload/cmds.txt
A lldb/test/API/functionalities/multi-breakpoint/Makefile
A lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
A lldb/test/API/functionalities/multi-breakpoint/main.c
M lldb/test/API/functionalities/valobj_errors/Makefile
R lldb/test/API/lang/c/array_types/cmds.txt
R lldb/test/API/lang/c/global_variables/cmds.txt
R lldb/test/API/lang/cpp/class_types/cmds.txt
R lldb/test/API/lang/cpp/namespace/cmds.txt
R lldb/test/API/lang/cpp/stl/cmds.txt
M lldb/test/API/lang/objc/modules-auto-import/TestModulesAutoImport.py
M lldb/test/API/lang/objc/modules-auto-import/main.m
M lldb/test/API/macosx/arm-pointer-metadata-cfa-dwarf-expr/Makefile
R lldb/test/API/macosx/order/cmds.txt
M lldb/tools/debugserver/source/JSON.h
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/tools/debugserver/source/RNBRemote.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPSessionManager.cpp
M lldb/tools/lldb-dap/EventHelper.cpp
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/ADT/FoldingSet.h
M llvm/include/llvm/ADT/STLExtras.h
M llvm/include/llvm/ADT/StableHashing.h
M llvm/include/llvm/AsmParser/LLLexer.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/include/llvm/Transforms/Utils/CodeExtractor.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp
M llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h
M llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
M llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCDisassembler/Disassembler.cpp
M llvm/lib/Object/ModuleSymbolTable.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Support/FoldingSet.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOPDInstructions.td
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/DirectX/CMakeLists.txt
M llvm/lib/Target/DirectX/DXILWriter/CMakeLists.txt
M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h
M llvm/lib/Target/DirectX/DXILWriter/DXILValueEnumerator.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILValueEnumerator.h
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
M llvm/lib/Target/DirectX/DirectXIRPasses/CMakeLists.txt
A llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
A llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.h
M llvm/lib/Target/DirectX/DirectXIRPasses/PointerTypeAnalysis.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
M llvm/lib/Target/M68k/M68kMCInstLower.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/P10InstrResources.td
M llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCMacroFusion.def
M llvm/lib/Target/PowerPC/PPCRegisterClasses.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/PowerPC/PPCScheduleP7.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVPassRegistry.def
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
A llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.h
M llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.cpp
A llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/HotColdSplitting.cpp
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Assembler/2006-09-28-CrashOnInvalid.ll
A llvm/test/Assembler/float-literals.ll
A llvm/test/Assembler/invalid-call-float-literal.ll
A llvm/test/Assembler/invalid-uselistorder_bb-float-literal.ll
A llvm/test/CodeGen/AArch64/aarch64-no-mov-spill-chain.ll
M llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
A llvm/test/CodeGen/AArch64/neon-matmul-f16.ll
A llvm/test/CodeGen/AArch64/neon-matmul-f16f32mm.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-saba.ll
M llvm/test/CodeGen/AArch64/partial-reduction-sub-fp.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
A llvm/test/CodeGen/AArch64/sanitize_vec_pow.ll
A llvm/test/CodeGen/AArch64/scvtf-div-mul-combine.ll
A llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-bf16.ll
A llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-f16.ll
A llvm/test/CodeGen/AArch64/sve-masked-ldst-alias-analysis.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-abal.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-addqp.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-addsubp.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-subp.ll
M llvm/test/CodeGen/AArch64/veclib-llvm.pow.ll
A llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll
A llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
A llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
M llvm/test/CodeGen/ARM/vbits.ll
A llvm/test/CodeGen/DirectX/global-variable.ll
A llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
M llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fpext.ll
A llvm/test/CodeGen/LoongArch/stackslot.mir
M llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
M llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
A llvm/test/CodeGen/NVPTX/unknown-intrinsic.ll
M llvm/test/CodeGen/PowerPC/masked-sdiv.ll
M llvm/test/CodeGen/PowerPC/masked-srem.ll
M llvm/test/CodeGen/PowerPC/masked-udiv.ll
M llvm/test/CodeGen/PowerPC/masked-urem.ll
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/incorrect-extract-subvector-combine.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareFunctions.ll
M llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareGlobals-predicate-id-string.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareGlobals.ll
M llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll
M llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
M llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
M llvm/test/CodeGen/X86/dag-topological-sort.ll
M llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll
R llvm/test/CodeGen/X86/gc-empty-basic-blocks.mir
M llvm/test/CodeGen/X86/machine-block-hash.mir
M llvm/test/CodeGen/X86/pr134602.ll
M llvm/test/CodeGen/X86/vselect-avx.ll
A llvm/test/ExecutionEngine/Interpreter/test-interp-variable-arguments.ll
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd_unused_operands.txt
A llvm/test/Transforms/AggressiveInstCombine/fold-split-ctlz.ll
A llvm/test/Transforms/AggressiveInstCombine/fold-split-cttz.ll
M llvm/test/Transforms/FunctionAttrs/nosync.ll
M llvm/test/Transforms/GVN/tbaa.ll
M llvm/test/Transforms/GlobalOpt/ctor-memset.ll
M llvm/test/Transforms/GlobalOpt/pr54572.ll
M llvm/test/Transforms/InstCombine/RISCV/riscv-vmv-v-x.ll
M llvm/test/Transforms/InstCombine/and-xor-or.ll
M llvm/test/Transforms/InstCombine/binop-and-shifts.ll
A llvm/test/Transforms/InstCombine/shift-sub.ll
M llvm/test/Transforms/InstSimplify/load.ll
M llvm/test/Transforms/LoopFusion/double_loop_nest_inner_guard.ll
M llvm/test/Transforms/LoopFusion/triple_loop_nest_inner_guard.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
A llvm/test/Transforms/LoopVectorize/VPlan/widen-canonical-iv-register-pressure.ll
A llvm/test/Transforms/LoopVectorize/X86/widen-canonical-iv-register-pressure.ll
M llvm/test/Transforms/LoopVectorize/hints-trans.ll
M llvm/test/Transforms/LoopVectorize/scalable-trunc-min-bitwidth.ll
A llvm/test/Transforms/OpenMP/spirv_ctor.ll
A llvm/test/Transforms/SLPVectorizer/X86/identity-reuses-with-poisons.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-with-multi-used-expanded.ll
A llvm/test/tools/dxil-dis/opaque-pointers-var.ll
M llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
M llvm/tools/llvm-dwp/llvm-dwp.cpp
M llvm/tools/llvm-exegesis/lib/DisassemblerHelper.cpp
M llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
M llvm/tools/llvm-mc/llvm-mc.cpp
M llvm/tools/llvm-mca/llvm-mca.cpp
M llvm/tools/llvm-ml/Disassembler.cpp
M llvm/tools/llvm-ml/llvm-ml.cpp
M llvm/tools/llvm-objdump/MachODump.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
M llvm/tools/sancov/sancov.cpp
M llvm/unittests/AsmParser/AsmParserTest.cpp
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/unittests/CodeGen/MachineOperandTest.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
M llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/MC/AMDGPU/Disassembler.cpp
M llvm/unittests/MC/DwarfDebugFrameCIE.cpp
M llvm/unittests/MC/DwarfLineTableHeaders.cpp
M llvm/unittests/MC/DwarfLineTables.cpp
M llvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp
M llvm/unittests/MC/SystemZ/SystemZMCDisassemblerTest.cpp
M llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp
M llvm/unittests/Support/xxhashTest.cpp
M llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp
M llvm/unittests/Target/DirectX/CMakeLists.txt
M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
M llvm/unittests/tools/llvm-mca/MCATestBase.cpp
M llvm/utils/lit/lit/TestingConfig.py
M llvm/utils/lit/tests/shtest-ulimit-nondarwin.py
M mlir/docs/Passes.md
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/Transforms/Passes.h
M mlir/include/mlir/Dialect/OpenMP/Transforms/Passes.td
A mlir/include/mlir/Dialect/OpenMP/Utils/Utils.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/lib/Dialect/OpenMP/CMakeLists.txt
A mlir/lib/Dialect/OpenMP/IR/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
A mlir/lib/Dialect/OpenMP/Transforms/StackToShared.cpp
A mlir/lib/Dialect/OpenMP/Utils/CMakeLists.txt
A mlir/lib/Dialect/OpenMP/Utils/Utils.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTosaOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Target/LLVM/ROCDL/Target.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Dialect/LLVMIR/nvvm-transcendentals.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Dialect/MemRef/elide-reinterpret-cast.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
A mlir/test/Dialect/OpenMP/stack-to-shared.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/types.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Target/LLVMIR/nvvm/transcendentals.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-constant-alloca-raise.mlir
A mlir/test/Target/LLVMIR/omptarget-device-shared-mem.mlir
A mlir/test/Target/LLVMIR/omptarget-device-shared-memory.mlir
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
M mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir
M mlir/test/Target/LLVMIR/omptarget-region-device-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-target-generic-spmd.mlir
M mlir/test/Target/LLVMIR/openmp-target-private-allocatable.mlir
A mlir/test/Target/LLVMIR/openmp-target-private-shared-mem.mlir
M offload/liboffload/API/Device.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/plugins-nextgen/level_zero/dynamic_l0/L0DynWrapper.cpp
M offload/plugins-nextgen/level_zero/dynamic_l0/level_zero/ze_api.h
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/test/offloading/ctor_dtor.cpp
A offload/test/offloading/fortran/target-generic-loops.f90
A offload/test/offloading/fortran/target-generic-outlined-loops.f90
A offload/test/offloading/fortran/target-spmd-loops.f90
M offload/tools/deviceinfo/llvm-offload-device-info.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
M openmp/runtime/src/kmp_taskdeps.cpp
M openmp/runtime/src/kmp_tasking.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Address comments
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/bb4aebb8699b...4bab7ea656a0
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list