[all-commits] [llvm/llvm-project] cf30e4: [AArch64] Enable Spillage Copy Elimination by defa...

[Jack Styles via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf30e4b5c2d55e217ade2483c4672f2488da48df
      https://github.com/llvm/llvm-project/commit/cf30e4b5c2d55e217ade2483c4672f2488da48df
  Author: Jack Styles <jack.styles at arm.com>
  Date:   2026-04-27 (Mon, 27 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    A llvm/test/CodeGen/AArch64/aarch64-no-mov-spill-chain.ll
    M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll

  Log Message:
  -----------
  [AArch64] Enable Spillage Copy Elimination by default (#186093)

In times of high register pressure, the greedy register allocator can
emit large eviction chains that consist of many `mov` instructions. The
Spillage Copy Elimination pass handles this, by finding these chains and
decreasing their impact. Take a mov chain such as the following where
`x8` is used for an 8-byte Folded Reload:
```
mov x7, x6
mov x6, x5
mov x5, x4
mov x4, x3
mov x3, x2
mov x2, x1
mov x1, x30
mov x30, x8
< use x8 >
mov x8, x30
mov x30, x1
mov x1, x2
mov x2, x3
mov x3, x4
mov x4, x5
mov x5, x6
mov x6, x7
```
Becomes:
```
mov x7, x6
mov x6, x8
< use x8 >
mov x8, x6
mov x6, x7
```

This provides performance benefits for long mov chains, where we are no
longer needing to copy these values between registers.

This does introduce compile time regressions, as was originally noted in
the initial review. From my testing, this was around 0.17% on average
using LLVM Test Suite.

Further information:
Original Review: https://reviews.llvm.org/D122118
Compile Time Regression information from original review:
http://llvm-compile-time-tracker.com/compare.php?from=781eabeb40b8e47e3a46b0b927784e63f0aad9ab&to=0af2744a89bf0ed05e83ac1ed9d21d6d74cdfeca&stat=instructions%3Au

Assisted-by: codex (Generation of new test)



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