[all-commits] [llvm/llvm-project] 0a11c0: [gn build] Port ad2bf491badb (#192461)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Fri Apr 17 14:12:12 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slp-improve-cost-model-for-i1-select-as-orand-patterns
Home: https://github.com/llvm/llvm-project
Commit: 0a11c04f42666dfb838d08d5176b474256a8f22f
https://github.com/llvm/llvm-project/commit/0a11c04f42666dfb838d08d5176b474256a8f22f
Author: Nico Weber <thakis at chromium.org>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
Log Message:
-----------
[gn build] Port ad2bf491badb (#192461)
Commit: 0e3f5504beb0e4ac918f6934fdc7cbf847014e9d
https://github.com/llvm/llvm-project/commit/0e3f5504beb0e4ac918f6934fdc7cbf847014e9d
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll
M llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll
M llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll
A llvm/test/CodeGen/SPIRV/struct-null-pointer-member.ll
Log Message:
-----------
[SPIR-V] Simplify addrspacecast for null in composite constant preprocessing (#192030)
Fold addrspacecast(null) to a typed null pointer during composite
constant preprocessing so that null pointer members in structs and
arrays get the correct SPIR-V pointer type instead of being lowered as
integers. This fixes invalid SPIR-V where OpConstantNull had an integer
type instead of a pointer type, and where OpSpecConstantOp was
unnecessarily emitted for null casts
related to https://github.com/llvm/llvm-project/issues/190736
Commit: 2c67f2fdfc41afd9acfe28e3cb42850a97f1db54
https://github.com/llvm/llvm-project/commit/2c67f2fdfc41afd9acfe28e3cb42850a97f1db54
Author: Georgiy Samoylov <Ignitor21838 at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/include/llvm/MC/TargetRegistry.h
M llvm/lib/MC/TargetRegistry.cpp
M llvm/unittests/MC/TargetRegistry.cpp
Log Message:
-----------
[llvm] Add format check for MCSubtargetFeatures (#180943)
`SubtargetFeatures` class has next constraints:
https://github.com/llvm/llvm-project/blob/c9d065abc15846deb95a23fb0b3e1855d3d26314/llvm/include/llvm/TargetParser/SubtargetFeature.h#L167-L174
At this moment feature string isn't checked for fitting in such format.
This leads to assertion failure, for example in lldb:
https://github.com/llvm/llvm-project/pull/180901, when features from
user's input don't meet the requirements.
With implementing additional format check we can avoid such problems.
Commit: 925e2156c71da60a61f1199960f5fff82de35f57
https://github.com/llvm/llvm-project/commit/925e2156c71da60a61f1199960f5fff82de35f57
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SISchedule.td
M llvm/test/tools/llvm-mca/AMDGPU/gfx12-pseudo-scalar-trans.s
Log Message:
-----------
[AMDGPU] Update gfx12 sched model (#192448)
Commit: c095488da4586f4d98c13f9793088b444e686a4a
https://github.com/llvm/llvm-project/commit/c095488da4586f4d98c13f9793088b444e686a4a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/same-node-reused.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll
M llvm/test/Transforms/SLPVectorizer/X86/shll1-add-sub-combined.ll
Log Message:
-----------
[SLP]Initial compatibility support for shl v, 1 and add v, v
Allows to make shl v, 1 to be compatible with add operations by
modeling it as add v,v
Fixes #40801
Reviewers: bababuck, hiraditya, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/181168
Commit: b96818f2e0118fcbf908b0a168ca1d23190ac295
https://github.com/llvm/llvm-project/commit/b96818f2e0118fcbf908b0a168ca1d23190ac295
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M lldb/test/API/tools/lldb-server/TestGdbRemoteHostInfo.py
Log Message:
-----------
[lldb][test] Remove print in TestGdbRemoteHostInfo.py (#192468)
Leftover debugging code, not part of the test's assertions.
Commit: 2f268ec5b04462bebb94bfe07633cdbd3881b2c7
https://github.com/llvm/llvm-project/commit/2f268ec5b04462bebb94bfe07633cdbd3881b2c7
Author: Peng Sun <peng.sun at arm.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-pro-fp-valid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Add row_gather_block_scaled op (#192272)
Add `tosa.row_gather_block_scaled` to the MLIR TOSA dialect, aligned
with the current TOSA 1.1 draft spec and the implementation in
`tosa-tools`.
This includes:
- op definition
- verifier and shape inference support
- validation / profile compliance wiring
- availability and extension handling
- lit tests for parsing, verification, shape inference, and version /
extension gating
The op supports both spec-defined forms:
- non-block-scaled: 1 input value tensor, `BLOCK_SIZE_1`, 1 output
- block-scaled: data + scale tensor list, non-`BLOCK_SIZE_1`, 2 outputs
Op-specific level checks for ROW_GATHER_BLOCK_SCALED have been deferred
while the TOSA 1.1 draft is still evolving.
Signed-off-by: Peng Sun <peng.sun at arm.com>
Commit: f472ebed217c51af47cc6eb3ec697d8555b00c50
https://github.com/llvm/llvm-project/commit/f472ebed217c51af47cc6eb3ec697d8555b00c50
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
A llvm/test/CodeGen/SPIRV/smulextended-builtin.ll
A llvm/test/CodeGen/SPIRV/umulextended-builtin.ll
Log Message:
-----------
[SPIR-V] Add OpSMulExtended and OpUMulExtended builtin support (#187474)
Support OpSMulExtended and OpUMulExtended builtins in a new MulExtended
builtin group and handle both calling conventions: direct struct return
and sret pointer.
Commit: ad554651add849014743f68c0decef3e66b3cdbd
https://github.com/llvm/llvm-project/commit/ad554651add849014743f68c0decef3e66b3cdbd
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/predicated-reverse-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
Reapply "[VPlan] Extract reverse mask from reverse accesses" (#189930)
Following https://github.com/llvm/llvm-project/pull/146525, separate the
reverse mask from reverse access recipes.
At the same time, remove the unused member variable Reverse from
VPWidenMemoryRecipe.
This will help to reduce redundant reverse mask computations by
VPlan-based common subexpression elimination.
The previous revert was due to an over-aggressive assertion that
incorrectly flagged a reverse load followed by a scatter store as
illegal. This version relaxes the assertion to check the mask only.
Re-land #155579
Base on pre-commit #189928
Commit: e4ebeac8d1ee124016e6fa9fba8e5a05c3737543
https://github.com/llvm/llvm-project/commit/e4ebeac8d1ee124016e6fa9fba8e5a05c3737543
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
Log Message:
-----------
[MCP][NFC] Cleanup and prepare to preserve frame-setup/destroy (#186240)
This mixes renames, removing redundant code, avoiding
`else`-after-`return`, etc. with factoring out the `isNeverRedundant`
concept.
Change-Id: I43a62a9415019cdd63c68fd3b915ebb7505d317a
Commit: 232251164fe1fe7336450bfd61810aa9b812c6bb
https://github.com/llvm/llvm-project/commit/232251164fe1fe7336450bfd61810aa9b812c6bb
Author: Leonardo Román Carrillo <leonardoroman at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
Log Message:
-----------
[AArch64] Correct comparator in regalloc hints to satisfy strict weak ordering (#192383)
The current comparator will have a strict-weak ordering violation for
the following scenario:
a = GoodReg ((!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) == true) && !Op1Reg
b = BadReg ((!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) == false) && !Op1Reg
c = Op1Reg
Then we would have:
a vs c
A != B && B == Op1Reg && (!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) = true && true && true ->
a < c
a vs b
A != B && B == Op1Reg && (!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) =true && false && false ->
a ~ b
b vs c
A != B && B == Op1Reg && (!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) = true && true && false ->
b ~ c
That will result in a strict-weak ordering violation (a < c && a ~ c),
with the new implementation we define that a < b && a < c.
Commit: 0a984edbcd2e2f094f45e5ec009d444a947aea18
https://github.com/llvm/llvm-project/commit/0a984edbcd2e2f094f45e5ec009d444a947aea18
Author: Chandana Mudda <quic_csinderi at quicinc.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatterns.td
A llvm/test/CodeGen/Hexagon/sext-mul-v2i16.ll
Log Message:
-----------
[Hexagon] Optimize sext + mul pattern to use vmpyh instruction (#190316)
This patch adds TableGen patterns to recognize and optimize the pattern:
(v2i32 (mul (sext v2i16), (sext v2i16)))
And transforms it to use the M2_vmpy2s_s0 instruction which generates
the efficient vmpyh (vector multiply halfwords) instruction.
The transform is guarded by `nsw` because `M2_vmpy2s_s0` performs a
saturating signed multiply (`vmpyh(...):sat`), so the replacement is
only semantics-preserving when signed overflow is undefined in the IR.
Currently, this pattern expands to:
r3:2 = vsxthw(r0) // Sign extend
r1:0 = vsxthw(r1) // Sign extend
r1 = mpyi(r3,r1) // Scalar multiply
r0 = mpyi(r2,r0) // Scalar multiply
With this patch, it generates:
r1:0 = vmpyh(r0,r1):sat // Single vector multiply
Co-authored-by: Santanu Das <quic_santdas at quicinc.com>
Commit: fce45b3e961cac33e6b26725405a14a5b1f5d733
https://github.com/llvm/llvm-project/commit/fce45b3e961cac33e6b26725405a14a5b1f5d733
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/lib/Frontend/CompilerInstance.cpp
A clang/test/Interpreter/ftime-report.cpp
M clang/tools/driver/cc1_main.cpp
M clang/unittests/Support/TimeProfilerTest.cpp
Log Message:
-----------
[Frontend] Consolidate frontend timer setup in CompilerInstance::ExecuteAction. NFC (#192266)
Move the frontend timer creation (-ftime-report) and TimeTraceScope
("ExecuteCompiler") from cc1_main into CompilerInstance::ExecuteAction
via a new private PrepareForExecution() method. This ensures all tools
that use ExecuteAction (cc1, clang-repl, libclang, etc.) get consistent
timing infrastructure without duplicating setup code.
Commit: 5467e556a3756304e5c9a8aa93e309da755eff28
https://github.com/llvm/llvm-project/commit/5467e556a3756304e5c9a8aa93e309da755eff28
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
M llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
M llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
A llvm/test/CodeGen/RISCV/calls-cf-branch.ll
M llvm/test/CodeGen/RISCV/calls.ll
A llvm/test/CodeGen/RISCV/cf-branch-isel.ll
M llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
M llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
M llvm/test/CodeGen/RISCV/lpad.ll
M llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir
M llvm/test/CodeGen/RISCV/nest-register.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
M llvm/test/CodeGen/RISCV/pr97304.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
Log Message:
-----------
[RISCV] Generate landing pad based on cf-protection-branch flag only (#179960)
Previously, the backend generated lpad instructions when the Zicfilp
extension was enabled. This patch changes the behavior to generate lpad
instructions only when the cf-protection-branch module flag is set
(typically from -fcf-protection=branch).
This aligns with the Clang frontend's intent, which has a comment saying
"Always generate Zicfilp lpad insns, Non-zicfilp CPUs would read them as
NOP".
The Zicfilp extension is no longer required for lpad generation - only
the module flag matters. Tests that previously used
-mattr=+experimental-zicfilp to trigger lpad generation now use the
cf-protection-branch module flag.
Additionally, the selection of NonX7 variants for indirect
branches/calls is now based on the cf-protection-branch module flag
instead of the Zicfilp extension. This ensures consistent behavior: when
cf-protection-branch is enabled, X7 is reserved for landing pad labels
and cannot be used for indirect branch/call target addresses.
Commit: f4e43c43ea7da30c580d5edb1e2f5e12623d1184
https://github.com/llvm/llvm-project/commit/f4e43c43ea7da30c580d5edb1e2f5e12623d1184
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/pr109581-unused-blend.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
Log Message:
-----------
[VPlan] Remove ComputeAnyOfResult, use ComputeReductionResult. (#190039)
ComputeAnyOfResult is simply a boolean OR reduction. Remove the
dedicated opcode and model directly via ComputeReductionResult.
This simplifies and unifies the code, as well as enabling trivial
constant folding.
PR: https://github.com/llvm/llvm-project/pull/190039
Commit: 9d923ec59516041609038fabeaae8202026adec6
https://github.com/llvm/llvm-project/commit/9d923ec59516041609038fabeaae8202026adec6
Author: Lei Huang <lei at ca.ibm.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/lib/Headers/altivec.h
M clang/lib/Sema/SemaPPC.cpp
A clang/test/CodeGen/PowerPC/builtins-ppc-deeply-compressed-weights.c
A clang/test/Sema/builtins-ppc-deeply-compressed-weights-error.c
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
A llvm/test/CodeGen/PowerPC/deeply-compressed-weights.ll
Log Message:
-----------
[PowerPC] Implement Deeply Compressed Weights Builtins (#184666)
Add support for the following deeply compressed weights builtins for ISA
Future.
- vec_uncompresshn(vector unsigned char, vector unsigned char)
- vec_uncompressln(vector unsigned char, vector unsigned char)
- vec_uncompresshb(vector unsigned char, vector unsigned char)
- vec_uncompresslb(vector unsigned char, vector unsigned char)
- vec_uncompresshh(vector unsigned char, vector unsigned char)
- vec_uncompresslh(vector unsigned char, vector unsigned char)
- vec_unpack_hsn_to_byte(vector unsigned char)
- vec_unpack_lsn_to_byte(vector unsigned char)
- vec_unpack_int4_to_bf16(vector unsigned char, uint2)
- vec_unpack_int8_to_bf16(vector unsigned char, uint1)
- vec_unpack_int4_to_fp32(vector unsigned char, uint3)
- vec_unpack_int8_to_fp32(vector unsigned char, uint2)
Assisted by AI.
Commit: 82467159043f3007e41e81fb921c81beaa234a14
https://github.com/llvm/llvm-project/commit/82467159043f3007e41e81fb921c81beaa234a14
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for add_min/max intrinsics (#192356)
Commit: 04cae92976cc89c9747cb057c9d88a4c1bc25db6
https://github.com/llvm/llvm-project/commit/04cae92976cc89c9747cb057c9d88a4c1bc25db6
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/Basic/Targets/SPIR.cpp
M clang/test/Preprocessor/predefined-macros.c
Log Message:
-----------
[SPIRV] Conditionally define `__AMDGCN_UNSAFE_FP_ATOMICS__` for AMDGCN flavoured SPIR-V (#192136)
Client apps rely on the `__AMDGCN_UNSAFE_FP_ATOMICS__` macro to guide
optimised execution pathways. We were not defining it for AMDGCN
flavoured SPIR-V, which led to pessimisation.
Commit: 547197d200cbaf7b24b9f14c756310e3b60c8850
https://github.com/llvm/llvm-project/commit/547197d200cbaf7b24b9f14c756310e3b60c8850
Author: woruyu <1214539920 at qq.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
Log Message:
-----------
[NFC][AMDGPU] Rename AMDGPUUnifyDivergentExitNodes to AMDGPUUnifyDivergentExitNodesLegacy (#192399)
### Summary
This NFC patch renames the legacy pass wrapper class for
`AMDGPUUnifyDivergentExitNodes` to
`AMDGPUUnifyDivergentExitNodesLegacy`. This makes the old pass manager
wrapper explicit and avoids ambiguity. No behavior change is intended.
Commit: 1b433e936fbeef8fc1c649ad223719df897d311f
https://github.com/llvm/llvm-project/commit/1b433e936fbeef8fc1c649ad223719df897d311f
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
A mlir/test/Dialect/OpenACC/compute-region-canonicalize.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
Log Message:
-----------
[mlir][acc] Add canonicalization patterns for compute_region (#192376)
This PR improves the APIs for navigating through acc.compute_region
block arguments and also adds canonicalization patterns for those
arguments to remove unused ones and merge duplicates.
Commit: a81621a7b14ffd33d1b3fd7b6134a083f51ea1d3
https://github.com/llvm/llvm-project/commit/a81621a7b14ffd33d1b3fd7b6134a083f51ea1d3
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for perm_pk16_b{4,6,8}_u4 (#192368)
Commit: 1317890e1b81b952dbbd6d4011fc9113d4722488
https://github.com/llvm/llvm-project/commit/1317890e1b81b952dbbd6d4011fc9113d4722488
Author: Jiahao Guo <eoonguo at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Lower NEON vrsra_n intrinsics (#191129)
### Summary
Implement CIR lowering for all intrinsics in
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right-and-accumulate
This PR references the implementation from the ClangIR incubator:
https://github.com/llvm/clangir/blob/main/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp#L4854
AArch64 does not provide a dedicated "rounding shift right by immediate"
instruction. Instead, the `SRSHL` / `URSHL` intrinsics take a signed
per-lane shift amount where a negative value means right shift, so an
immediate right shift by `n` is encoded as a signed vector splat of
`-n`. The three infrastructure changes below exist to support this
encoding at the call site:
- extends `emitNeonShiftVector` with a `neg` parameter so the
right-shift-as-negative-left-shift encoding is handled inside the
helper;
- adds `getSignChangedVectorType` (also mirroring the incubator) used to
construct the signed shift-amount vector type for the unsigned path;
- replaces the `errorNYI` in `emitNeonCallToOp`'s `shift == j` branch
with an actual call to `emitNeonShiftVector`.
Tests: new CHECK lines in clang/test/CodeGen/AArch64/neon/intrinsics.c
under section 2.1.3.2.4.
Part of #185382.
Commit: 7aa2b040236bfa8b60ebec69af60f5a334ee160e
https://github.com/llvm/llvm-project/commit/7aa2b040236bfa8b60ebec69af60f5a334ee160e
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll
M llvm/test/CodeGen/X86/stack-clash-small-alloc-medium-align.ll
Log Message:
-----------
[X86] Use unsigned comparison for stack clash probing loop (#192355)
The stack clash probing loop generated in `EmitLoweredProbedAlloca` used
a signed comparison (`X86::COND_GE`) to determine when the allocation
target had been reached.
In 32-bit mode, memory addresses above `0x80000000` have the sign bit
set. If the stack pointer lands in this region, treating the addresses
as signed integers causes the comparison logic to fail. This leads to
incorrect loop execution, resulting in an infinite loop and a crash
(segmentation fault) when setting up custom stacks for pthreads mapped
above `0x80000000` in a 32b process.
This patch changes the condition code to `X86::COND_AE` (Above or
Equal), which generates an unsigned comparison. This ensures that
addresses are treated correctly as unsigned quantities on all targets.
On 64-bit systems, this change has no practical effect on valid
user-space addresses because they do not use the sign bit (being
restricted to the lower half of the address space). However, using
unsigned comparison is the correct behavior for pointer arithmetic and
bounds checks.
Reported-by: Wonsik Kim <wonsik at google.com>
Commit: dcfe195ef1cb7590207cc7a89765482cfb164767
https://github.com/llvm/llvm-project/commit/dcfe195ef1cb7590207cc7a89765482cfb164767
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
Log Message:
-----------
[MCP][NFC] Opinionated refactoring (#186239)
There are a few minor inconsistencies across the pass which I found mildly distracting:
* The use of `Def`/`Dest`/`Dst` to refer to the same thing
* Inconsistent declaration order of `Dst`/`Src` vs `Src`/`Dst`
* Lots of `->getReg()->asMCReg()`, and uses of `Register` when the pass
is always running after RA anyway.
* Some places explicitly `assert(isCopyInstr)` while others just deref
the `optional`.
Standardize on `Dst`/`Src` to match the metaphor and ordering of
`DestSourcePair`.
Assume `std::optional::operator*` will assert in any reasonable
implementation, even though this may technically be undefined behavior.
When asserts are disabled it would be anyway.
The refactor uses structured bindings for a couple reasons:
* Naturally enforces consistent order of `Dst`-then-`Src`
* Requires the use of `auto`, which ensures the declaration is not
implicitly converting from `MCRegister` back to `Register`.
In both cases the explicitness of the name `getDstSrcMCRegs` hopefully
makes the meaning at the callsite clear (`Dst, Src = DstSrc`, and
explicitly mentioning `MCReg`).
Change-Id: Ic58f555e03535d726cdad38dbe3f9c6df1b86460
Commit: ffde06f4c11927c60936802fb439a5195ac0742e
https://github.com/llvm/llvm-project/commit/ffde06f4c11927c60936802fb439a5195ac0742e
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Transforms/Utils.h
A llvm/include/llvm/Transforms/Utils/StripConvergenceIntrinsics.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
R llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
A llvm/lib/Transforms/Utils/StripConvergenceIntrinsics.cpp
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
A llvm/test/CodeGen/DirectX/strip-convergence-intrinsics.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
A llvm/test/Transforms/StripConvergenceIntrinsics/basic.ll
Log Message:
-----------
[NFC][SPIRV] Move `SPIRVStripConvergenceIntrinsics` to Utils (#188537)
The `SPIRVStripConvergenceIntrinsic` pass was written as a spirv pass as
it is the currently the only target that emits convergence tokens during
codegen. There is nothing target specific to the pass, and, we plan to
emit convergence tokens when targeting DirectX (and all targets in
general), so move the pass to a common place.
The previous pass used temporary `Undef`s, as part of moving the pass we
can simply reverse the traverse order to remove the use of `Undef` as it
is deprecated.
Enables the pass for targeting DirectX and is a pre-req for:
https://github.com/llvm/llvm-project/pull/188792.
Assisted by: Github Copilot
Commit: 9e45a7a4fa86dae50569308df5c5d5ab9a441bdc
https://github.com/llvm/llvm-project/commit/9e45a7a4fa86dae50569308df5c5d5ab9a441bdc
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
Log Message:
-----------
[clang][OpenMP] Fix __llvm_omp_indirect_call_lookup signature for targets with non-default program AS (#192470)
The argument and return value for `__llvm_omp_indirect_call_lookup` are
function pointers so make sure they are in the correct address space.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 7328b74dceed9764b9195e42f1e6f08f04727157
https://github.com/llvm/llvm-project/commit/7328b74dceed9764b9195e42f1e6f08f04727157
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Lower/PowerPC/ppc-vec-convert.f90
M flang/test/Lower/PowerPC/ppc-vec-load-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-load.f90
M flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-store.f90
Log Message:
-----------
[flang] Handle ub.poison in lowering (#192454)
This patch is to add the UB dialect registration and UBToLLVM conversion
interface in lowering.
Commit: e90f463db5c2d28ae0d65e2ceccfaa03d4ea7c53
https://github.com/llvm/llvm-project/commit/e90f463db5c2d28ae0d65e2ceccfaa03d4ea7c53
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/bottom-to-top-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/operand-reorder-with-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll
Log Message:
-----------
[SLP] Normalize copyable operand order via majority voting
When building operands for entries with copyable elements, non-copyable
lanes of commutative ops may have inconsistent operand order (e.g. some
lanes have load,add while others have add,load). This prevents
VLOperands::reorder() from grouping consecutive loads on one side,
degrading downstream vectorization.
Add majority-voting normalization during buildOperands: track the
(ValueID, ValueID) pair frequency across non-copyable lanes and swap
any lane whose operand types are the exact inverse of the most common
pattern. This makes operand order consistent, enabling better load
grouping.
This is part 1 of #189181.
Reviewers: RKSimon, hiraditya
Pull Request: https://github.com/llvm/llvm-project/pull/191631
Commit: b9ae01500d8b8c6c5b6f35d09bacd11325e67c8f
https://github.com/llvm/llvm-project/commit/b9ae01500d8b8c6c5b6f35d09bacd11325e67c8f
Author: macurtis-amd <macurtis at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
A llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp
A llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
Log Message:
-----------
AMDGPU: Add NextUseAnalysis Pass (#178873)
Based on
- https://github.com/llvm/llvm-project/pull/156079 and
- https://github.com/llvm/llvm-project/pull/171520
See those PRs for background.
Provides a compatibility mode option
`--amdgpu-next-use-analysis-compatibility-mode` that produces results
that match either PR #156079 (`compute`) or PR #171520 (`graphics`).
Co-authored-by: alex-t <atimofee at amd.com>
Co-authored-by: Konstantina Mitropoulou <KonstantinaMitropoulou at amd.com>
---------
Co-authored-by: Konstantina Mitropoulou <KonstantinaMitropoulou at amd.com>
Commit: fd8b58ce1c3e71b53a677394da1fcf3994e80585
https://github.com/llvm/llvm-project/commit/fd8b58ce1c3e71b53a677394da1fcf3994e80585
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M mlir/test/Dialect/SPIRV/IR/group-ops.mlir
M mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
Log Message:
-----------
[mlir][spirv][nfc] Move GroupNonUniformBallotBitCount tests to `non-uniform-ops.mlir` (#192115)
Tests were incorrectly placed in `group-ops.mlir` since the op is
defined in `SPIRVNonUniformOps.td`.
Commit: 796302a402eb439592042bcbc9469ae2b4582b07
https://github.com/llvm/llvm-project/commit/796302a402eb439592042bcbc9469ae2b4582b07
Author: adams381 <adams at nvidia.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
R clang/test/CIR/global-var-simple.cpp
Log Message:
-----------
[CIR][NFC] Remove redundant global-var-simple.cpp test (#192354)
This early smoke test is fully covered by
`clang/test/CIR/CodeGen/globals.cpp` and is no longer needed.
Per @andykaylor's feedback on #191521.
Made with [Cursor](https://cursor.com)
Commit: 3091b9811305b98cf45aaf6ed7b5c2c910b24a6f
https://github.com/llvm/llvm-project/commit/3091b9811305b98cf45aaf6ed7b5c2c910b24a6f
Author: adams381 <adams at nvidia.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/test/CIR/CodeGen/global-array-dtor.cpp
M clang/test/CIR/CodeGen/global-init.cpp
Log Message:
-----------
[CIR] Add noundef to __cxx_global_array_dtor parameter (#191529)
The synthetic __cxx_global_array_dtor helper created by
LoweringPrepare was missing noundef on its ptr parameter,
causing a mismatch with classic codegen.
Commit: a109303236e2aef39c9abe0f3264af5fa482fe1a
https://github.com/llvm/llvm-project/commit/a109303236e2aef39c9abe0f3264af5fa482fe1a
Author: Matthew Nagy <matthew.nagy at sony.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M compiler-rt/lib/tysan/tysan.cpp
Log Message:
-----------
[TySan] Set and cache tool name. (#192410)
Partial reland of [sanitizer common
support](https://github.com/llvm/llvm-project/pull/183310)
Commit: 53368bf9788b58b80405394e2e7554c3e6b6fc65
https://github.com/llvm/llvm-project/commit/53368bf9788b58b80405394e2e7554c3e6b6fc65
Author: Vatsal Khosla <95174891+VatsalKhosla at users.noreply.github.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAsm.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/IR/inline-asm.cir
Log Message:
-----------
[CIR] Fix InlineAsmOp roundtrip parse crash on cir.asm (#186588)
Fix InlineAsmOp parser/printer roundtrip for cir.asm and avoid null
operand_attrs entries that crash alias printing during
--verify-roundtrip.
- Parse attr-dict before optional result arrow to match print order.
- Use non-null sentinel attributes for non-maybe_memory operands and
check UnitAttr explicitly.
- Keep lowering semantics by treating only UnitAttr as maybe_memory
marker.
- Update inline-asm CIR IR test to run with --verify-roundtrip and add
an attr+result coverage case.
Fix https://github.com/llvm/llvm-project/issues/161441
Commit: db9132e636dd8d375a0c6c0191749c2a221350e1
https://github.com/llvm/llvm-project/commit/db9132e636dd8d375a0c6c0191749c2a221350e1
Author: Aman LaChapelle <aman.lachapelle at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M lldb/include/lldb/Interpreter/OptionGroupVariable.h
M lldb/source/Interpreter/OptionGroupVariable.cpp
Log Message:
-----------
[lldb] Reformat OptionGroupVariable.{h,cpp}, NFC. (#192395)
This patch runs clang-format on OptionGroupVariable.{h,cpp}.
Commit: 6ee930cb48a8716c884bb7d4991c0c1e05b3e766
https://github.com/llvm/llvm-project/commit/6ee930cb48a8716c884bb7d4991c0c1e05b3e766
Author: Nico Weber <thakis at chromium.org>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[clang] Expose -fdiagnostics-show-inlining-chain to clang-cl (#192241)
Commit: 0feabfa1d83356964d4464202db25ac1b4c94f6a
https://github.com/llvm/llvm-project/commit/0feabfa1d83356964d4464202db25ac1b4c94f6a
Author: Nico Weber <thakis at chromium.org>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port b9ae01500d8b (#192496)
[gn build] Port b9ae01500d8b
Commit: 9ff4276edf5cd4d614a7a46a4d8bde04d54df68a
https://github.com/llvm/llvm-project/commit/9ff4276edf5cd4d614a7a46a4d8bde04d54df68a
Author: Nico Weber <thakis at chromium.org>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
Log Message:
-----------
[gn build] Port ffde06f4c119 (#192498)
Commit: 6c2bf97994c949da8d3252e7fcb18a6d7c70b098
https://github.com/llvm/llvm-project/commit/6c2bf97994c949da8d3252e7fcb18a6d7c70b098
Author: Yoonseo Choi <yoonchoi at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.cluster.id.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dispatch.id.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.queue.ptr.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.workgroup.id.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.workitem.id.ll
Log Message:
-----------
[AMDGPU] InstCombine: fold invalid calls to amdgcn intrinsics into poison values (#191904)
Replace a call to amdgpu intrinsic into a poison value when the call is
invalid because of "amdgpu-no-<xyz>" attribute in the caller function.
Upon
https://github.com/llvm/llvm-project/pull/186925#pullrequestreview-3983414064
Assisted by claude-4.6-sonnet-medium through CURSOR.
Commit: 8b15fc14f5314ceb8576629f3190d4c740590396
https://github.com/llvm/llvm-project/commit/8b15fc14f5314ceb8576629f3190d4c740590396
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
Log Message:
-----------
[CIR] Fix FlattenCFG pattern rewriter contract violations (#192359)
Fix patterns in CIRFlattenCFGPass that modify IR but return failure(),
violating the MLIR greedy pattern rewriter contract. The contract
requires that if a pattern modifies IR, it must return success().
- CIRCleanupScopeOpFlattening: always return success() since IR is
modified (blocks split, regions inlined) before error paths
- Ternary op flattening: return success() instead of falling through
after emitError, since splitBlock/createBlock already modified IR
- Use rewriter.moveOpBefore() instead of direct defOp->moveBefore() to
properly notify the rewriter of IR mutations
Found by MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.
Test: flatten-cleanup-scope-nyi.cir (a silly one since it's testing an
error, but point still valid)
Commit: 81c4ceb90239098e60d706f0a68f68d4dacec7af
https://github.com/llvm/llvm-project/commit/81c4ceb90239098e60d706f0a68f68d4dacec7af
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
M mlir/test/Dialect/SPIRV/IR/logical-ops.mlir
M mlir/test/Target/SPIRV/logical-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Add spirv.Any and spirv.All ops (#192286)
Commit: 2427dc449759b48ed88920e0768af82a2dce27ca
https://github.com/llvm/llvm-project/commit/2427dc449759b48ed88920e0768af82a2dce27ca
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC] Remove unused PtrN parameter from analyzeConstantStrideCandidate() (#191567)
Commit: 0bbfddf03770a870c7f9aa9b888205be38e71446
https://github.com/llvm/llvm-project/commit/0bbfddf03770a870c7f9aa9b888205be38e71446
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-call-between-operands.ll
Log Message:
-----------
[SLP][NFC]Add a test with the incorrect spill cost calculation between operands
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/192509
Commit: 6b054fdbcd8bd7b3fb850794e0feaa6d6525c793
https://github.com/llvm/llvm-project/commit/6b054fdbcd8bd7b3fb850794e0feaa6d6525c793
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/field-init-eh.cpp
Log Message:
-----------
[CIR] Implement EH handling for field initializers (#192360)
This implements the handling to call the dtor for any previously
initialized fields of destructed type if an exception is thrown later in
the initialization of the containing class.
The basic infrastructure to handle this was already in place. We just
needed a function to push an EH-only destroy cleanup on the EH stack and
a call to that function.
Commit: 5aea02a163d94092b54833001e06a26c7e57fb01
https://github.com/llvm/llvm-project/commit/5aea02a163d94092b54833001e06a26c7e57fb01
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M offload/test/api/omp_indirect_call_table_manual.c
M offload/test/api/omp_indirect_func_array.c
M offload/test/api/omp_indirect_func_struct.c
M openmp/device/src/Misc.cpp
Log Message:
-----------
[OpenMP][Device] Fix __llvm_omp_indirect_call_lookup function pointer types (#192502)
`__llvm_omp_indirect_call_lookup` takes in and returns a function
pointer, so make sure the types are correct, which includes the correct
address space.
The FE was recently changed to generate the correct code
[here](https://github.com/llvm/llvm-project/pull/192470).
With this change, three function pointer tests start passing.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 23dcca9d91110ebdb4e95d01818f7e16071fb21f
https://github.com/llvm/llvm-project/commit/23dcca9d91110ebdb4e95d01818f7e16071fb21f
Author: Yoonseo Choi <Yoonseo.Choi at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
R llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.cluster.id.ll
R llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dispatch.id.ll
R llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
R llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
R llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.queue.ptr.ll
R llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.workgroup.id.ll
R llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.workitem.id.ll
Log Message:
-----------
Revert "[AMDGPU] InstCombine: fold invalid calls to amdgcn intrinsics into poison values" (#192514)
Reverts llvm/llvm-project#191904
Commit: 2086b8701df4c876646e2049275efbfad5674585
https://github.com/llvm/llvm-project/commit/2086b8701df4c876646e2049275efbfad5674585
Author: Carlos Galvez <carlos.galvez at zenseact.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/CommentSema.h
M clang/lib/AST/CommentSema.cpp
M clang/test/Sema/warn-documentation.cpp
Log Message:
-----------
[clang] Fix false positive with -Wdocumentation and explicit instanti… (#178223)
…ations
Solves a use case listed in #64087.
Commit: 38f3d0be121c04b42f0988a25c22ea67543919f8
https://github.com/llvm/llvm-project/commit/38f3d0be121c04b42f0988a25c22ea67543919f8
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/test/CodeGen/X86/machine-copy-prop.mir
Log Message:
-----------
[MCP] Never eliminate frame-setup/destroy instructions (#186237)
Presumably targets only insert frame instructions which are significant,
and there may be effects MCP doesn't model. Similar to reserved
registers this
is probably overly conservative, but as this causes no codegen change in
any lit test I think it is benign.
The motivation is just to clean up #183149 for AMDGPU, as we can spill
to physical registers, and currently have to spill the EXEC mask purely
to enable debug-info.
Change-Id: I9ea4a09b34464c43322edd2900361bf635efd9f7
Commit: ca3bc44c3090481615bd8fc4b3e64358b845c8bf
https://github.com/llvm/llvm-project/commit/ca3bc44c3090481615bd8fc4b3e64358b845c8bf
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/Intrinsics/transfer.f90
Log Message:
-----------
[flang] Inline scalar-to-scalar TRANSFER for same-size trivial types (#191589)
Inline the TRANSFER intrinsic for scalar-to-scalar cases where the
result is a trivial type (integer, real, etc.) and source and result
have the same storage size. Instead of calling _FortranATransfer, the
lowering now emits a fir.convert on the source address followed by a
fir.load, effectively performing a reinterpret cast.
Commit: 9931b7830f5a411cfdb1bc1f819601a8217a4a21
https://github.com/llvm/llvm-project/commit/9931b7830f5a411cfdb1bc1f819601a8217a4a21
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
A clang/test/Driver/amdgpu-multilib.yaml
A clang/test/Driver/nvptx-multilib.yaml
Log Message:
-----------
[Clang] Add multilib support for GPU targets (#192285)
Summary:
This PR uses the new, generic multilib support added in
https://github.com/llvm/llvm-project/pull/188584
to also function for GPU targets. This will allow toolchains to easy
provide variants of these GPU libraries (for debug or asan). In
practice, this will look something like this:
```console
-DRUNTIMES_amdgcn-amd-amdhsa+debug_CMAKE_BUILD_TYPE=Debug \
-DRUNTIMES_amdgcn-amd-amdhsa+debug_LIBOMPTARGET_ENABLE_DEBUG=ON \
-DRUNTIMES_amdgcn-amd-amdhsa+debug_LLVM_ENABLE_RUNTIMES=openmp \
-DLLVM_RUNTIME_MULTILIBS=debug \
-DLLVM_RUNTIME_MULTILIB_debug_TARGETS="amdgcn-amd-amdhsa" \
```
This will then install it into the tree like this:
```
<install>/lib/amdgcn-amd-amdhsa/debug/libompdevice.a
```
The user can then activate this like the following (assuming they have a
multilib.yaml in the library directory):
```
clang input.c -fopenmp --offload-arch=gfx942 -fmultilib-flag=debug
```
Commit: bec1019d14d9c9b79b0b5e29ae4b1114942fb67b
https://github.com/llvm/llvm-project/commit/bec1019d14d9c9b79b0b5e29ae4b1114942fb67b
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
Revert "[Fuchsia] Stack analysis flags for runtimes" (#192515)
Reverts llvm/llvm-project#175677
We noticed using -fexperimental-call-graph-section with Control Flow
Integrity causes link failures in certain situations. Reverting this
change that sets the call graph section flag until we investigate the
root cause of the problem and handle it in the compiler well.
Commit: e60e400d778ca1734edab609f9db991b1acaab5b
https://github.com/llvm/llvm-project/commit/e60e400d778ca1734edab609f9db991b1acaab5b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
Log Message:
-----------
[RISCV][P-ext] Use pli.b when only the lower 2 bytes are used. (#192400)
If the lower 2 bytes are the same and are the only bytes used we
can use pli.b instead of lui+addi.
Commit: f162be248636046a20e71209e139347e084b637a
https://github.com/llvm/llvm-project/commit/f162be248636046a20e71209e139347e084b637a
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/stack-probing-dynamic.ll
M llvm/test/CodeGen/RISCV/stack-clash-prologue.ll
Log Message:
-----------
[RISCV] Use unsigned comparison for stack clash probing loop (#192485)
The stack clash probing loop generated in `emitDynamicProbedAlloc` used
a signed comparison (`RISCV::COND_BLT`) to determine when the allocation
target had been reached.
In 32-bit mode, memory addresses above `0x80000000` have the sign bit
set. If the stack pointer lands in this region, treating the addresses
as signed integers causes the comparison logic to fail.
This patch changes the condition code to `RISCV::COND_BLTU` (Branch if
Less Than Unsigned), which generates an unsigned comparison. This
ensures that addresses are treated correctly as unsigned quantities on
all targets.
On 64-bit systems, this change has no practical effect on valid
user-space addresses because they do not use the sign bit (being
restricted to the lower half of the address space). However, using
unsigned comparison is the correct behavior for pointer arithmetic and
bounds checks.
Link: #192355
Commit: e210f2216df103c57b749e17b125cf002359d307
https://github.com/llvm/llvm-project/commit/e210f2216df103c57b749e17b125cf002359d307
Author: Praneeth Sarode <praneethsarode at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/docs/MemorySanitizer.rst
M clang/docs/ThreadSanitizer.rst
Log Message:
-----------
[Clang][Docs] Fix malformed code-block directive in MSan and TSan docs (#190461)
The `code-block` directives in MemorySanitizer.rst and
ThreadSanitizer.rst were missing a leading period (`. code-block`
instead of `.. code-block`). This syntax error caused Sphinx to fail to
recognize the directives, resulting in the the subsequent C code being
rendered as plain text rather than a syntax-highlighted block.
The currently broken rendering on the official docs can be seen
[here](https://clang.llvm.org/docs/MemorySanitizer.html#interaction-of-inlining-with-disabling-sanitizer-instrumentation)
and
[here](https://clang.llvm.org/docs/ThreadSanitizer.html#interaction-of-inlining-with-disabling-sanitizer-instrumentation).
Fixed the typos to ensure proper HTML rendering.
Commit: 981da65faca247557efa37f8bc55b6dc36e9b8bd
https://github.com/llvm/llvm-project/commit/981da65faca247557efa37f8bc55b6dc36e9b8bd
Author: Lei Huang <lei at ca.ibm.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/test/ClangScanDeps/prune-scanning-modules.m
M llvm/test/tools/llvm-objcopy/ELF/strip-preserve-atime.test
Log Message:
-----------
Invalidate tests using "touch -a" on Darwin (#192521)
Tests uses 'touch -a' which is known to fail on macOS.
Commit: 19ad75ef7f14e012fa8dac8312d0af4cdd806ee1
https://github.com/llvm/llvm-project/commit/19ad75ef7f14e012fa8dac8312d0af4cdd806ee1
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitDeclare.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-declare.mlir
M mlir/unittests/Dialect/OpenACC/CMakeLists.txt
A mlir/unittests/Dialect/OpenACC/OpenACCCGOpsTest.cpp
Log Message:
-----------
[mlir][acc] Ensure implicit declare hoisting works for compute_region (#192501)
Any hoisting across `acc.compute_region` needs to be wired through block
arguments as the region is `IsolatedFromAbove`. Thus update
`ACCImplicitDeclare` to do so by using new API
`wireHoistedValueThroughIns` which handles the value wiring after
hoisting.
Commit: 7039515e0cb5ed48ede8634a7fc58df6f6f93d2e
https://github.com/llvm/llvm-project/commit/7039515e0cb5ed48ede8634a7fc58df6f6f93d2e
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/test/OpenMP/metadirective_device_arch_codegen.cpp
M offload/test/offloading/ompx_coords.c
Log Message:
-----------
[OpenMP] Fix convention of SPIRV outline functions (#192450)
When creating an outline function for device code we're not setting the
right calling convention when the target is SPIRV. This results in the
calls to the function to be removed by the InstCombine pass as it thinks
is not callable.
Commit: c195385e0b6512736b2edf9d6f576115ccb645cc
https://github.com/llvm/llvm-project/commit/c195385e0b6512736b2edf9d6f576115ccb645cc
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
Log Message:
-----------
[bazel] Update rules_python (#192518)
This pulls in this fix
https://github.com/bazel-contrib/rules_python/pull/3420
Commit: 6ff9ca2f1918e60c7e0dad327541dcbb7ea25ff2
https://github.com/llvm/llvm-project/commit/6ff9ca2f1918e60c7e0dad327541dcbb7ea25ff2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[RISCV] Don't check isApplicableToPLI for simm12 constants. (#192522)
It won't match except when the constant is -1, which we should use li
for. This avoids an unecessary call for hasAllWUsers in that case.
Commit: a8f1f387255a56c3080682ad62015670cca697df
https://github.com/llvm/llvm-project/commit/a8f1f387255a56c3080682ad62015670cca697df
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M mlir/unittests/Dialect/OpenACC/OpenACCCGOpsTest.cpp
Log Message:
-----------
[mlir][acc] Fix OpenACCCGOpsTest ValueRange construction (#192529)
Ensure that `Value`s are used in the `ValueRange` construction to avoid
failure:
`error: call of overloaded ValueRange(mlir::acc::ParWidthOp&) is
ambiguous`
Commit: 2c56a63b4969be7c5938db6e7e085288224b8621
https://github.com/llvm/llvm-project/commit/2c56a63b4969be7c5938db6e7e085288224b8621
Author: David CARLIER <devnexen at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M bolt/lib/Passes/Instrumentation.cpp
Log Message:
-----------
[BOLT][Passes] switch remaining Instrumentation containers to ADT. (#192525)
Follow-up to #192289. Swap the remaining `std::unordered_set`/
`std::unordered_map` containers in `Instrumentation.cpp` for `DenseSet`/
`DenseMap`: the `BBToSkip` param and `Visited` local in
`hasAArch64ExclusiveMemop`, and `BBToSkip`, `BBToID`, `VisitedSet` in
`instrumentFunction`. Drop the now-unused `<unordered_set>` include.
The swap removes per-element heap allocations on the hot path, stops
inserting empty buckets on probes where a miss is possible, and replaces
hashed-bucket traversal over node-based storage with lookups over inline
`DenseMap` storage. `BBToID` reads keep `operator[]` since the map is
pre-populated for every basic block of the function, so no
default-construct path is ever taken. NFC.
Measured on `llvm-bolt -instrument` against a relocations-linked
clang-23: -1.3% instrumentation-pass wall time, peak RSS unchanged
(dominated by instrumentation output size).
Commit: 046fd10b5e2592f10b4b0f90279d53ad24e71af6
https://github.com/llvm/llvm-project/commit/046fd10b5e2592f10b4b0f90279d53ad24e71af6
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/test/DebugInfo/Generic/bounds-checking-debuginfo.c
M clang/test/DebugInfo/Generic/cfi-check-fail-debuginfo.c
M clang/test/DebugInfo/Generic/cfi-icall-generalize-debuginfo.c
M clang/test/DebugInfo/Generic/cfi-icall-normalize2-debuginfo.c
M clang/test/DebugInfo/Generic/ubsan-function-debuginfo.c
M clang/test/DebugInfo/Generic/unsigned-promotion-debuginfo.c
Log Message:
-----------
UBSan: Use ubsan_interface.h for synthetic debug info (#171929)
Before the patch, even with the same synthetic function name, they
counted as different functions, because the file name was different.
This makes it easier to analyze data in performance profiles.
`pprof -lines -top <somefile> | grep __ubsan_check_pointer_overflow`
Before:
```
60368049443 6.26% 6.26% 60383492016 6.26% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/TSVC/tsc.inc (inline)
43746146224 4.53% 10.79% 43763767409 4.54% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/SciMark2-C/SparseCompRow.c (inline)
11670846196 1.21% 26.03% 11673592781 1.21% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/ASC_Sequoia/AMGmk/csr_matvec.c (inline)
7948730683 0.82% 29.07% 7949496154 0.82% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/ASC_Sequoia/IRSmk/rmatmult3.c (inline)
7442972883 0.77% 30.62% 7447647795 0.77% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/mafft/Galign11.c (inline)
7181873035 0.74% 32.88% 7182846509 0.74% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/ASC_Sequoia/AMGmk/relax.c (inline)
7086681860 0.73% 33.61% 7086681860 0.73% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/SciMark2-C/FFT.c (inline)
6634628163 0.69% 35.03% 6644529197 0.69% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/Olden/em3d/make_graph.c (inline)
5778832834 0.6% 37.55% 5778832835 0.6% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/SciMark2-C/LU.c (inline)
5707159214 0.59% 38.14% 5707159214 0.59% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/SciMark2-C/Random.c (inline)
5265117200 0.55% 40.99% 5266753453 0.55% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/Trimaran/netbench-url/search.c (inline)
```
After:
```
143372006423 14.76% 14.76% 143426398982 14.76% __ubsan_check_pointer_overflow sanitizer/ubsan_interface.h (inline)
16972753760 1.75% 31.03% 16979483803 1.75% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/TSVC/tsc.inc (inline)
14296973786 1.47% 32.50% 14297951231 1.47% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/SciMark2-C/SparseCompRow.c (inline)
7857020738 0.81% 36.93% 7857966628 0.81% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/ASC_Sequoia/AMGmk/csr_matvec.c (inline)
6956467376 0.72% 41.47% 6958074907 0.72% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/Olden/em3d/make_graph.c (inline)
5502783427 0.57% 45.07% 5502783429 0.57% __ubsan_check_pointer_overflow test-suite/MultiSource/Benchmarks/SciMark2-C/LU.c (inline)
```
Commit: b2e0403b11de1ce60fbf2aadec0cc4efb44cd4c4
https://github.com/llvm/llvm-project/commit/b2e0403b11de1ce60fbf2aadec0cc4efb44cd4c4
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-types/x86_64/ucontext_t.h
M libc/src/CMakeLists.txt
A libc/src/ucontext/CMakeLists.txt
A libc/src/ucontext/getcontext.h
A libc/src/ucontext/setcontext.h
A libc/src/ucontext/x86_64/CMakeLists.txt
A libc/src/ucontext/x86_64/getcontext.cpp
A libc/src/ucontext/x86_64/setcontext.cpp
M libc/test/integration/src/CMakeLists.txt
A libc/test/integration/src/ucontext/CMakeLists.txt
A libc/test/integration/src/ucontext/ucontext_test.cpp
M libc/test/src/CMakeLists.txt
A libc/test/src/ucontext/CMakeLists.txt
A libc/test/src/ucontext/ucontext_test.cpp
Log Message:
-----------
[libc] Implement getcontext and setcontext for x86_64 (#192343)
Implemented getcontext and setcontext for x86_64 architecture in LLVM
libc. These functions use inline assembly with naked attributes to
capture and restore the exact register state.
Added:
* src/ucontext/getcontext.h and setcontext.h
* src/ucontext/x86_64/getcontext.cpp and setcontext.cpp
* Hermetic integration test for register preservation.
* Unit tests for basic functionality and signal mask preservation.
Updated entrypoints for x86_64 Linux.
Commit: c88d891f2b693dbc45a2d0e155974a9541905755
https://github.com/llvm/llvm-project/commit/c88d891f2b693dbc45a2d0e155974a9541905755
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Upstream pairwise-minimum NEON builtins (#191759)
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for pairwise-minimum intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#pairwise-minimum)
Port tests from `clang/test/CodeGen/AArch64/neon_intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`
Commit: b104dab739ad6ad60ef0725d563d9a4ae640c5bf
https://github.com/llvm/llvm-project/commit/b104dab739ad6ad60ef0725d563d9a4ae640c5bf
Author: gulfemsavrun <gulfem at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/lib/Lex/PPExpressions.cpp
M clang/test/Lexer/cxx-features.cpp
R clang/test/Preprocessor/p2843r3.cpp
M clang/www/cxx_status.html
Log Message:
-----------
Revert "[Clang] Implement P2843R3 - Preprocessing is never undefined" (#192532)
Reverts llvm/llvm-project#192073
Reason for revert: This change caused build failures on Windows when
compiling libcxx.
Commit: 59c6862804e2638ac8a4b57de505dfb963871d6d
https://github.com/llvm/llvm-project/commit/59c6862804e2638ac8a4b57de505dfb963871d6d
Author: Bill Wendling <morbo at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/test/CodeGen/asm.c
Log Message:
-----------
[Clang] Refactor the tests to be more uniform (#191944)
- Add missing "CHECK:" lines to testcases.
- Improve checking to be a bit more readable.
- Move "rm" testcases to the bottom in anticipation of
future refactoring.
Commit: dd81356eacdd78d6781772e4ca5a25482a347b68
https://github.com/llvm/llvm-project/commit/dd81356eacdd78d6781772e4ca5a25482a347b68
Author: Sherman Pay <shermanpay1991 at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/PrettyPrinter.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/test/AST/ast-printer-lambda.cpp
A clang/test/AST/constexpr-lambda-diagnostic.cpp
Log Message:
-----------
Suppress printing lambda body for constexpr diagnostics (#185800)
closes #125914
Introduce `SupressLambdaBody` `PrintingPolicy` that is used only for
constexpr diagnostics. This ensures `--print-ast` still works the same.
I also considered other approaches such as modifying the
`PrintingPolicy` in the current `AstContext`, but that might cause
unexpected changes.
Add two tests:
1. To ast-printer-lambda to ensure `--print-ast` works the same.
2. Ensure lambda body is not printed for constexpr diagnostics.
Commit: db4dfdce0b6cb4eaf56804c91ffa91bea1cf16ac
https://github.com/llvm/llvm-project/commit/db4dfdce0b6cb4eaf56804c91ffa91bea1cf16ac
Author: Sharjeel Khan <sharjeelkhan at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M libcxx/utils/ci/BOT_OWNERS.txt
Log Message:
-----------
[libc++] Update Android CI owners (#192511)
Add nickdesaulniers as an owner for Android libc++ CI
Commit: 9d51c891b7191914952fa783ffd05acb96dafe2d
https://github.com/llvm/llvm-project/commit/9d51c891b7191914952fa783ffd05acb96dafe2d
Author: 4ast <alexei.starovoitov at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFISelLowering.h
A llvm/test/CodeGen/BPF/cleanup-reject-typed-catch.ll
A llvm/test/CodeGen/BPF/cleanup-section.ll
Log Message:
-----------
[BPF] Add exception handling support with .bpf_cleanup section (#192164)
Add support for invoke/landingpad/resume instructions in the BPF backend
so that Rust programs compiled with panic=unwind can run cleanup code
(Drop implementations) when bpf_throw fires.
Changes:
1. BPFISelLowering: Define exception pointer and selector registers
(both R0) so SelectionDAG can lower landingpad instructions.
2. BPFAsmPrinter::emitFunctionBodyEnd: Emit a .bpf_cleanup section with
a flat table of (begin, end, landing_pad) triples using
R_BPF_64_NODYLD32 relocations.
The .bpf_cleanup section layout (12 bytes per entry):
u32 begin // start of the invoke region
u32 end // end of the invoke region
u32 landing_pad // address of the cleanup block
The invoke region [begin, end) includes argument setup instructions
before the call. The runtime checks begin <= PC < end to find the
matching landing pad.
Landing pad blocks survive optimization because invoke maintains CFG
edges to them throughout codegen, same as every other backend. The
standard .gcc_except_table and .eh_frame are also emitted by the
existing DwarfCFIException handler; libbpf will ignore them.
In runtime:
- bpf_throw() is called (from panic handler)
- Kernel walks the BPF call stack with arch_bpf_stack_walk()
- For each frame, look up current PC in .bpf_cleanup table
- If match found: redirect execution to the cleanup function . cleanup
function runs Drop impls (bpf_free, rcu_read_unlock, etc.) . calls
_Unwind_Resume() which is patched to just 'ret' by the verifier .
bpf_throw() pops frame goes to next
- If no match: go to next frame
Signed-off-by: Alexei Starovoitov <ast at kernel.org>
Co-authored-by: Alexei Starovoitov <ast at kernel.org>
Commit: 9de94147b5ed83f9078f0f0f3a67b25cc2abb093
https://github.com/llvm/llvm-project/commit/9de94147b5ed83f9078f0f0f3a67b25cc2abb093
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Use find instead of lookup for using ArrayRef instead of SmallVector
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/192540
Commit: b3cbad3214fcec02487b5ab4f6652c37ecb3467a
https://github.com/llvm/llvm-project/commit/b3cbad3214fcec02487b5ab4f6652c37ecb3467a
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.h
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/Transform/IR/TransformTypes.td
M mlir/include/mlir/Dialect/Transform/Interfaces/CMakeLists.txt
M mlir/include/mlir/Dialect/Transform/Interfaces/TransformInterfaces.h
M mlir/include/mlir/Dialect/Transform/Interfaces/TransformInterfaces.td
M mlir/lib/Dialect/Transform/IR/TransformAttrs.cpp
M mlir/lib/Dialect/Transform/IR/TransformDialect.cpp
M mlir/lib/Dialect/Transform/IR/TransformTypes.cpp
M mlir/lib/Dialect/Transform/Interfaces/TransformInterfaces.cpp
A mlir/test/Dialect/Transform/normal-forms.mlir
M mlir/test/Dialect/Transform/ops-invalid.mlir
M mlir/test/lib/Dialect/Transform/CMakeLists.txt
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.h
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.td
Log Message:
-----------
[mlir] transform dialect; add pre/post-condition type (#191813)
Add a transform dialect type denoting additional invariants on payload
IR usable for pre/post-conditions of a transformation. The invariants
are defined as a list of attributes in the type parameter, where the
attribute implements the interface for invariant-checking. This allows
clients to factor out, explicify and deduplicate precondition
verification logic.
This required adding support for Transform dialect extensions injecting
attributes into the dialects similarly to how they already do this for
operations and types.
Co-authored-by: Tim Gymnich <tim at gymni.ch>
Co-authored-by: Martin Lücke <martin.luecke at amd.com>
Assisted-by: Claude Opus 4.3 / Cursor
Co-authored-by: Tim Gymnich <tim at gymni.ch>
Co-authored-by: Martin Lücke <martin.luecke at amd.com>
Commit: 04a502d04d6030ed417b244faf51a35904384924
https://github.com/llvm/llvm-project/commit/04a502d04d6030ed417b244faf51a35904384924
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
Log Message:
-----------
[flang][cuda] Avoid false positive on multi device symbol with components (#192513)
Semantic was wrongly flagging derived-type components as two device
resident object. Update how we collect symbols and count the number of
device resident object.
Commit: fa44ca8e5ef6f57c03ba55a4c7b944c9a3ee633e
https://github.com/llvm/llvm-project/commit/fa44ca8e5ef6f57c03ba55a4c7b944c9a3ee633e
Author: Congzhe Cao <congzhe.cao at huawei.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopBoundSplit.cpp
Log Message:
-----------
[LoopBoundSplit] Fix edge connections during transformation (#192106)
Fixed #190672.
The issue is caused by invalid intermediate IR when `getSCEV()` is
called during transformation: the exiting block of `pre-loop` did not
re-connect to preheader of the `post-loop`, causing `LI.verify()`
unable to correctly recompute another LoopInfo for verification.
To fix, reconnect the edge earlier before calling `getSCEV()`.
Also moved the DT updates to more appropriate places right after IR
control flow has changed. and added a few LI and DT verifications to
improve robustness of the pass.
Commit: 22acd64a1b15cd7ccf60393340a59a6e0569edb9
https://github.com/llvm/llvm-project/commit/22acd64a1b15cd7ccf60393340a59a6e0569edb9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
Log Message:
-----------
[SLP][NFC]Add a test with the spill cost overestimation for blocks, dominated by root
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/192556
Commit: 030be3f7045633622158859bb2ffcd99cb5e9f4a
https://github.com/llvm/llvm-project/commit/030be3f7045633622158859bb2ffcd99cb5e9f4a
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/test/SemaCXX/void-lambda-return-init.cpp
Log Message:
-----------
[Clang] [Tests] Add more tests for 87104ee (#192555)
Requested by Shafik:
https://github.com/llvm/llvm-project/pull/188904#discussion_r3090555425
Commit: 9f74e0f7df988977a643f847b83ce77b93780442
https://github.com/llvm/llvm-project/commit/9f74e0f7df988977a643f847b83ce77b93780442
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes b3cbad3 (#192554)
This fixes b3cbad3214fcec02487b5ab4f6652c37ecb3467a.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: bbf325be7e2d2078cba058e3fb4763d756b15d41
https://github.com/llvm/llvm-project/commit/bbf325be7e2d2078cba058e3fb4763d756b15d41
Author: Aman LaChapelle <aman.lachapelle at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M lldb/include/lldb/API/SBVariablesOptions.h
M lldb/include/lldb/Interpreter/OptionGroupVariable.h
A lldb/include/lldb/Utility/ValueType.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBVariablesOptions.cpp
M lldb/source/Interpreter/OptionGroupVariable.cpp
Log Message:
-----------
[lldb] Scaffolding for synthetic variable support. (#181500)
This patch handles most of the scaffolding for synthetic variable support that isn't directly tied to functional changes. This patch will be used by one following patch that actually modifies the lldb_private::StackFrame API to allow us to fetch synthetic variables.
There were a couple important/interesting decisions made in this patch that should be noted:
- Any value type may be synthetic, which is why it's a mask applied over the top of another value type.
- When printing frame variables with `fr v`, default to showing synthetic variables.
This new value type mask makes some of the ValueType handling more interesting, but since nothing generates objects with this mask until the next patch, we can land the concept in this patch in some amount of isolation.
Commit: 393207a1408a93fa5831a97a298c5d6dda96617e
https://github.com/llvm/llvm-project/commit/393207a1408a93fa5831a97a298c5d6dda96617e
Author: Brendan Dahl <brendan.dahl at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
Log Message:
-----------
[WebAssembly] Improve FP16 load and store generation. (#191274)
Previously, these LL instructions were expanded to software emulation
calls, causing performance overhead in benchmarks. By making these
operations legal and providing patterns, we can generate efficient code
using the new instructions.
Commit: daf814c4319b4cbf183a55df0030d0706630999e
https://github.com/llvm/llvm-project/commit/daf814c4319b4cbf183a55df0030d0706630999e
Author: Victor Mustya <victor.mustya at intel.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M libclc/opencl/lib/generic/atomic/atomic_fetch_add.cl
M libclc/opencl/lib/generic/atomic/atomic_fetch_sub.cl
Log Message:
-----------
[libclc] Fix atomic_fetch_add/sub overloads for uintptr_t (#192570)
The overloads taking the memory order and/or scope parameters should
have the `_explicit` suffix, according to the OpenCL C specification.
Commit: 2664fd38127d463765d17573bec238f31a92cbaf
https://github.com/llvm/llvm-project/commit/2664fd38127d463765d17573bec238f31a92cbaf
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M offload/test/mapping/map_ordering_tgt_exit_data_always_always.c
M offload/test/mapping/map_ordering_tgt_exit_data_delete_from.c
M offload/test/mapping/map_ordering_tgt_exit_data_delete_from_assumedsize.c
M offload/test/mapping/map_ordering_tgt_exit_data_from_delete_assumedsize.c
Log Message:
-----------
[NFC][OpenMP] Make map ordering tests for no host->tgt transfer more robust (#192571)
They were relying on the host value not being seen on the device, but
the value being matched was small enough for the probability of a
successful match against garbage data relatively high.
Now we just rely on the LIBOMPTARGET_DEBUG logs to ensure there wasn't
any transfer.
Commit: 3b1cc610162b118ba422b5dccde2c3718ed55614
https://github.com/llvm/llvm-project/commit/3b1cc610162b118ba422b5dccde2c3718ed55614
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M flang-rt/lib/cuda/pointer.cpp
M flang/include/flang/Runtime/CUDA/pointer.h
M flang/lib/Optimizer/Transforms/CUDA/CUFAllocationConversion.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] Add missing pointer deallocation entry point (#192566)
We were missing the deallocation entry point for pointer and wiring all
to allocatable deallocate which will trigger Invalid descriptor error.
Commit: 4b6231d410696dad377f4997cc17ac886fcbab57
https://github.com/llvm/llvm-project/commit/4b6231d410696dad377f4997cc17ac886fcbab57
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/Attributes/CUFAttr.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/CUDA/cuda-data-attribute.cuf
M flang/test/Semantics/cuf03.cuf
Log Message:
-----------
[flang][cuda] Accept attributes(value) as a CUDA Fortran extension (#192560)
This is accepted by legacy compiler and is part of some documentation
Commit: c78f80c405a005346f8b2dd3f8605851df294900
https://github.com/llvm/llvm-project/commit/c78f80c405a005346f8b2dd3f8605851df294900
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
A clang/test/CIR/IR/branch.cir
A clang/test/CIR/IR/do-while.cir
A clang/test/CIR/IR/for.cir
A clang/test/CIR/IR/while.cir
Log Message:
-----------
[CIR][NFC] Upstream IR roundtrip tests for branch and loop ops (#189006)
Add `clang/test/CIR/IR` roundtrip tests for `cir.br`, `cir.brcond`,
`cir.for`, `cir.while`, and `cir.do`.
This adds parser/printer coverage for the textual forms of these
control-flow operations.
Partially addresses #156747.
Commit: 03312094b8243bb54b5bc8d89dea923fc09ce885
https://github.com/llvm/llvm-project/commit/03312094b8243bb54b5bc8d89dea923fc09ce885
Author: Jim Lin <jim at andestech.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/RISCV/rvv/buildvec-sext.ll
Log Message:
-----------
[DAGCombiner] Extend convertBuildVecZextToZext to sign extends (#192372)
Generalize the existing fold that collapses a BUILD_VECTOR of ZERO_EXTEND
(or ANY_EXTEND) of EXTRACT_VECTOR_ELTs into a single vector extend so that
it also handles SIGN_EXTEND. Mixed sign and zero extends remain unsupported
because their high-bit semantics differ, so the combine bails out in that
case.
---------
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: 114f6627d927f560550136c2b43747dc77f3ee9d
https://github.com/llvm/llvm-project/commit/114f6627d927f560550136c2b43747dc77f3ee9d
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[llvm-readobj][ELF] Remove redundant error in reportWarning (#192458)
Commit: 27769d7b5976c40f43f535ef19bcc6f8603fc3f6
https://github.com/llvm/llvm-project/commit/27769d7b5976c40f43f535ef19bcc6f8603fc3f6
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/test/CodeGen/RISCV/machine-outliner-call-x5-liveout.mir
A llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir
A llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave-rv32e.mir
A llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave.mir
Log Message:
-----------
[RISCV] Support MachineOutlinerRegSave for RISCV (#191351)
This patch adds support for the RegSave strategy in the RISC-V
MachineOutliner pass. It uses t1–t6 to preserve the t0 value across the
outlined function call when t0 is unavailable. This enables more
potential outlining candidates.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 91fcdab8983a5f014528949183e9992940404782
https://github.com/llvm/llvm-project/commit/91fcdab8983a5f014528949183e9992940404782
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
Log Message:
-----------
[mlir][memref] Remove unit-stride restriction in SubViewOp folding (#192437)
This PR replaces manual offset/size resolution with `affine::mergeOffsetsSizesAndStrides`, simplifying the code and extending subview-of-subview folding to support non-unit strides.
Commit: 7094eb52d8cbaa9faeb635bfb6f6c06e6cd52b64
https://github.com/llvm/llvm-project/commit/7094eb52d8cbaa9faeb635bfb6f6c06e6cd52b64
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/CndVar.h
M libc/src/__support/threads/darwin/futex_utils.h
A libc/src/__support/threads/futex_utils.h
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
M libc/src/semaphore/CMakeLists.txt
M libc/src/semaphore/posix_semaphore.h
M libc/test/integration/src/__support/threads/CMakeLists.txt
A libc/test/integration/src/__support/threads/futex_requeue_test.cpp
M libc/test/src/__support/threads/CMakeLists.txt
A libc/test/src/__support/threads/futex_utils_test.cpp
Log Message:
-----------
[libc][threads] adjust futex library and expose requeue API (#192478)
Make futex a common abstraction layer across platforms.
(linux/wasm/macOS/windows/fuchsia all have the support, which we can
align their support later on).
This patch also expose a requeue API that returns ENOSYS on unsupported
platforms. The requeue operation will be needed to reimplement a strict
FIFO style condvar similar to musl.
Additional cleanup is done to change raw syscall return value to
`ErrorOr<int>`.
Assisted-by: Codex with gpt-5.4 medium fast
Commit: 685ee06ff810e818a55b4b0d10f93dd75303a84c
https://github.com/llvm/llvm-project/commit/685ee06ff810e818a55b4b0d10f93dd75303a84c
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 7094eb5 (#192584)
This fixes 7094eb52d8cbaa9faeb635bfb6f6c06e6cd52b64.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 7cabc53157287698fa33a310466e9ae4d49c73f9
https://github.com/llvm/llvm-project/commit/7cabc53157287698fa33a310466e9ae4d49c73f9
Author: hev <wangrui at loongson.cn>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
Log Message:
-----------
[LoongArch][NFC] Add tests for add/sub with negative splat immediates (#191965)
Commit: 2bac8d6ebe9003f6ad575a5e2b4465fd1449dea7
https://github.com/llvm/llvm-project/commit/2bac8d6ebe9003f6ad575a5e2b4465fd1449dea7
Author: hev <wangrui at loongson.cn>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/nor.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/nor.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
Log Message:
-----------
[LoongArch][NFC] Add tests for bitwise with byte splat immediates (#192216)
Commit: 8398672dca5dcc53b56620b70659e38ea30f2f98
https://github.com/llvm/llvm-project/commit/8398672dca5dcc53b56620b70659e38ea30f2f98
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
A llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
Log Message:
-----------
[LoongArch][NFC] Pre-commit tests for vector fptrunc from vxf64 to vxf32 (#164058)
Commit: ab94dbc0569368290c7b400e9b47981193b73e69
https://github.com/llvm/llvm-project/commit/ab94dbc0569368290c7b400e9b47981193b73e69
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Mark pointers destroyed in destructors (#192460)
We didn't use to do this at all, so calling the destructor explicitly
twice in a row wasn't an error. Calling it and accessing the object
afterwards wasn't an error either.
Commit: fca80b4ff3fc00d95a1ae6412e838c04443f55ef
https://github.com/llvm/llvm-project/commit/fca80b4ff3fc00d95a1ae6412e838c04443f55ef
Author: Chaitanya <Krishna.Sankisa at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-alloca-placement.ll
Log Message:
-----------
[AMDGPU][ASAN] Move allocas to entry block in amdgpu-sw-lower-lds pass (#190772)
The `amdgpu-sw-lower-lds` pass inserts a workitem-0 check, malloc, and
barrier before the original entry block, creating a new entry block.
This pushes the original allocas into a non-entry block, causing LLVM to
treat them as dynamic allocas.
AMDGPU backend generates incorrect flat addresses for dynamic alloca
addrspacecasts at -O0, causing memory faults when ASan is enabled with
LDS.
This PR hoists constant-size allocas to the new entry block so they
remain static.
Commit: ede75e5d5dfb9b9481c1ae2c332085d24d9744df
https://github.com/llvm/llvm-project/commit/ede75e5d5dfb9b9481c1ae2c332085d24d9744df
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Don't diagnose const assignments... (#192593)
... when we're in CPCE mode.
Commit: 19463aab0271572a3e9e2f45ec21014553241c05
https://github.com/llvm/llvm-project/commit/19463aab0271572a3e9e2f45ec21014553241c05
Author: Konrad Kleine <kkleine at redhat.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFCFIPrinter.cpp
Log Message:
-----------
[llvm][DebugInfo] Use formatv in DWARFCFIPrinter (#191982)
This relates to #35980.
Commit: b4e75e158e460f66407bd5be7d13a38ff61d816a
https://github.com/llvm/llvm-project/commit/b4e75e158e460f66407bd5be7d13a38ff61d816a
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libc/src/ucontext/getcontext.h
M libc/src/ucontext/setcontext.h
M libc/src/ucontext/x86_64/getcontext.cpp
M libc/src/ucontext/x86_64/setcontext.cpp
Log Message:
-----------
[libc][nfc] Fix ucontext buildbot failure with noexcept (#192343) (#192601)
Added noexcept to getcontext and setcontext declarations and definitions
to resolve missing attribute warning on aliases.
This fixes failures on builders using GCC like
libc-x86_64-debian-gcc-fullbuild-dbg.
Commit: 10536d48b700e82101d9c8f4a0a87c999b6f9251
https://github.com/llvm/llvm-project/commit/10536d48b700e82101d9c8f4a0a87c999b6f9251
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M llvm/include/llvm/Transforms/IPO/LowerTypeTests.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/test/Other/fatlto.ll
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/ThinLTO/X86/lower_type_test_phi.ll
M llvm/test/Transforms/LowerTypeTests/drop_type_test.ll
M llvm/test/Transforms/LowerTypeTests/drop_type_test_phi.ll
M llvm/test/Transforms/LowerTypeTests/drop_type_test_select.ll
Log Message:
-----------
[CFI] Extract DropTypeTestsPass from LowerTypeTestsPass (#192578)
This patch introduces `DropTypeTestsPass` as a dedicated pass
to handle the dropping of type tests. Previously, this was handled
by `LowerTypeTestsPass` with a specific parameter.
By splitting this into its own pass, we simplify the pass pipeline
construction and make the intent clearer in `PassRegistry.def` and
various pipeline builders.
It's almost NFC, if not opt command line changes.
Commit: 8671b797be7a9b6424ed33b7df1f4869412fe4db
https://github.com/llvm/llvm-project/commit/8671b797be7a9b6424ed33b7df1f4869412fe4db
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
Log Message:
-----------
[LV][RISCV] Fix incorrect pointer operand in interleaved access tests. nfc (#192464)
In some load cases, the index 1 member used the same pointer as the
index 0 member. This patch corrected the pointer use.
Commit: bcc606cd0e04735af71988498c59362e81a25d8b
https://github.com/llvm/llvm-project/commit/bcc606cd0e04735af71988498c59362e81a25d8b
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
Log Message:
-----------
[NFC][mlir][shard] Unify MoveLastSplitAxisPattern/MoveLastSplitAxisPattern (#192295)
Made MoveLastSplitAxisPattern more general to also cover MoveLastSplitAxisPattern.
Less code, same functionality.
Assisted by claude.
Commit: 2fdd23f7a32c15e07a2217abbcfec35092dffc59
https://github.com/llvm/llvm-project/commit/2fdd23f7a32c15e07a2217abbcfec35092dffc59
Author: Brad Smith <brad at comstyle.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc
Log Message:
-----------
[compiler-rt][AArch64][NFC] Sort HWCAP entries (#192370)
Commit: a02d955b334c3b65a08159bb869018e8a7f0f81c
https://github.com/llvm/llvm-project/commit/a02d955b334c3b65a08159bb869018e8a7f0f81c
Author: Matthias Springer <me at m-sp.org>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/vector-contract-to-matrix-intrinsics-transforms.mlir
M mlir/test/Dialect/XeGPU/xegpu-vector-linearize.mlir
Log Message:
-----------
[mlir][vector] Fold poison operands into vector.shuffle mask (#190932)
Fold poison operands into the `vector.shuffle` mask. This commit also
splits up the `vector::ShuffleOp::fold` implementation into multiple
helper functions.
Assisted-by: claude-4.6-opus-high
Commit: 7f5588f35abefa7f961fd471eb5282ab384dc46a
https://github.com/llvm/llvm-project/commit/7f5588f35abefa7f961fd471eb5282ab384dc46a
Author: Dmitrii Makarenko <dmitrii.makarenko at intel.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.td
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[MLIR] make One-Shot and SCF bufferization TensorLikeType-aware (#189073)
Fix bufferization inconsistencies between builtin tensor types and
custom TensorLikeType implementations across One-Shot analysis/module
paths and SCF bufferization interfaces.
The main issue was a mix of TensorType/RankedTensorType checks in places
that need TensorLikeType-aware handling. This could leave
function-boundary equivalence/aliasing incomplete for custom tensor-like
types, leading to spurious SCF loop equivalence verification failures.
This change:
- switches relevant One-Shot analysis/module checks from TensorType/
RankedTensorType to TensorLikeType;
- updates generic/default aliasing utilities to treat TensorLikeType
consistently;
- updates SCF BufferizableOpInterface implementations
(for/while/if/yield related paths) to use TensorLikeType/BufferLikeType
where appropriate;
- updates test custom ops to provide required aliasing/getBufferType
hooks for custom tensor-like types;
- refreshes and renames custom_types SCF tests to explicitly check
memref replacement after bufferization.
Potential follow-ups / known risk areas:
- SCF.Forall shared_outs still has RankedTensorType assumptions in
signatures/ paths and should be audited for full TensorLikeType
coverage.
- SCF.For and SCF.While resolveConflicts call
allocateTensorForShapedValue, which currently assumes ranked
tensor/memref copy paths; this may still be a limitation for some
tensor-like/unranked scenarios.
---------
Signed-off-by: Dmitrii Makarenko <dmitrii.makarenko at intel.com>
Commit: 1963feb560d6f95c0402c48d3c75bcb06057827c
https://github.com/llvm/llvm-project/commit/1963feb560d6f95c0402c48d3c75bcb06057827c
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[LV] Replace "BinOp" with "ExtendedOp" in partial reduction transforms (NFCI) (#192422)
"BinOp" as not been accurate for a while (as it's sometime just an
extend). After #188043, it can now also be an "abs" in some cases.
This patch renames "BinOp" to "ExtendedOp" (in line with
matchExtendedReductionOperand). It also updates some doc comments and
tweaks matching the "ExtendedOp" in transformToPartialReduction.
Commit: b2317cc584b84b275a60004226b5962e635c4fda
https://github.com/llvm/llvm-project/commit/b2317cc584b84b275a60004226b5962e635c4fda
Author: Matthias Springer <me at m-sp.org>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/ops.mlir
Log Message:
-----------
[mlir][arith] Add rounding mode flags to binary arithmetic operations (#188458)
Add rounding mode flags for `addf`, `subf`, `mulf`, `divf`. This
addresses a TODO in the op description.
The folder now takes into account the specified rounding mode. If no
rounding mode is specified, the folders/canonicalizations default to
`rmNearestTiesToEven`. (This behavior has not changed.) This is
documented in the top-level arith dialect documentation. The default
arith rounding mode applies only to "internal" transformations such as
foldings/canonicalizations. In case of an unspecified explicit rounding
mode, the runtime behavior is up to the target backend.
Also add a lowering to LLVM intrinsics such as
`llvm.intr.experimental.constrained.fadd`.
Assisted-by: claude-4.6-opus-high
Commit: 6b0d268fe544b25fd1f82aad4e246f8a74e260ed
https://github.com/llvm/llvm-project/commit/6b0d268fe544b25fd1f82aad4e246f8a74e260ed
Author: Jean-Didier PAILLEUX <jean-didier.pailleux at sipearl.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/include/flang/Lower/MultiImageFortran.h
A flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/include/flang/Optimizer/Dialect/MIF/MIFOps.td
M flang/include/flang/Optimizer/Transforms/MIFOpConversion.h
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/Dialect/MIF/CMakeLists.txt
M flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/test/Fir/MIF/change_team.mlir
M flang/test/Fir/MIF/change_team2.mlir
A flang/test/Fir/MIF/coarray-alloc.mlir
M flang/test/Fir/MIF/form_team.mlir
M flang/test/Fir/MIF/get_team.mlir
M flang/test/Fir/MIF/sync_team.mlir
M flang/test/Fir/MIF/team_number.mlir
A flang/test/Lower/MIF/coarray_allocation.f90
A flang/test/Lower/MIF/coarray_allocation2.f90
A flang/test/Lower/MIF/coarray_allocation3.f90
A flang/test/Lower/MIF/coarray_allocation4.f90
A flang/test/Lower/MIF/coarray_allocation5.f90
Log Message:
-----------
[Flang] Adding first lowering for the allocation and deallocation of coarrays (#182110)
This PR add support of coarray allocation and deallocation in Flang and
adds two new operations to MIF:
- `mif::AllocaCoarrayOp` : Allocates a coarray
using `prif_allocate_coarray` PRIF procedure.
- `mif::DeallocaCoarrayOp` : Deallocates a coarray
using `prif_deallocate_coarray` PRIF procedure
This PR does not yet handle allocation for the following cases (which
will be added in future PRs):
- Coarrays with ALLOCATABLE and/or POINTER components (PRIF has
procedures (`prif_(de)allocate`) for this).
- Coarray dummy arguments (PRIF has also procedures for this)
- Finalization of coarrays
- non-ALLOCATABLE SAVE coarrays outside the scoping unit of the main
program (e.g. non-ALLOCATABLE coarrays declared in a module or a
procedure)
Another PR which add support of some basic intrinsics with a coarray as
an argument will follow after this one.
---------
Co-authored-by: Dan Bonachea <dobonachea at lbl.gov>
Commit: 4b2fffab5620fb937e96ef3f2911fc79a3703081
https://github.com/llvm/llvm-project/commit/4b2fffab5620fb937e96ef3f2911fc79a3703081
Author: Zhijie Wang <yesterda9 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/warn-lifetime-safety-suggestions.cpp
Log Message:
-----------
[LifetimeSafety] Handle xvalue operand of LValueToRValue cast (#192312)
Under C++23, P2266 wraps the operand of `return p;` in an xvalue NoOp
cast for by-value parameters. The `CK_LValueToRValue` branch in
FactsGenerator guarded on `!SubExpr->isLValue()`, breaking origin flow
and silencing the suggestion for `int* id(int* p) { return p; }`.
Use `isGLValue()`, matching how origins are built and stripped elsewhere
in the analysis.
Only add a RUN in suggestion test file, since some tests in
`warn-lifetime-safety.cpp` cause a hard error under C++23. For example:
`MyObj& f() { MyObj s; return s; }`. `error: non-const lvalue reference
to type 'MyObj' cannot bind to a temporary of type 'MyObj'`.
Fixes: #176292
Commit: 8364db5096b6baa00904242eb323d66f1ef96e94
https://github.com/llvm/llvm-project/commit/8364db5096b6baa00904242eb323d66f1ef96e94
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
A llvm/test/Transforms/LoopVectorize/AArch64/splice-cost.ll
Log Message:
-----------
[LV] Fix the cost of first order recurrence splice (#192473)
The index had the wrong sign (for splice.right, the sign is negative),
which meant that it calculates the cost of a splice.left operation. For
SVE this makes a difference because a splice.left is lowered using an
unpredicated EXT instruction, whereas a splice.right is lowered using a
predicated SPLICE instruction, which needs a slightly higher cost.
The change in `reduction-recurrence-costs-sve.ll` happens because the
vector loop is now less profitable (higher cost) and therefore requires
a higher trip-count to be profitable (hence the extra umax).
Commit: 3ac04b93d0fe0c4554bf753e57047872f6f55de9
https://github.com/llvm/llvm-project/commit/3ac04b93d0fe0c4554bf753e57047872f6f55de9
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
Log Message:
-----------
[mlir][spirv] Improve type constraints for SPIR-V Tosa CastOp (#192227)
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: a4cccdc393ec8930c03d633ecf932e47d914466b
https://github.com/llvm/llvm-project/commit/a4cccdc393ec8930c03d633ecf932e47d914466b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/runtime-check-dependent-on-stride.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[VPlan] Remove constant branches early. (#183397)
Simplify constant branches early, after introducing the check in the
middle block.
This removes any trivial branches in the input CFG (e.g. over-reduced
test cases) early and also folds branches on true/false created by
addMiddleChecks. This allows to check if there's a scalar tail instead
to check if the tail has been folded, as mentioned in
https://github.com/llvm/llvm-project/pull/182507
This requires to remove recipes in the new unreachable blocks, as
otherwise we would fail during verification, due to uses in unreachable
blocks. Alternatively, we may be able to skip verification for uses in
unreachable blocks.
Depends on https://github.com/llvm/llvm-project/pull/181252.
PR: https://github.com/llvm/llvm-project/pull/183397
Commit: 58b65fa67f1fa25c45a92550f99c2d7f7b2c2bec
https://github.com/llvm/llvm-project/commit/58b65fa67f1fa25c45a92550f99c2d7f7b2c2bec
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M cross-project-tests/lit.cfg.py
Log Message:
-----------
[cross-project-tests][lit] Print LLDB version when configuring tests (#192614)
Useful when debugging issues with the LLDB tests.
Commit: 935413c3cb8eabf3e69181c986c8899affa13d7a
https://github.com/llvm/llvm-project/commit/935413c3cb8eabf3e69181c986c8899affa13d7a
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
Log Message:
-----------
[LoongArch] Add support for vector FP_ROUND from vxf64 to vxf32 (#164059)
In LoongArch, [x]vfcvt.s.d intstructions require two vector registers
for v4f64->v4f32, v8f64->v8f32 conversions.
This patch handles these cases:
- For FP_ROUND v2f64->v2f32(illegal), add a customized v2f32 widening to
convert it into a target-specific LoongArchISD::VFCVT.
- For FP_ROUND v4f64->v4f32, on LSX platforms, v4f64 is illegal and will
be split into two v2f64->v2f32, resulting in two LoongArchISD::VFCVT.
Finally, they are combined into a single node during combining
LoongArchISD::VPACKEV. On LASX platforms, v4f64->v4f32 can directly
lower to vfcvt.s.d in lowerFP_ROUND.
- For FP_ROUND v8f64->v8f32, on LASX platforms, v8f64 is illegal and
will be split into two v4f64->v4f32 and then combine using
ISD::CONCAT_VECTORS, so we combine two ISD::FP_ROUND to
LoongArchISD::VFCVT in this phase.
Commit: b3661c2da61c5f2b6cca30a3ca2e66dfdf26acd3
https://github.com/llvm/llvm-project/commit/b3661c2da61c5f2b6cca30a3ca2e66dfdf26acd3
Author: hev <wangrui at loongson.cn>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
Log Message:
-----------
[LoongArch] Select V{ADD,SUB}I for operations with negative splat immediates (#191966)
Currently, vector add/sub with a negative splat immediate is lowered as
a vector splat followed by a register-register operations, e.g.:
```
vrepli.b $vr1, -1
vadd.b $vr0, $vr0, $vr1
```
This misses the opportunity to use the more efficient V{ADD,SUB}I
instruction with a positive immediate.
This patch introduces `selectVSplatImmNeg` to detect negative splat
immediates whose negated value fits in a 5-bit unsigned immediate. New
patterns `(Pat{Vr,Vr}Nimm5)` are added to match:
```
add v, splat(-imm) --> vsubi v, v, imm
sub v, splat(-imm) --> vaddi v, v, imm
```
This avoids materializing the splat constant and reduces the instruction
count.
The transformation is applied for both LSX and LASX vector types.
Commit: 9a3f0a0e136c6a6e23515ba2769de6e6160488d3
https://github.com/llvm/llvm-project/commit/9a3f0a0e136c6a6e23515ba2769de6e6160488d3
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libc/config/linux/x86_64/headers.txt
Log Message:
-----------
[libc] Add ucontext to public headers for Linux x86_64 (#192621)
Added libc.include.ucontext to TARGET_PUBLIC_HEADERS for Linux x86_64 in
headers.txt.
Commit: 79f31de283b66cc8fa0e372c18d2ca7629829b7d
https://github.com/llvm/llvm-project/commit/79f31de283b66cc8fa0e372c18d2ca7629829b7d
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvextrins.ll
Log Message:
-----------
[LoongArch][NFC] Pre-commit tests for `xvextrins` (#164373)
Commit: 1014eb28e7d4bbfe132b270d885cb9e094e4227a
https://github.com/llvm/llvm-project/commit/1014eb28e7d4bbfe132b270d885cb9e094e4227a
Author: Vincent <janssen.vincentius at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/lib/IR/ODSSupport.cpp
A mlir/test/IR/invalid-properties.mlir
Log Message:
-----------
[mlir] Fix copy paste typo in convertFromAttribute (#192484)
It seems that the bool overload for `convertFromAttribute` has a failure
message incorrectly copied over from the string overload's
implementation.
Commit: a82f3093a05bf00bc959ba439a616efa787c8086
https://github.com/llvm/llvm-project/commit/a82f3093a05bf00bc959ba439a616efa787c8086
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/SemaCXX/cxx2a-consteval.cpp
Log Message:
-----------
[clang][bytecode] Allow more function calls in CPCE mode (#192597)
We previously didn't diagnose the attached test cases correctly.
Commit: cb5445f0797b01fee6410319df09813bfc8021f6
https://github.com/llvm/llvm-project/commit/cb5445f0797b01fee6410319df09813bfc8021f6
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/masked-divrem.ll
M llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll
M llvm/test/CodeGen/RISCV/rvv/masked-srem.ll
M llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll
M llvm/test/CodeGen/RISCV/rvv/masked-urem.ll
Log Message:
-----------
[RISCV] Lower masked_{u,s}{div,rem} and update TTI (#192543)
The loop vectorizer will soon emit llvm.masked.udiv intrinsics and
friends. The vast majority of the time these will be transformed to
vp.udiv on RISC-V thanks to tail folding, but if it doesn't tail fold or
uses a fixed VF then it will reach instruction selection.
This patch lowers the nodes to the masked pseudo for scalable and fixed
vectors, and updates the TTI to account for it.
Commit: b7716135a88f1424fbb400124d3b57a269b38c75
https://github.com/llvm/llvm-project/commit/b7716135a88f1424fbb400124d3b57a269b38c75
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
Log Message:
-----------
[RISCV] Add tests for Zvzip CodeGen (#192591)
Then we can add CodeGen support incrementally.
Commit: 6383afba60e16a9b5b9c62e68fe214f870dd3183
https://github.com/llvm/llvm-project/commit/6383afba60e16a9b5b9c62e68fe214f870dd3183
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Use vputils helper in Blend::usesFirstLaneOnly (NFC) (#189697)
Commit: 2b93b3ca7932d415d7f1c3b029f9e39a0a41272e
https://github.com/llvm/llvm-project/commit/2b93b3ca7932d415d7f1c3b029f9e39a0a41272e
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libsycl/src/CMakeLists.txt
A libsycl/src/detail/device_image_wrapper.cpp
M libsycl/src/detail/device_image_wrapper.hpp
M libsycl/src/detail/device_impl.hpp
A libsycl/src/detail/device_kernel_info.hpp
R libsycl/src/detail/kernel_id.hpp
M libsycl/src/detail/program_manager.cpp
M libsycl/src/detail/program_manager.hpp
Log Message:
-----------
[libsycl] Add liboffload kernel creation (#188794)
This commit extends ProgramAndKernelManager functionality with kernel
creation.
First, it introduces device kernel info object containing kernel data
that is uniform for submissions of the same kernel. This object helps to
avoid kernel data lookup for subsequent calls of the same kernel. This
data is used to create kernel or to find kernel symbol if it has already
been created.
Second, this commit introduces wrappers to manage kernel related data
and its lifetime. Wrappers are implemented for:
1) programs, wrapper is a RAII helper and calls liboffload
create/release methods for program
2) device images, keeps built programs and provide methods to search
existing programs and to add new ones.
---------
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Co-authored-by: Alexey Bader <alexey.bader at intel.com>
Commit: 7f3ed0c45c52b3ed514b181cf716cae3dae3b947
https://github.com/llvm/llvm-project/commit/7f3ed0c45c52b3ed514b181cf716cae3dae3b947
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/sve-sext-zext.ll
Log Message:
-----------
[LLVM][DAGTypeLegalizer] Maintain scalableness when widening inreg extends. (#192482)
Fixes https://github.com/llvm/llvm-project/issues/187557
Commit: d00a49fc3495f260d8b3125b5d9f4e263ac13166
https://github.com/llvm/llvm-project/commit/d00a49fc3495f260d8b3125b5d9f4e263ac13166
Author: Elio <xiongzile at bytedance.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/aarch64/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/windows/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/wctype_t.h
A libc/hdr/wctype_overlay.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/wctype_t.h
M libc/include/wctype.yaml
M libc/src/__support/wctype_utils.h
M libc/src/wctype/CMakeLists.txt
A libc/src/wctype/iswctype.cpp
A libc/src/wctype/iswctype.h
A libc/src/wctype/wctype.cpp
A libc/src/wctype/wctype.h
M libc/test/src/__support/wctype_utils_test.cpp
M libc/test/src/wctype/CMakeLists.txt
A libc/test/src/wctype/iswctype_test.cpp
A libc/test/src/wctype/wctype_test.cpp
Log Message:
-----------
[libc] Add iswctype and wctype (#191178)
Implement the iswctype and wctype functions from <wctype.h>.
- Add wctype_t type definition.
- Implement wctype to map property strings to classification
descriptors.
- Implement iswctype as a dispatcher over existing wide character
classification functions.
- Add corresponding entrypoints and unit tests.
Refs: https://github.com/llvm/llvm-project/issues/191076
---------
Co-authored-by: Zile Xiong <xiongzile99 at gmail.com>
Commit: 8d488fcd6f7c35b3d256feb0554fd885a9f5ce10
https://github.com/llvm/llvm-project/commit/8d488fcd6f7c35b3d256feb0554fd885a9f5ce10
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix nanobind header build (#192627)
The build was broken by 3b3ac5a1169722bff1ae0f5f8f27a48cc08c3d02
changing textual_hdrs to hdrs - the copts/features weren't copied over,
meaning Nanobind was attempted to be built with exceptions disabled.
Co-authored-by: James Molloy <jmolloy at google.com>
Commit: 96266b71214a2fa0925ea11fe2d01a349eb702e0
https://github.com/llvm/llvm-project/commit/96266b71214a2fa0925ea11fe2d01a349eb702e0
Author: Kryptonite <oalazizi75 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/CMakeLists.txt
M clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp
A clang-tools-extra/clang-tidy/readability/RedundantLambdaParameterListCheck.cpp
A clang-tools-extra/clang-tidy/readability/RedundantLambdaParameterListCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-lambda-parameter-list.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-lambda-parameter-list.cpp
Log Message:
-----------
[clang-tidy] Add `readability-redundant-lambda-parameter-list` (#190438)
Adds a new clang-tidy check that removes redundant empty parameter lists
from lambda expressions when the rewrite is valid for the active
language standard.
Fixes #190396
Assisted by Claude (Anthropic), all decisions taken in
this PR involved my active judgment
Commit: 91339fd737c67771fd944f17ea9c3e0908e9d418
https://github.com/llvm/llvm-project/commit/91339fd737c67771fd944f17ea9c3e0908e9d418
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
M llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sme2-asm.ll
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
M llvm/test/CodeGen/AArch64/branch-relax-cross-section.mir
M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/jump-table-compress.mir
M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/ptrauth-isel.ll
M llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
M llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir
M llvm/test/CodeGen/AArch64/wineh9.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/AMDGPU/spill-regpressure-less.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
M llvm/test/CodeGen/AMDGPU/swdev282079.mir
M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
M llvm/test/CodeGen/AMDGPU/vopc-remat.mir
M llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
M llvm/test/CodeGen/ARM/inlineasmbr-if-cvt.mir
M llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
M llvm/test/CodeGen/ARM/machine-outliner-unoutlinable.mir
M llvm/test/CodeGen/LoongArch/inline-asm-clobbers-fcc.mir
M llvm/test/CodeGen/MIR/Generic/inline-asm-bad-mem-constraint.mir
M llvm/test/CodeGen/MIR/Generic/inline-asm-bad-regclass.mir
M llvm/test/CodeGen/MIR/Generic/inline-asm-extra-info.mir
M llvm/test/CodeGen/MIR/Generic/inline-asm-no-constraint.mir
M llvm/test/CodeGen/MIR/Generic/inline-asm-tiedto-bad-operand-number.mir
M llvm/test/CodeGen/MIR/Generic/inline-asm-tiedto-missing-colon.mir
M llvm/test/CodeGen/MIR/Generic/inline-asm-tiedto-missing-dollar.mir
M llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
M llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
M llvm/test/CodeGen/MIR/X86/inline-asm-rm-exhaustion.mir
M llvm/test/CodeGen/MIR/X86/inline-asm.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
M llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll
M llvm/test/CodeGen/PowerPC/aix-print-pc.mir
M llvm/test/CodeGen/PowerPC/alignlongjumptest.mir
M llvm/test/CodeGen/PowerPC/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/PowerPC/ctrloops32.mir
M llvm/test/CodeGen/PowerPC/ctrloops64.mir
M llvm/test/CodeGen/PowerPC/shrink-wrap.mir
M llvm/test/CodeGen/RISCV/branch-rel.mir
M llvm/test/CodeGen/RISCV/rvv/pr99782.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/zdinx-spill.ll
M llvm/test/CodeGen/RISCV/zilsd-spill.ll
M llvm/test/CodeGen/SystemZ/twoaddr-kill.mir
M llvm/test/CodeGen/Thumb/high-reg-clobber.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
M llvm/test/CodeGen/Thumb2/high-reg-spill.mir
M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
M llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
M llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir
M llvm/test/CodeGen/X86/callbr-asm-kill.mir
M llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel-m32.ll
M llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/X86/callbr-asm-outputs-regallocfast.mir
M llvm/test/CodeGen/X86/cfi-xmm.ll
M llvm/test/CodeGen/X86/early-clobber.mir
M llvm/test/CodeGen/X86/flags-copy-lowering.mir
M llvm/test/CodeGen/X86/fp16-reload.mir
M llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
M llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
M llvm/test/CodeGen/X86/peephole-copy.mir
M llvm/test/CodeGen/X86/pr86880.mir
M llvm/test/CodeGen/X86/regallocfast-callbr-asm-spills-after-reload.mir
M llvm/test/CodeGen/X86/scheduler-asm-moves.mir
M llvm/test/CodeGen/X86/stack-folding-bmi2.mir
M llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/switch-jmp-edge-split.mir
M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
Log Message:
-----------
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
Commit: c872a64173f75e0285b44ffb27fd771ea3383f20
https://github.com/llvm/llvm-project/commit/c872a64173f75e0285b44ffb27fd771ea3383f20
Author: StefanPaulet <65234821+StefanPaulet at users.noreply.github.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/CXX/drs/cwg17xx.cpp
M clang/test/SemaCXX/cxx1z-constexpr-lambdas.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
M clang/test/SemaTemplate/GH75426.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add diagnostic for friend declaration of closure type member (#191419)
Clang allows friend declarations of closure type members, which is
disallowed per CWG 1780 (Issue #26540).
Added a new diagnostic when the friend declaration targets a member of a
`CXXRecordDecl` that is a lambda.
---------
Co-authored-by: Corentin Jabot <corentinjabot at gmail.com>
Commit: 873a2597118c473fd0038d6b9270503b79dbce69
https://github.com/llvm/llvm-project/commit/873a2597118c473fd0038d6b9270503b79dbce69
Author: idubinov <idubinov at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
Log Message:
-----------
[SPIRV] Fix trunc nonstandard int types (#191393)
In some cases, the trunc dst type was widened to higher bit size, which
changes behavior of the instruction.
Now, in case of need of widening, the trunc instruction is replaced with
AND with appropriate mask.
Assisted-by: Claude Code.
---------
Co-authored-by: Marcos Maronas <mmaronas at amd.com>
Co-authored-by: Arseniy Obolenskiy <gooddoog at student.su>
Commit: fa7d199f3eb3655b2bbc76ffa5f35cf74d3a53a5
https://github.com/llvm/llvm-project/commit/fa7d199f3eb3655b2bbc76ffa5f35cf74d3a53a5
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Port d00a49fc3495f260d8b3125b5d9f4e263ac13166 (#192637)
Commit: 027ca61e5cc040c4db1d6219a9843b81432d5ea6
https://github.com/llvm/llvm-project/commit/027ca61e5cc040c4db1d6219a9843b81432d5ea6
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Lex/LiteralSupport.cpp
M clang/test/C/C2y/n3353.c
Log Message:
-----------
Suppress octal literal diagnostics from system macros (#192481)
We emit two kinds of diagnostics related to octal literals. One is a
compat/extension warning for use of 0o as the literal prefix and the
other is a deprecation warning for use of 0 as the literal prefix.
Clang now suppresses both of those diagnostics when the octal literal
comes from a macro expansion of a macro defined in a system header.
Those are not uses of the literal the user has any control over,
generally, so the diagnostics are not helpful in that case.
Fixes #192389
Commit: 15e523bb7ebe35a4e3bf114fb26efe324b9112da
https://github.com/llvm/llvm-project/commit/15e523bb7ebe35a4e3bf114fb26efe324b9112da
Author: Rolf Morel <rolfmorel at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[MLIR][CODEOWNERS] Update CODEOWNERS to include MLIR Shard Dialect (#192642)
Add CODEOWNERS for MLIR Shard Dialect.
Commit: e270662c0b2c3a24211f200fe758a84b45b25fcd
https://github.com/llvm/llvm-project/commit/e270662c0b2c3a24211f200fe758a84b45b25fcd
Author: NagaChaitanya Vellanki <pnagato at protonmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinHeaders.def
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaChecking.cpp
A clang/test/CodeGen/Inputs/stdbit.h
A clang/test/CodeGen/builtin-stdc-bit-functions.c
A clang/test/Sema/Inputs/stdbit.h
A clang/test/Sema/builtin-stdc-bit-functions.c
A clang/test/SemaCXX/constexpr-builtin-stdc-bit-functions.cpp
Log Message:
-----------
[clang]Implement the c23 stdc bit builtins (#185978)
This patch implements the following C23 bit builtins
__builtin_stdc_leading_zeros/ones
__builtin_stdc_trailing_zeros/ones
__builtin_stdc_first_leading/trailing_zero/one
__builtin_stdc_count_zeros/ones
__builtin_stdc_has_single_bit
__builtin_stdc_bit_width
__builtin_stdc_bit_floor
__builtin_stdc_bit_ceil
Additional Notes:
* Supports all unsigned integer types including _BitInt and __int128
* lowers to llvm.ctlz / llvm.cttz / llvm.ctpop intrinsics
* constexpr support
Addresses: #79630
Commit: ed19c7775f6eae5be5f238adc67114330b8daf61
https://github.com/llvm/llvm-project/commit/ed19c7775f6eae5be5f238adc67114330b8daf61
Author: Yoni Katzuv <yoni.katzuv at quantum-machines.co>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Async/IR/Async.h
M mlir/include/mlir/Dialect/Func/IR/FuncOps.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.h
M mlir/include/mlir/IR/BuiltinOps.h
Log Message:
-----------
[mlir] Fix definition of type traits struct member for some ops (#192047)
This commit fixes all appearences of `numLowBitsAvailable` to the
correct `NumLowBitsAvailable`. Prior to this change, instantiation of
templates like `llvm::PointerIntPair<mlir::ModuleOp, 3>` would not
compile.
See usage of `NumLowBitsAvailable`:
https://github.com/llvm/llvm-project/blob/224c429e858f8171852990a6f7b2b3590eeaffb7/llvm/include/llvm/ADT/PointerIntPair.h#L169
Commit: e13c07bc57cbe13da73053d57387563fb79660c6
https://github.com/llvm/llvm-project/commit/e13c07bc57cbe13da73053d57387563fb79660c6
Author: Lucas Chollet <lucas.chollet at serenityos.org>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/test/Driver/serenity.cpp
Log Message:
-----------
[clang] Reland NO_LIBCXX test in serenity.cpp (#192638)
The test was first introduced in 934f7950 and then removed in 9c94881f.
The first iteration was depending on the default runtime being
compiler-rt, which isn't true for all bots and thus caused failures:
https://lab.llvm.org/buildbot/#/builders/10/builds/26512
The new version of the test doesn't depend on the compiler runtime.
Commit: 7dddddc3185da662c70cac5ca14f60480b211ef0
https://github.com/llvm/llvm-project/commit/7dddddc3185da662c70cac5ca14f60480b211ef0
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang-rt/lib/runtime/type-info.cpp
M flang-rt/unittests/Runtime/Descriptor.cpp
Log Message:
-----------
[flang-rt] Fix REAL(10)/COMPLEX(10) component sizes in runtime type info (#192049)
This fixes a crash caused by incorrect component sizes in runtime type
info.
For REAL(10) and COMPLEX(10) components,
`Component::GetElementByteSize()` was using the Fortran kind value as
the byte size. On x86-64 that underestimates the actual storage size, so
component size computation can be wrong for extended-precision types.
This patch routes REAL and COMPLEX component sizes through
`Descriptor::BytesFor()`, which matches the runtime’s existing
storage-size handling. I also added a runtime unit test covering the
relevant `Descriptor::BytesFor()` storage-size behavior for REAL and
COMPLEX kinds, including kind 10.
Fixes #192085
---------
Co-authored-by: Sairudra More <moresair at pe31.hpc.amslabs.hpecorp.net>
Commit: 4c7ed8dc849be29e6fb5ee869f4cc6024604b823
https://github.com/llvm/llvm-project/commit/4c7ed8dc849be29e6fb5ee869f4cc6024604b823
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll
M llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll
M llvm/test/CodeGen/SPIRV/ExecutionMode_GLCompute.ll
M llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll
M llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll
M llvm/test/CodeGen/SPIRV/OpVectorInsertDynamic.ll
M llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll
M llvm/test/CodeGen/SPIRV/TruncToBool.ll
M llvm/test/CodeGen/SPIRV/assume.ll
M llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchChar.ll
M llvm/test/CodeGen/SPIRV/branching/analyze-branch-opt.ll
M llvm/test/CodeGen/SPIRV/branching/if-merging.ll
M llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll
M llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll
M llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll
M llvm/test/CodeGen/SPIRV/capability-Shader.ll
M llvm/test/CodeGen/SPIRV/capability-integers.ll
M llvm/test/CodeGen/SPIRV/constant/local-aggregate-constant.ll
M llvm/test/CodeGen/SPIRV/constant/local-arbitrary-width-integers-constants-type-promotion.ll
M llvm/test/CodeGen/SPIRV/constant/local-bool-constants.ll
M llvm/test/CodeGen/SPIRV/constant/local-float-point-constants.ll
M llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll
M llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll
M llvm/test/CodeGen/SPIRV/constant/local-vector-matrix-constants.ll
M llvm/test/CodeGen/SPIRV/debug-info/no-nonsemantic-without-extension.ll
M llvm/test/CodeGen/SPIRV/event_no_group_cap.ll
M llvm/test/CodeGen/SPIRV/exec_mode_float_control_khr.ll
M llvm/test/CodeGen/SPIRV/expect.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_relaxed_printf_string_address_space/builtin_printf.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_relaxed_printf_string_address_space/non-constant-printf.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomic_bfloat16_load_store_xchg.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomic_int16_arithmetic.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomic_int16_load_store_xchg_cmpxchg.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomicrmw_faddfsub_bfloat16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomicrmw_fminfmax_bfloat16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_bf16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_checked.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_get_coord.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_packed.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_prefetch.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_tf32.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-barrier.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-empty-md.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-load-store-struct.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-load-store.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_faddfsub_vec_float16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_fminfmax_vec_float16.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
M llvm/test/CodeGen/SPIRV/extensions/unused-but-allowed-SPV_INTEL_arbitrary_precision_integers.ll
M llvm/test/CodeGen/SPIRV/freeze.ll
M llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll
M llvm/test/CodeGen/SPIRV/function/identity-function.ll
M llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll
M llvm/test/CodeGen/SPIRV/function/trivial-function-definition.ll
M llvm/test/CodeGen/SPIRV/function/trivial-function-with-attributes.ll
M llvm/test/CodeGen/SPIRV/function/trivial-function-with-call.ll
M llvm/test/CodeGen/SPIRV/function/variadics-lowering-builtin-substr-in-name.ll
M llvm/test/CodeGen/SPIRV/function/variadics-lowering-namespace-printf.ll
M llvm/test/CodeGen/SPIRV/global-var-intrinsic.ll
M llvm/test/CodeGen/SPIRV/half_extension.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll
M llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer_unused.ll
M llvm/test/CodeGen/SPIRV/image-unoptimized.ll
M llvm/test/CodeGen/SPIRV/image.ll
M llvm/test/CodeGen/SPIRV/image_decl_func_arg.ll
M llvm/test/CodeGen/SPIRV/image_dim.ll
M llvm/test/CodeGen/SPIRV/instructions/call-complex-function.ll
M llvm/test/CodeGen/SPIRV/instructions/call-trivial-function.ll
M llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
M llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
M llvm/test/CodeGen/SPIRV/instructions/float-fast-flags.ll
M llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
M llvm/test/CodeGen/SPIRV/instructions/scalar-bitwise-operations.ll
M llvm/test/CodeGen/SPIRV/instructions/scalar-floating-point-arithmetic.ll
M llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll
M llvm/test/CodeGen/SPIRV/instructions/undef-simple-composite-store.ll
M llvm/test/CodeGen/SPIRV/instructions/unreachable.ll
M llvm/test/CodeGen/SPIRV/instructions/vector-bitwise-operations.ll
M llvm/test/CodeGen/SPIRV/instructions/vector-floating-point-arithmetic.ll
M llvm/test/CodeGen/SPIRV/instructions/vector-integer-arithmetic.ll
M llvm/test/CodeGen/SPIRV/linkage/LinkOnceODR.ll
M llvm/test/CodeGen/SPIRV/linkage/LinkOnceODRFun.ll
M llvm/test/CodeGen/SPIRV/linked-list.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/debugtrap.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/nearbyint.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/sqrt.ll
M llvm/test/CodeGen/SPIRV/logical-access-chain.ll
M llvm/test/CodeGen/SPIRV/mangled_function.ll
M llvm/test/CodeGen/SPIRV/multi_md.ll
M llvm/test/CodeGen/SPIRV/no_capability_shader.ll
M llvm/test/CodeGen/SPIRV/opaque_pointers.ll
M llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll
M llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll
M llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll
M llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll
M llvm/test/CodeGen/SPIRV/opencl/get_num_groups.ll
M llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll
M llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll
M llvm/test/CodeGen/SPIRV/opencl/metadata/opencl_version_metadata.ll
M llvm/test/CodeGen/SPIRV/opencl/vstore2.ll
M llvm/test/CodeGen/SPIRV/physical-layout/generator-magic-number.ll
M llvm/test/CodeGen/SPIRV/physical-layout/spirv-version.ll
M llvm/test/CodeGen/SPIRV/preprocess-metadata.ll
M llvm/test/CodeGen/SPIRV/pstruct.ll
M llvm/test/CodeGen/SPIRV/read_image.ll
M llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll
M llvm/test/CodeGen/SPIRV/spec_const_decoration.ll
M llvm/test/CodeGen/SPIRV/spirv-tools-dis.ll
M llvm/test/CodeGen/SPIRV/spirv.Queue.ll
M llvm/test/CodeGen/SPIRV/spirv_param_decorations_quals.ll
M llvm/test/CodeGen/SPIRV/store.ll
M llvm/test/CodeGen/SPIRV/transcoding/DecorationMaxByteOffset.ll
M llvm/test/CodeGen/SPIRV/transcoding/GlobalFunAnnotate.ll
M llvm/test/CodeGen/SPIRV/transcoding/NoSignedUnsignedWrap.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpConstantBool.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpConstantSampler.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageReadMS.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpenCL/sub_group_mask.ll
M llvm/test/CodeGen/SPIRV/transcoding/RelationalOperators.ll
M llvm/test/CodeGen/SPIRV/transcoding/RelationalOperatorsFUnord.ll
M llvm/test/CodeGen/SPIRV/transcoding/ReqdSubgroupSize.ll
M llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll
M llvm/test/CodeGen/SPIRV/transcoding/TransFNeg.ll
M llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll
M llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll
M llvm/test/CodeGen/SPIRV/transcoding/optional-core-features-multiple.ll
M llvm/test/CodeGen/SPIRV/transcoding/readonly.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll
M llvm/test/CodeGen/SPIRV/transcoding/vec8.ll
M llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
M llvm/test/CodeGen/SPIRV/vk-pushconstant-access.ll
M llvm/test/CodeGen/SPIRV/vk-pushconstant-layout-natural.ll
Log Message:
-----------
[NFC][SPIR-V] Enable testing using spirv-val in CodeGen tests (#192407)
Commit: 0b88e333b0fee5d78bbc66f62369230c1b29ff39
https://github.com/llvm/llvm-project/commit/0b88e333b0fee5d78bbc66f62369230c1b29ff39
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/Analysis/CostModel/AArch64/masked-divrem.ll
M llvm/test/CodeGen/AArch64/masked-sdiv-fixed-length.ll
M llvm/test/CodeGen/AArch64/masked-sdiv-scalable.ll
M llvm/test/CodeGen/AArch64/masked-udiv-fixed-length.ll
M llvm/test/CodeGen/AArch64/masked-udiv-scalable.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-div.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Add custom lowering for ISD::MASKED_SDIV/UDIV. (#191164)
Also refactor custom lowering of ISD::SDIV/UDIV to replace uses of
Arch64ISD::PRED_SDIV/UDIV with the new target independent equivalents.
Commit: c74c4a8bf6f7663e1fc645e3bd43935791f33123
https://github.com/llvm/llvm-project/commit/c74c4a8bf6f7663e1fc645e3bd43935791f33123
Author: Michael Jones <michaelrj at google.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
A libc/include/string.h.def
M libc/include/string.yaml
Log Message:
-----------
[libc] Fix missing strings symbols in string.h (#192640)
The glibc string.h includes strings.h if it's in the default mode. Added
to allow more programs to be built.
Commit: efd8a91ee1e10e10fa7eeab06abbee91c5c5232d
https://github.com/llvm/llvm-project/commit/efd8a91ee1e10e10fa7eeab06abbee91c5c5232d
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
Log Message:
-----------
[VPlan] Split sinkable FindLastIV tail folding tests into new test. NFC (#191195)
Follow up to
https://github.com/llvm/llvm-project/pull/191176#pullrequestreview-4082422318
Commit: 1ba89ddd9b2baa5e5a1fdd98dfccc07cbfc1c0c3
https://github.com/llvm/llvm-project/commit/1ba89ddd9b2baa5e5a1fdd98dfccc07cbfc1c0c3
Author: Fred Tingaud <95592999+frederic-tingaud-sonarsource at users.noreply.github.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/Stmt.h
M clang/lib/AST/ExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
A clang/test/AST/ast-dump-cxx20-reversed-operator.cpp
Log Message:
-----------
[AST]Fix Location and Range for reversed rewritten CXXOperatorCallExpr (#192467)
In C++20+, when `a != b` is automatically rewritten to `!(b == a)`, the
range and sourceLocation of the generated nodes are incorrect and the
range has begin > end.
Assisted-by: Claude code
Commit: ab799d32d54eba0fb7562a2ed331a63f6fb750ee
https://github.com/llvm/llvm-project/commit/ab799d32d54eba0fb7562a2ed331a63f6fb750ee
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes c74c4a8 (#192646)
This fixes c74c4a8bf6f7663e1fc645e3bd43935791f33123.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: ea7e7527d104fb46789ba74eafe154bfa3c67fef
https://github.com/llvm/llvm-project/commit/ea7e7527d104fb46789ba74eafe154bfa3c67fef
Author: Weronika Lewandowska <weronika.lewandowska at intel.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M offload/tools/deviceinfo/llvm-offload-device-info.cpp
Log Message:
-----------
[offload] Add backend L0 to offload deviceinfo tool (#192622)
Commit: 9fa05b0377de8d9f573b9a7f026bd202ef9e897a
https://github.com/llvm/llvm-project/commit/9fa05b0377de8d9f573b9a7f026bd202ef9e897a
Author: lonely eagle <2020382038 at qq.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/MemRef/ops.mlir
Log Message:
-----------
[mlir][memref] Make memref.cast areCastCompatible return true when meet same types (#192029)
When both the source and destination types of `memref.cast` are
unranked, it causes an IR verification failure, which impacts downstream
projects and its behavior is inconsistent with the documentation. To
address this, this PR now allows the operation to return true if the
source and destination types are identical.
Commit: 705cdc3a9d0adb4c0667aa840a1f23165eca297b
https://github.com/llvm/llvm-project/commit/705cdc3a9d0adb4c0667aa840a1f23165eca297b
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
Log Message:
-----------
Reland "[AMDGPU] Generate more swaps" #184164 (#192452)
After fixing analysis of implicit register operands when matching a swap
in https://github.com/llvm/llvm-project/pull/192220, reland #184164.
#184164 was reverted in
https://github.com/llvm/llvm-project/pull/187723.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: e5bb8046685769be4f1ed685a583a8a615f8abc8
https://github.com/llvm/llvm-project/commit/e5bb8046685769be4f1ed685a583a8a615f8abc8
Author: Nico Weber <thakis at chromium.org>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
Log Message:
-----------
[gn build] Port 96266b71214a (#192663)
Commit: 00177ef8c57987d4105b9f088a6f52ec6374adf8
https://github.com/llvm/llvm-project/commit/00177ef8c57987d4105b9f088a6f52ec6374adf8
Author: Nico Weber <thakis at chromium.org>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[clang] Exposse -fdiagnostics-print-source-range-info to clang-cl (#192500)
Commit: ed9da27de8789d5052b152e2b7f64d3ea354a23a
https://github.com/llvm/llvm-project/commit/ed9da27de8789d5052b152e2b7f64d3ea354a23a
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Transform/IR/TransformOps.td
M mlir/include/mlir/Dialect/Transform/Interfaces/TransformInterfaces.h
M mlir/include/mlir/Dialect/Transform/Interfaces/TransformInterfaces.td
M mlir/lib/Dialect/Transform/IR/TransformDialect.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/Transform/IR/TransformTypes.cpp
M mlir/lib/Dialect/Transform/Interfaces/TransformInterfaces.cpp
M mlir/test/Dialect/Transform/normal-forms.mlir
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.td
Log Message:
-----------
[mlir] add normal form checked transform interface (#192647)
This interface can be implemented by operations that guarantee certain
normal forms for themselves and their regions. The operations provide
the list of normal forms they guarantee. This interface interacts with
the typed transform handles removing the need for them to check normal
forms that are guaranteed (and preserved by transforms).
Provide a simple `transform.payload` operation to carry a list of normal
forms and implement the interface.
This exposes the fact that the transform interpreter may be running the
verifier too much, but this is a pre-existing beavior that is orthogonal
to this patch.
Assisted-by: Claude Opus 4.7 / Cursor
Commit: 456bf22d5dfd0010c376190b4fca83d5d7cbb857
https://github.com/llvm/llvm-project/commit/456bf22d5dfd0010c376190b4fca83d5d7cbb857
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAArch64.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Sema/SemaARM.cpp
R clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
M clang/test/CodeGen/arm_acle.c
M clang/test/CodeGen/builtins-arm64.c
R clang/test/Sema/AArch64/pcdphint-atomic-store.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
R llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
M llvm/test/Verifier/AArch64/intrinsic-immarg.ll
Log Message:
-----------
Remove __arm_atomic_store_with_stshh from llvm (#192419)
This patch is revert of #181386 with some manual changes applied due to
revert conflicts.
Current implementation of __arm_atomic_store_with_stshh is incorrect as
it doesn't enforce the memory ordering constraints as can be seen
[here](https://godbolt.org/z/n5YnbaT8E). Different solution will need to
be implemented, but removing for now so users don't pick this up.
Commit: 0863312900d38ee124fa31c5842d3f3009ffd73f
https://github.com/llvm/llvm-project/commit/0863312900d38ee124fa31c5842d3f3009ffd73f
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/test/Lower/logical-operations.f90
M flang/test/Lower/loops2.f90
M flang/test/Lower/loops3.f90
M flang/test/Lower/memory-alloc.f90
M flang/test/Lower/zero-size.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 46) (#192439)
Tests converted from test/Lower: logical-operations.f90, loops2.f90,
loops3.f90, memory-alloc.f90, zero-size.f90
Commit: 735b15239c493fce6a5033776470892f30d7e00e
https://github.com/llvm/llvm-project/commit/735b15239c493fce6a5033776470892f30d7e00e
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libc/src/strings/strcasecmp.cpp
M libc/src/strings/strncasecmp.cpp
M libc/test/src/string/strcmp_test.cpp
M libc/test/src/strings/strcasecmp_test.cpp
M libc/test/src/strings/strncasecmp_test.cpp
Log Message:
-----------
[libc] Fix strcasecmp/strncasecmp signedness and add tests (#192632)
Fixed character signedness bug in strcasecmp and strncasecmp
implementations in src/strings/ where characters > 127 were not
correctly handled.
Added LIBC_CRASH_ON_NULLPTR checks to both functions.
Enhanced unit tests in test/src/strings/ to be comprehensive without
duplicating basic case insensitivity tests.
Updated assertions in strcasecmp_test, strncasecmp_test, and strcmp_test
to check for sign instead of exact value.
Commit: bf3cc1754024c08164d78e42bb55928d41953e95
https://github.com/llvm/llvm-project/commit/bf3cc1754024c08164d78e42bb55928d41953e95
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h
M mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-pro-fp-invalid.mlir
Log Message:
-----------
[mlir][tosa] Add `draft` information to specification version (#192122)
The draft flag can be used by useful to indicate that a specification
version is not yet finalized, and may be subject to change. This is
particularly important for serialized formats that offer guarantees
around backwards compatibility. By exposing `draft` information in the
specification version in the target environment, we can allow consumers
to query this information.
Commit: b077718c8911dea21efc4d21b2abbf2d85435640
https://github.com/llvm/llvm-project/commit/b077718c8911dea21efc4d21b2abbf2d85435640
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M bolt/include/bolt/Core/MCPlus.h
M bolt/include/bolt/Core/MCPlusBuilder.h
Log Message:
-----------
[BOLT] Support non-null MCInst operands in annotation handling (#192188)
The annotation sentinel in BOLT is a null MCInst operand appended after
all prime operands. However, some architectures (e.g. Hexagon) use
non-null MCInst operands as legitimate prime operands for duplex
sub-instructions. The existing code treated any MCInst operand as the
annotation sentinel, causing duplex sub-instructions to be
misidentified.
In getNumPrimeOperands(), only treat a null MCInst operand as the
sentinel. In getAnnotationInstOp(), skip non-null MCInst operands when
searching for the annotation sentinel.
Commit: 03d3d6bf8acd67b6f194075846df54f2497b7b19
https://github.com/llvm/llvm-project/commit/03d3d6bf8acd67b6f194075846df54f2497b7b19
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 735b152 (#192673)
This fixes 735b15239c493fce6a5033776470892f30d7e00e.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 0993b11a12e1eacd63ae8c84e0a5cff9e3f09ef6
https://github.com/llvm/llvm-project/commit/0993b11a12e1eacd63ae8c84e0a5cff9e3f09ef6
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/lib/AST/ASTContext.cpp
Log Message:
-----------
[clang] Clear ASTContext::TUDecl in 'cleanup' for easier debugging (#191697)
While the ASTContext has more things inside, I think we should at least
clear the TUDecl so that when traversing the (dangling) AST would
immediately step on the null-dereference instead of chasing dangling
pointers and crash later.
I was bitten by this in #191058.
This commit should be NFC - assuming that people didn't traverse already
dangling ASTs.
Commit: 56bb0a4fce3030b62ce842e5b06e8ecc5b816de1
https://github.com/llvm/llvm-project/commit/56bb0a4fce3030b62ce842e5b06e8ecc5b816de1
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/lit.local.cfg
Log Message:
-----------
[SPIR-V] Use ToolSubst for spirv-tools lit substitutions (#192462)
Bare-string substitutions match as substrings and the replacement path
contains the tool name, causing corrupted RUN lines
The issue is reproducible, for example, when path to llvm has tool name
substring at any point
Commit: ea2f50817fa32560f8fac227b58d6a2a9626df3b
https://github.com/llvm/llvm-project/commit/ea2f50817fa32560f8fac227b58d6a2a9626df3b
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
Log Message:
-----------
[mlir][tosa] Fix validation test (#192679)
Fixes a validation test after a merge race condition with
https://github.com/llvm/llvm-project/pull/192122 and
https://github.com/llvm/llvm-project/pull/192272.
Commit: b7e915c59354cf4e78a37363fab514ad21ebb29c
https://github.com/llvm/llvm-project/commit/b7e915c59354cf4e78a37363fab514ad21ebb29c
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Lower/HLFIR/conditional-expr.f90
Log Message:
-----------
[flang] Conditional expressions lowering: use fir.if SSA results for trivial scalar types (#192338)
For trivial scalar types (INTEGER, REAL, COMPLEX, LOGICAL, UNSIGNED),
generate `fir.if` with SSA results instead of allocating a temporary and
using `hlfir.assign`. This avoids the alloca/declare/assign/load pattern
for types that can be passed directly as SSA values.
Non-trivial scalar types (derived types, characters) continue to use the
existing temporary-based paths.
The LIT test expectations have been updated accordingly, and a test case
was added.
Commit: 7ce828298b4882c12f8218f37159b3df2be036f3
https://github.com/llvm/llvm-project/commit/7ce828298b4882c12f8218f37159b3df2be036f3
Author: v-zhangxiaomeng5 <v-zhangxiaomeng5 at xiaomi.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libcxx/src/ios.cpp
Log Message:
-----------
[libc++] Fix realloc bug in ios.cpp (#177526)
When realloc fails in the function register_callback in `ios.cpp`, the
memory will be leaked, then `__fn_` is assigned as `nullptr`,
dereferencing `__fn_` causes UB. The fix is quite simple which aligns to
`iword & pword` for `realloc`, i.e. return directly if `realloc` fails.
Regarding testing for this bug fix, because `realloc` is a C function
that we can't replace, there is no way to exercise that path easily.
Commit: 49a7f37154df354167ed3420cbee00a305e0316f
https://github.com/llvm/llvm-project/commit/49a7f37154df354167ed3420cbee00a305e0316f
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/CAS/MappedFileRegionArena.cpp
A llvm/test/tools/llvm-cas/mapping-size-too-small.test
Log Message:
-----------
[CAS] Fix assertion failure when opening CAS with smaller mapping size (#192565)
When opening an existing large CAS using a smaller requested mapping
size, the file size can be smaller than capacity while holding only a
shared lock. Replace the assertion with a graceful lock upgrade to
exclusive before resizing the file.
Commit: a342f779af8ccaebeedaec7a59dc789a0c7e8db3
https://github.com/llvm/llvm-project/commit/a342f779af8ccaebeedaec7a59dc789a0c7e8db3
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libc/include/llvm-libc-types/x86_64/mcontext_t.h
M libc/include/llvm-libc-types/x86_64/ucontext_t.h
Log Message:
-----------
[libc] Fix ucontext_t and mcontext_t for C compliance (#192648)
* x86_64/ucontext_t.h: Removed alignas to fix C compilation error.
* x86_64/mcontext_t.h: Updated include guard to prevent collision.
Commit: 69112990ebc6ade572b74c79e2535aa3bbf071fa
https://github.com/llvm/llvm-project/commit/69112990ebc6ade572b74c79e2535aa3bbf071fa
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libc/include/limits.yaml
M libc/include/llvm-libc-macros/limits-macros.h
Log Message:
-----------
[libc] Various limits adds and fixes (#192672)
Implemented and corrected POSIX limits:
* Corrected _POSIX_NAME_MAX and _POSIX_PATH_MAX definitions.
* Added PATH_MAX for Linux.
* Added _POSIX_THREAD_DESTRUCTOR_ITERATIONS and
PTHREAD_DESTRUCTOR_ITERATIONS.
* Updated limits.yaml to include these macros.
Commit: fd647ca46564e60915d3108a3dd2f0eb0499a6c1
https://github.com/llvm/llvm-project/commit/fd647ca46564e60915d3108a3dd2f0eb0499a6c1
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll
Log Message:
-----------
[AArch64] Fix codegen for FEAT_F16F32DOT with SVE2/SME. (#192668)
When compiling with +sve2/+sme, don't override to use Custom lowering
for PARTIAL_REDUCE_FMLA when it previously determined the operation was
legal due to +f16f32dot/+fp16fml.
Commit: d9b43e2e31b4f0b06e35f65e40c5aafdf67f3ae9
https://github.com/llvm/llvm-project/commit/d9b43e2e31b4f0b06e35f65e40c5aafdf67f3ae9
Author: Michael Jones <michaelrj at google.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M libc/src/__support/CMakeLists.txt
A libc/src/__support/wctype_impl.h
M libc/src/__support/wctype_utils.h
M libc/src/wctype/CMakeLists.txt
M libc/src/wctype/iswctype.cpp
M libc/src/wctype/wctype.cpp
Log Message:
-----------
[libc] Reorganize iswctype to avoid GPU/libc++ error (#192659)
After #191178 there were build errors when building the libc++
hand-in-hand pieces due to header layering.
Written with the assistance of Gemini
Commit: 6e94ad04a118cf7113463715900b772d77247bce
https://github.com/llvm/llvm-project/commit/6e94ad04a118cf7113463715900b772d77247bce
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/lib/Evaluate/fold-implementation.h
M flang/test/Evaluate/rewrite01.f90
A flang/test/Evaluate/rewrite09.f90
M flang/test/Lower/HLFIR/array-ctor-as-elemental.f90
M flang/test/Lower/HLFIR/array-ctor-as-inlined-temp.f90
M flang/test/Lower/HLFIR/array-ctor-as-runtime-temp.f90
Log Message:
-----------
[flang] Fold x + 0, 0 + x and x - 0 for INTEGER and UNSIGNED (#192479)
This fixes https://github.com/llvm/llvm-project/issues/191928.
Commit: 2c9a1a74fb7b6c3297d16fa98a0b5432317067f7
https://github.com/llvm/llvm-project/commit/2c9a1a74fb7b6c3297d16fa98a0b5432317067f7
Author: Chris Apple <cja-private at pm.me>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize-realtime.c
Log Message:
-----------
[clang][rtsan] Disallow type and realtime sanitizer combo (#192681)
Both of these sanitizer runtimes define similar interceptors, so they
may not be used together
Commit: 8656768ceb131c67da789bf95558b7485ae540a3
https://github.com/llvm/llvm-project/commit/8656768ceb131c67da789bf95558b7485ae540a3
Author: quic-k <kushpal at qti.qualcomm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/test/Driver/hexagon-toolchain-picolibc.c
Log Message:
-----------
[Hexagon] Relax toolchain check to accept ld in driver test (#192596)
Fixes failures in
https://lab.llvm.org/buildbot/#/builders/145/builds/13829
https://lab.llvm.org/buildbot/#/builders/124/builds/2152
Signed-off-by: Kushal Pal <kushpal at qti.qualcomm.com>
Commit: fce4a1eab3801c250eb6a271d0248a7b6293fa19
https://github.com/llvm/llvm-project/commit/fce4a1eab3801c250eb6a271d0248a7b6293fa19
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-04-18 (Sat, 18 Apr 2026)
Changed paths:
R clang/docs/CIR/ABILowering.md
A clang/docs/CIR/ABILowering.rst
R clang/docs/CIR/CleanupAndEHDesign.md
A clang/docs/CIR/CleanupAndEHDesign.rst
Log Message:
-----------
[CIR][docs] Migrate existing Markdown documents to reStructuredText format (#192066)
This patch migrates the existing ClangIR documents that are written in
Markdown format to reStructuredText format to align CIR's documents with
clang's documentation policy.
Closes #191850 .
Commit: 3183e576bb25defeabf8e000a05846d16fc73174
https://github.com/llvm/llvm-project/commit/3183e576bb25defeabf8e000a05846d16fc73174
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/CodeGen/X86/masked_gather_scatter.ll
Log Message:
-----------
[X86] masked_gather_scatter.ll - regenerate with VPADD asm comments (#192685)
Commit: 5de013ddcb0e93269541a9e209220414ab46d36a
https://github.com/llvm/llvm-project/commit/5de013ddcb0e93269541a9e209220414ab46d36a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
A llvm/test/CodeGen/X86/pr192034.ll
Log Message:
-----------
[X86] Add test coverage for #192034 (#192686)
Commit: b2ca7319ca38553d111b9519dfc7a4a2e2e3ac3b
https://github.com/llvm/llvm-project/commit/b2ca7319ca38553d111b9519dfc7a4a2e2e3ac3b
Author: artyo_Om <art.maklakov28 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
A llvm/test/CodeGen/X86/block-placement-triangle-profile-likely-prob.mir
Log Message:
-----------
[CodeGen] Fix profiled triangular CFG threshold in MachineBlockPlacement (#188752)
Fix an assertion failure in MachineBlockPlacement for profiled
triangular CFGs with large -profile-likely-prob values.
The existing triangular-CFG threshold scaling can produce a
BranchProbability greater than 1. Capping to `BranchProbability(100,
100)` added.
Commit: ecb2d8173782f547efac8db304c0eb41f2b0d632
https://github.com/llvm/llvm-project/commit/ecb2d8173782f547efac8db304c0eb41f2b0d632
Author: Ayush Sahay <quic_asahay at quicinc.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
Log Message:
-----------
[lldb][Windows] Read/Write PC after suspending thread (#191371)
Currently, we access the PC before suspending the thread in case of a
software breakpoint exception. However, we can't reliably read or write
the thread context while the thread is running. So, suspend the thread
first and then read or write the PC when handling a software breakpoint
exception.
Co-authored-by: Ayush Sahay <asahay at qti.qualcomm.com>
Commit: 25b0ab2d4f7a7a4b165b26d31dd563ef4dde4f17
https://github.com/llvm/llvm-project/commit/25b0ab2d4f7a7a4b165b26d31dd563ef4dde4f17
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M cross-project-tests/debuginfo-tests/dexter-tests/memvars/const-branch.c
Log Message:
-----------
[ci][llvm] Run cross-project-tests on llvm/ changes (#188522)
This patch ensures we run the `cross-project-tests` on `llvm/` PRs. At
the very least those tests depend on debug-info and
`llvm/ADT/`/`llvm/Support` (and the data-formatters that also live in
`llvm/`).
This would've helped catch
https://github.com/llvm/llvm-project/pull/188483 at pre-merge time.
Commit: d1f742532b9286196d0c60e9364a99095ba8cdd4
https://github.com/llvm/llvm-project/commit/d1f742532b9286196d0c60e9364a99095ba8cdd4
Author: jumerckx <31353884+jumerckx at users.noreply.github.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/lib/IR/OperationSupport.cpp
M mlir/test/IR/operation-equality.mlir
Log Message:
-----------
[mlir] Propagate `checkCommutativeEquivalent` into `isRegionEquivalentTo` (#192670)
The `checkCommutativeEquivalent` callback was not forwarded when
recursing into nested regions via `isRegionEquivalentTo`, causing silent
fallback to strict operand-order comparison for ops inside regions. Fix
by propagating the callback through the call site, and add a lit test
covering this case.
Commit: 4284bd02269d65ed7d5efc477ecf5b9fde8a5cef
https://github.com/llvm/llvm-project/commit/4284bd02269d65ed7d5efc477ecf5b9fde8a5cef
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/CodeGen/X86/avx-vperm2x128.ll
M llvm/test/CodeGen/X86/insertps-combine.ll
M llvm/test/CodeGen/X86/var-permute-128.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/var-permute-512.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
Log Message:
-----------
[X86] Regenerate shuffle lowering tests with VPADD asm comments (#192690)
Reduces diffs in upcoming patches
Commit: f14644d085de8e835125b4260e3f3ceee8681f93
https://github.com/llvm/llvm-project/commit/f14644d085de8e835125b4260e3f3ceee8681f93
Author: Kevin Sala Penades <salapenades1 at llnl.gov>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M offload/include/Shared/APITypes.h
M offload/include/device.h
M offload/include/omptarget.h
M offload/liboffload/src/OffloadImpl.cpp
M offload/libomptarget/device.cpp
M offload/libomptarget/interface.cpp
M offload/libomptarget/omptarget.cpp
M offload/libomptarget/private.h
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/include/RecordReplay.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
A offload/test/tools/omp-kernel-replay/record-replay-diff-teams-threads.cpp
A offload/test/tools/omp-kernel-replay/record-replay-diff-threads.cpp
M offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
Log Message:
-----------
[offload] Add mechanism to return info to kernel replay tool (#192611)
This commit adds a mechanism to return information about a kernel replay
to outer replay tool. This mechanism allows verifying the replay memory
output when using different launch configurations (e.g., different number
of teams or threads) than the one used for recording.
It also adds a new KernelExtraArgsTy structure that is only generated by
the offload/libomptarget runtime components (unlike KernelArgsTy). These
runtime arguments can be used by future extensions, including extensions
not related to kernel record replay.
Commit: a8c80fe41fde8c66434af91fd5a0f2d3b71b28be
https://github.com/llvm/llvm-project/commit/a8c80fe41fde8c66434af91fd5a0f2d3b71b28be
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
Log Message:
-----------
[flang][OpenMP] Clean up check-omp-structure.h, NFC (#192695)
Group declarations to make it clear in which of the check-omp-*.cpp
files a given function is defined.
Delete declarations that don't have corresponding definitions.
Rename private member variable to follow naming convention.
Commit: fdff641f760d529c9484ecdd48b00d07d203f9a7
https://github.com/llvm/llvm-project/commit/fdff641f760d529c9484ecdd48b00d07d203f9a7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
Log Message:
-----------
[MLIR] Fix -Wunused-variable (#192698)
Inline the variable given the call does not have side effects and the
variable name does not add any clarity.
Commit: 001b1b60121e30a6b9066e54d9a35a7a341a0918
https://github.com/llvm/llvm-project/commit/001b1b60121e30a6b9066e54d9a35a7a341a0918
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
Log Message:
-----------
[MLIR] Fix forward fdff641f760d529c9484ecdd48b00d07d203f9a7 (#192701)
ninja check-mlir somehow did not catch this...
Commit: 546cc690020e4e4317cd05ea833d5e6ff00ec161
https://github.com/llvm/llvm-project/commit/546cc690020e4e4317cd05ea833d5e6ff00ec161
Author: Dmitrii Kuragin <kuraginmail at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables-objcxx.mm
Log Message:
-----------
[Clang-Tidy] Fixed `cppcoreguidelines-init-variables` to handle ObjC for-in loops. (#191306)
The check used to report false positive in case of for-in loop in
Objective-C[++]:
```
for (NSString *value in values) {
...
}
```
With the report message:
```
...: warning: variable 'value' is not initialized [cppcoreguidelines-init-variables]
for (NSString *value in values) {
^
= NULL
```
This PR exclude the for-in loop from the the matcher in order to avoid
the false-positive.
Fixes #62106
Commit: 2253d7575a52918b37012e20d2fa5d6758bc8017
https://github.com/llvm/llvm-project/commit/2253d7575a52918b37012e20d2fa5d6758bc8017
Author: Lei Huang <lei at ca.ibm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/lib/Headers/altivec.h
A clang/test/CodeGen/PowerPC/builtins-post-quantum-crypto.c
A clang/test/Sema/PowerPC/builtins-post-quantum-crypto-error.c
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
A llvm/test/CodeGen/PowerPC/post-quantum-crypto.ll
Log Message:
-----------
[PowerPC] Add builtins for Post Quantum Cryptography Acceleration (#184717)
This patch implements Post Quantum Cryptography (PQC) Acceleration
builtins for PowerPC's future ISA by ensuring that vector operations
(vec_add, vec_sub, vec_mul, vec_mulh) correctly map to VSX instructions
(xvadduwm, xvadduhm, xvsubuwm, xvsubuhm, xvmuluwm, xvmuluhm, xvmulhsw,
xvmulhsh, xvmulhuw, xvmulhuh) when targeting mcpu=future.
Implement new builtin for vec_mulh:
* vector short vec_mulh(vector signed short, vector signed short)
* vector unsigned short vec_mulh(vector unsigned short, vector unsigned
short)
Assisted by AI.
Commit: e8c8cbb06a5285b19a009af15d05d3f9fd09bfee
https://github.com/llvm/llvm-project/commit/e8c8cbb06a5285b19a009af15d05d3f9fd09bfee
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M lldb/source/Core/Debugger.cpp
A lldb/test/API/functionalities/breakpoint/breakpoint_command_auto_continue/Makefile
A lldb/test/API/functionalities/breakpoint/breakpoint_command_auto_continue/TestBreakpointCommandAutoContinue.py
A lldb/test/API/functionalities/breakpoint/breakpoint_command_auto_continue/bpcmd.py
A lldb/test/API/functionalities/breakpoint/breakpoint_command_auto_continue/main.cpp
Log Message:
-----------
[lldb] Don't adopt in the ExecutionContext from auto-continue events (#191433)
When a breakpoint auto-continues, the event handler receives a "stopped
but restarted" event. During the transition where we step over the
breakpoint (before continuing), the public state hasn't yet been set to
running. This caused the `DefaultEventHandler` to call
`ExecutionContextRef` with `adopt_selected=true`, which would fetch
stale thread/frame state and needlessly (and incorrectly) interrupt the
target to compute the execution context (used by the statusline). This
PR fixes that by not doing that.
Fixes #190956
Co-authored-by: Jim Ingham <jingham at apple.com>
Commit: 0fd21b102286f3a920950d650cb50420b0f94fc3
https://github.com/llvm/llvm-project/commit/0fd21b102286f3a920950d650cb50420b0f94fc3
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.cpp
M clang/test/SemaOpenACC/compute-construct-private-clause.cpp
M clang/test/SemaOpenACC/compute-construct-reduction-clause.cpp
Log Message:
-----------
[OpenACC] Require a complete type for vars-with-restrictions (#192680)
The bug report shows a case where an incomplete type was passed to a
var-list in a clause that has a restriction. Only the 'private',
'firstprivate', and 'reduction' clauses have such restrictions on what
they can reference, so only those will cause problems.
This patch adds a 'completeness' requirement for all 3 of those to make
sure we can properly enforce our restrictions.
Fixes: #192664
Commit: 50b859cca1ccf7d174ee61a8a130ae14220209e4
https://github.com/llvm/llvm-project/commit/50b859cca1ccf7d174ee61a8a130ae14220209e4
Author: Addmisol <addmisol9 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M clang/lib/CodeGen/Targets/AMDGPU.cpp
A clang/test/CodeGen/amdgpu-abi-struct-coerce.c
M clang/test/CodeGen/amdgpu-variadic-call.c
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
M clang/test/Headers/amdgcn-openmp-device-math-complex.c
Log Message:
-----------
[AMDGPU] Stop coercing structs with FP and int fields to integer arrays (#185083)
Fixes #184150
This PR fixes the ABI lowering code for small aggregates (≤64 bits) on
AMDGPU targets to selectively coerce based on element types:
- Structs containing only sub-32-bit integers (char, short): Continue to
coerce to i16/i32/[2 x i32] for efficient register packing
- Structs containing floats or full-sized integers (i32, i64, float,
double): Preserve original types using ABIArgInfo::getDirect() without
coercion
Previously, ALL small aggregates were unconditionally coerced to integer
types. A struct like { float, int } would be lowered to [2 x i32],
losing the floating-point type information. This prevented attaching
FP-specific attributes like nofpclass to the float
component.
Changes
- clang/lib/CodeGen/Targets/AMDGPU.cpp: Added
containsOnlyPackableIntegerTypes() helper function that recursively
checks if an aggregate contains only sub-32-bit integer types. Updated
classifyReturnType and classifyArgumentType to use this helper - only
coercing
aggregates that contain exclusively small integers, while preserving
types for aggregates containing floats or full-sized integers.
- clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl: Updated expected
output to reflect that char-only structs are still coerced (e.g.,
struct_char_x8 -> [2 x i32]) while preserving correct behavior.
- clang/test/CodeGen/amdgpu-abi-struct-coerce.c: Added test coverage for
various struct types including mixed float/int fields, demonstrating the
selective coercion behavior.
Before/After
// Struct with float - NOW preserves types
typedef struct { float f; int i; } fp_int_pair;
Before: define [2 x i32] @ foo([2 x i32] %x.coerce)
After: define %struct.fp_int_pair @ foo(float %x.coerce0, i32
%x.coerce1)
// Struct with only small integers - STILL coerced for efficiency
typedef struct { char a, b, c, d, e, f, g, h; } eight_chars;
Before: define [2 x i32] @ bar([2 x i32] %x.coerce)
After: define [2 x i32] @ bar([2 x i32] %x.coerce) // Unchanged
Test Plan
- Updated existing ABI tests in amdgpu-abi-struct-coerce.cl
- Added new test amdgpu-abi-struct-coerce.c for mixed FP/int structs
- Updated affected OpenMP complex math header tests
Commit: 38ab75da336d7c0f9c87bf4fab9ce858dfa8a208
https://github.com/llvm/llvm-project/commit/38ab75da336d7c0f9c87bf4fab9ce858dfa8a208
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
[Github][CI] Add note about AI tools in good-first-issue text (#173109)
After https://github.com/llvm/llvm-project/pull/172515, we have a new
paragraph in LLVM policy about AI:
> The one exception we reserve is for GitHub issues labelled with the
“good first issue” label. These issues are selected by LLVM contributors
to help newcomers get familiar with the code base. Thus, it makes no
sense to fix them using AI tools. Using AI tools to fix issues labelled
as “good first issues” is forbidden.
We should add disclosure about it in the introduction note for
developers to see clearly.
---------
Co-authored-by: Reid Kleckner <rkleckner at nvidia.com>
Commit: 12771e9568972500a217481ab5c9960a596ba184
https://github.com/llvm/llvm-project/commit/12771e9568972500a217481ab5c9960a596ba184
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M lldb/test/API/lang/c/ptrauth/TestPtrAuth.py
M lldb/test/API/lang/c/ptrauth/main.c
Log Message:
-----------
[lldb] Convert TestPtrAuth.py from an inline to a regular test (NFC) (#192705)
This PR changes TestPtrAuth.py from an inline to a "regular" API test.
The motivation for this is #191416 and the need to specify parameters to
the build.
Commit: 1b62eaa2bf051a8207c86454ede3420e9f9d4886
https://github.com/llvm/llvm-project/commit/1b62eaa2bf051a8207c86454ede3420e9f9d4886
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/include/flang/Lower/OpenACC.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-loop-collapse-force-lowering.f90
A flang/test/Lower/OpenACC/acc-loop-collapse-force-non-tightly-nested.f90
M flang/test/Semantics/OpenACC/acc-collapse-force.f90
Log Message:
-----------
[flang][acc] Fix crash on collapse(force:N) with non-tightly nested loops (#191310)
When collapse(force:N) is applied to non-tightly nested loops, the
compiler could crash or generate redundant inner loops.
Crashes occurred because getNestedEvaluations() was called without
checking hasNestedEvaluations() first. Add guards in hasEarlyReturn(),
createRegionOp(), and the collapse-force sinking logic in Bridge.cpp.
Redundant inner loops were generated because processDoLoopBounds
absorbed N levels of do-loops into the outer acc.loop, but the PFT
walker still generated separate acc.loop ops for those same loops.
Fix by tracking absorbed DoConstruct* pointers in visitLoopControl
and skipping them in genFIR(DoConstruct).
Commit: d84356e74f5357a3a22317d4e766e244c28865b6
https://github.com/llvm/llvm-project/commit/d84356e74f5357a3a22317d4e766e244c28865b6
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for wave_reduce intrinsics (#192377)
Commit: cd0b558c195bd4d13aa311f081722fea51459a47
https://github.com/llvm/llvm-project/commit/cd0b558c195bd4d13aa311f081722fea51459a47
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/OpenACC/acc-host-data-cuda-device.f90
Log Message:
-----------
[flang][cuda][openacc] use the ultimate symbol to set the implicit device attribute (#192553)
The attribute was not applied when the symbol had a UseDetails. Use the
ultimate symbol so we get the proper ObjectEntityDetails to apply the
implicit attribute.
Commit: 2b8311ef3e6484679370d60b369aa189f48981b9
https://github.com/llvm/llvm-project/commit/2b8311ef3e6484679370d60b369aa189f48981b9
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Lower/OpenACC/acc-routine-named-external.f90
Log Message:
-----------
[flang][OpenACC] Support acc routine info on ProcEntityDetails for separate compilation (#192367)
When !$acc routine(name) vector is used in a caller for an external
subroutine, the symbol has ProcEntityDetails (not SubprogramDetails).
The routine info (vector/worker/gang/seq) was silently lost because
AddRoutineInfoToSymbol only handled SubprogramDetails, and CallInterface
only checked SubprogramDetails for openACCRoutineInfos.
Add openACCRoutineInfos storage to ProcEntityDetails and handle it in
both AddRoutineInfoToSymbol and CallInterface so the parallelism level
is properly lowered to acc.routine with the correct keyword.
Commit: f6916bded9f5306057824c5be7c5a877baa1bdc3
https://github.com/llvm/llvm-project/commit/f6916bded9f5306057824c5be7c5a877baa1bdc3
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll
M llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
M llvm/test/Transforms/LoopVectorize/vplan-native-path-inner-loop-with-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
Log Message:
-----------
[LV] Modernize outer loop tests check lines (NFC) (#192689)
Re-generate check lines with latest UTC, adjust naming for consistency.
Commit: 55e8c5e0eaea9943c2039a8add9525ed90dad03a
https://github.com/llvm/llvm-project/commit/55e8c5e0eaea9943c2039a8add9525ed90dad03a
Author: adeshcom14 <aadikane at amd.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
Log Message:
-----------
[AMDGPU] Mark ASYNCMARK as meta instruction to fix hazard cycle miscounting (#189981)
ASYNCMARK emits no hardware code it is used for tracking purpose but was
not marked as meta, causing getNumWaitStates to return 1 and
GCNHazardRecognizer to incorrectly count it as a pipeline cycle.
This patch marks ASYNCMARK as meta-Instruction so it correctly reports 0
wait states.
Fixes: #186878
Commit: 86397f49c7725f35a51517a8290cb4207c97771d
https://github.com/llvm/llvm-project/commit/86397f49c7725f35a51517a8290cb4207c97771d
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/builders/builder.py
M lldb/packages/Python/lldbsuite/test/builders/darwin.py
M lldb/packages/Python/lldbsuite/test/configuration.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/packages/Python/lldbsuite/test/dotest_args.py
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/test/API/commands/expression/ptrauth-auth-traps/Makefile
M lldb/test/API/commands/expression/ptrauth-auth-traps/TestPtrAuthAuthTraps.py
M lldb/test/API/commands/expression/ptrauth-objc/Makefile
M lldb/test/API/commands/expression/ptrauth-objc/TestPtrAuthObjectiveC.py
M lldb/test/API/commands/expression/ptrauth-vtable/Makefile
M lldb/test/API/commands/expression/ptrauth-vtable/TestPtrAuthVTableExpressions.py
M lldb/test/API/commands/expression/ptrauth/Makefile
M lldb/test/API/commands/expression/ptrauth/TestPtrAuthExpressions.py
M lldb/test/API/lang/c/ptrauth/Makefile
M lldb/test/API/lang/c/ptrauth/TestPtrAuth.py
Log Message:
-----------
[lldb] Rally around triple rather than arch in the API tests (#191416)
This PR removes as much uses of arch as possible, in favor of using
triple directly. Most of the changes are in the builder, which no longer
passes `ARCH` to Make, and of course in Makefile.rules.
This significantly simplifies the remote Darwin test suite, as it
previously had to try and piece together the triple from the platform
and the arch. As an added benefit, we now go through the same code path
for host and remote test runs.
I have tested this on Darwin and Linux and made the changes with the
remote test suites in mind, but it's possible I missed something not
caught by my local testing.
Commit: 1bf82626f7024cc66d46d07dfebd55d0acb44b29
https://github.com/llvm/llvm-project/commit/1bf82626f7024cc66d46d07dfebd55d0acb44b29
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/acc-declare-global-component-not-supported.f90
M flang/test/Lower/OpenACC/acc-declare.f90
Log Message:
-----------
[flang][acc] Accept component reference in non-global `acc declare` (#192563)
The current TODO was being issued for all cases of `acc declare`
including ones which are treated as a subroutine-scope lifetime. Since
the latter use normal data mapping clauses without the need for
ctors/dtors, accept them. However, still emit TODO for the cases where
component references are `acc declare`d in global context.
Commit: 809b4cfa2b15f1e5699ff00c842266e5362ccd32
https://github.com/llvm/llvm-project/commit/809b4cfa2b15f1e5699ff00c842266e5362ccd32
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/utils/lit/lit/Test.py
M llvm/utils/lit/lit/TestTimes.py
M llvm/utils/lit/lit/discovery.py
A llvm/utils/lit/tests/Inputs/malformed-test-times/a.txt
A llvm/utils/lit/tests/Inputs/malformed-test-times/b.txt
A llvm/utils/lit/tests/Inputs/malformed-test-times/lit.cfg
A llvm/utils/lit/tests/Inputs/malformed-test-times/lit_test_times
A llvm/utils/lit/tests/malformed-test-times.py
Log Message:
-----------
[llvm-lit] Error on malformed `.lit_test_times` entries instead of stack trace (#191305)
When running `llvm-lit`, I sometimes hit a traceback, because a
`.lit_test_times.txt` file has got corrupted (not sure how).
However, it's non-obvious what the issue is (you just get a traceback),
so I've fixed this as follows:
`read_test_times()` currently assumes every line in
`.lit_test_times.txt`
contains a floating-point time followed by a test path. If the file
contains a blank line, a line without a path, or a non-numeric time,
`llvm-lit` will now error with: `fatal: found malformed timing data in`
+ filename.
Add test coverage for this too.
Commit: faf63e97020c589eea64ddfcc64e0fbc1a40d8c4
https://github.com/llvm/llvm-project/commit/faf63e97020c589eea64ddfcc64e0fbc1a40d8c4
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M flang/test/Lower/PowerPC/ppc-intrinsics.f90
M flang/test/Lower/PowerPC/ppc-mma-accumulator-move-clear.f90
M flang/test/Lower/PowerPC/ppc-mma-assemble-disassemble.f90
M flang/test/Lower/PowerPC/ppc-mma-outer-product-1.f90
M flang/test/Lower/PowerPC/ppc-mma-outer-product-2.f90
M flang/test/Lower/PowerPC/ppc-pwr10-vec-intrinsics.f90
M flang/test/Lower/PowerPC/ppc-vec-abs.f90
M flang/test/Lower/PowerPC/ppc-vec-add-and-mul-sub-xor.f90
M flang/test/Lower/PowerPC/ppc-vec-any.f90
M flang/test/Lower/PowerPC/ppc-vec-cmp.f90
M flang/test/Lower/PowerPC/ppc-vec-cvf-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-max-min-madd-nmsub.f90
M flang/test/Lower/PowerPC/ppc-vec-merge-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-merge.f90
M flang/test/Lower/PowerPC/ppc-vec-perm-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-perm.f90
M flang/test/Lower/PowerPC/ppc-vec-sel.f90
M flang/test/Lower/PowerPC/ppc-vec-shift-be-le.f90
M flang/test/Lower/PowerPC/ppc-vec-shift.f90
M flang/test/Lower/PowerPC/ppc-vec-splat-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vector-types.f90
Log Message:
-----------
[flang][PPC] Remove -flang-experimental-hlfir flag in ppc vector tests (NFC) (#192715)
Commit: 3b45641a3d9b40c1c7210e4cf66a473a9f720d44
https://github.com/llvm/llvm-project/commit/3b45641a3d9b40c1c7210e4cf66a473a9f720d44
Author: Anshul Nigham <nigham at google.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-uzp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
Log Message:
-----------
[NewPM] Adds a port for AArch64PostLegalizerLowering (#190718)
Standard porting (extraction into a helper function shared across legacy
and new PM passes).
Dropped unused include `TargetPassConfig.h`
Commit: 37a8c718182a1dc25e46ae2295f172abb3791d78
https://github.com/llvm/llvm-project/commit/37a8c718182a1dc25e46ae2295f172abb3791d78
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M lldb/source/Commands/CommandObjectDWIMPrint.cpp
M lldb/source/Commands/CommandObjectDisassemble.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Commands/CommandObjectThread.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/CommandReturnObject.cpp
M lldb/source/Target/Thread.cpp
M lldb/test/Shell/Commands/command-disassemble-process.yaml
M lldb/test/Shell/Commands/command-disassemble.s
M lldb/test/Shell/Commands/command-list-reach-beginning-of-file.test
M lldb/test/Shell/Commands/command-list-reach-end-of-file.test
M lldb/test/Shell/Driver/LocalLLDBInit.test
Log Message:
-----------
[lldb] Assert lack of trailing period or newlines in diagnostics (#191447)
This PR adds an assert to `CommandReturnObject::{AppendNote,
AppendWarning}` to ensure the diagnostics don't end with a newline,
which is added by the function, or a period, which goes against the
coding standards.
I added a little helper that asserts in assert-enabled builds and trim
the diagnostic otherwise. I know that goes against the notion that
"asserts are preconditions" and therefore you shouldn't handle the case
where they don't hold (something I generally advocate for) but I think
we should prioritize a consistent user experience over purity.
We should do the same thing for `AppendError`, but currently there are
still too many violations that need to be cleaned up and if the compiler
emits non-compliant diagnostics, we may not be able to do this at all.
Commit: 6c3d84cbdf987e3f2eb113fb4e9212c56b54c6b5
https://github.com/llvm/llvm-project/commit/6c3d84cbdf987e3f2eb113fb4e9212c56b54c6b5
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/ValueMapper.h
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Transforms/Utils/ValueMapper.cpp
A llvm/test/Transforms/FunctionImport/Inputs/inline-history.ll
A llvm/test/Transforms/FunctionImport/inline-history.ll
Log Message:
-----------
[ThinLTO] Drop !inline_history metadata when importing functions (#192564)
In #190876 we now have functions in ValueAsMetadata (!inline_history
metadata). This has caused undefined symbol linker errors in some
ThinLTO builds. The following is what's going on:
@f in module A is getting imported from module A to module B, and it has
a call with !inline_history pointing to @g in module A, so a declaration
for @g is also imported into module B. But @g gets internalized in
module A, causing the undefined symbol error at link time due to
memprof's ICP in module B creating a call to @g since we can ICP a call
to any declaration.
To avoid pulling in a function declaration that may be wrong, simply
drop !inline_history metadata when importing functions. They aren't
necessary for correctness, they only prevent inlining explosion in some
recursive edge cases. Worst case is we do another round of inlining
through mutually recursive functions and then stop again due to newly
added !inline_history metadata, which should be fine; the inlining
explosion typically happens because we keep inlining through mutually
recursive functions.
Commit: bf10fc870e0db55a81db1d0da768011370113101
https://github.com/llvm/llvm-project/commit/bf10fc870e0db55a81db1d0da768011370113101
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/utils/lit/tests/filter-failed-delete.py
M llvm/utils/lit/tests/filter-failed-rerun.py
M llvm/utils/lit/tests/filter-failed.py
Log Message:
-----------
[lit] Fix tests when run via symlinks (#192530)
If the path to Inputs/filter-failed was a symlink, it would copy the
symlinks, and then edit the same files, leading to flaky failures if the
tests ran in parallel.
Commit: 8e424e318de2f7b51b0fea27915601c4a38cdb13
https://github.com/llvm/llvm-project/commit/8e424e318de2f7b51b0fea27915601c4a38cdb13
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/rv64p.ll
Log Message:
-----------
[RISCV] Support emitting plui.h for i32 constants on RV64. (#192534)
If the constant was originally i32, it will be sign or zero
extended to i64 during type legalization. If we can prove the
upper bits aren't used we can duplicate the lower bits to allow
RISCVMatInt to select plui.h.
Commit: 59a509aa80e57c420d06f364b02f0159f7f70775
https://github.com/llvm/llvm-project/commit/59a509aa80e57c420d06f364b02f0159f7f70775
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/docs/LFI.rst
Log Message:
-----------
[LFI][Doc] Update documentation for planned features (#192128)
This PR updates the LFI documentation to be a little less
AArch64-specific in anticipation of x86-64 support. I've also updated
the planned names for the `no-lfi-stores`/`no-lfi-loads` features, and
updated the planned rewrite sequence for `x30` modifications to make it
more PAC-compatible for when we include support for that.
Commit: ee82ab9cf406a22ad801db4e906a1444209046d3
https://github.com/llvm/llvm-project/commit/ee82ab9cf406a22ad801db4e906a1444209046d3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
Log Message:
-----------
[JTS][Passes] Enable JTS By Default (#190674)
Now that the compile-time issues have been fixed (#190092) and given
that was the last known blocker for enabling this pass, try enabling it
by default again.
Previous attempts at enablement are in
https://github.com/llvm/llvm-project/pull/82546 and
https://github.com/llvm/llvm-project/pull/83229 which were
reverted/never landed due to causing compile time explosions in
std::variant heavy code such as flang with old libstdc++ versions.
https://llvm-compile-time-tracker.com/compare.php?from=2aa4100fa710ed83c5acd7505c27b4498f727c8e&to=4d80149901a224a90505c3b30192dab20cca5358&stat=instructions:u
Compile time looks like it should just be noise.
Commit: 2733bc59596a99597659097460a1e2ee4cdba6d0
https://github.com/llvm/llvm-project/commit/2733bc59596a99597659097460a1e2ee4cdba6d0
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-17 (Fri, 17 Apr 2026)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .github/CODEOWNERS
M bolt/include/bolt/Core/MCPlus.h
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/Instrumentation.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/clang-tidy/readability/CMakeLists.txt
M clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp
A clang-tools-extra/clang-tidy/readability/RedundantLambdaParameterListCheck.cpp
A clang-tools-extra/clang-tidy/readability/RedundantLambdaParameterListCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-lambda-parameter-list.rst
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables-objcxx.mm
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-lambda-parameter-list.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
R clang/docs/CIR/ABILowering.md
A clang/docs/CIR/ABILowering.rst
R clang/docs/CIR/CleanupAndEHDesign.md
A clang/docs/CIR/CleanupAndEHDesign.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/MemorySanitizer.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/ThreadSanitizer.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/CommentSema.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/PrettyPrinter.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/Basic/BuiltinHeaders.def
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAArch64.td
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Options/Options.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/CommentSema.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/CIR/CodeGen/CIRGenAsm.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Headers/altivec.h
M clang/lib/Headers/arm_acle.h
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaPPC.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/new-delete.cpp
A clang/test/AST/ast-dump-cxx20-reversed-operator.cpp
M clang/test/AST/ast-printer-lambda.cpp
A clang/test/AST/constexpr-lambda-diagnostic.cpp
M clang/test/C/C2y/n3353.c
A clang/test/CIR/CodeGen/field-init-eh.cpp
M clang/test/CIR/CodeGen/global-array-dtor.cpp
M clang/test/CIR/CodeGen/global-init.cpp
A clang/test/CIR/IR/branch.cir
A clang/test/CIR/IR/do-while.cir
A clang/test/CIR/IR/for.cir
M clang/test/CIR/IR/inline-asm.cir
A clang/test/CIR/IR/while.cir
R clang/test/CIR/global-var-simple.cpp
M clang/test/CXX/drs/cwg17xx.cpp
M clang/test/ClangScanDeps/prune-scanning-modules.m
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
R clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
A clang/test/CodeGen/Inputs/stdbit.h
A clang/test/CodeGen/PowerPC/builtins-post-quantum-crypto.c
A clang/test/CodeGen/PowerPC/builtins-ppc-deeply-compressed-weights.c
A clang/test/CodeGen/amdgpu-abi-struct-coerce.c
M clang/test/CodeGen/amdgpu-variadic-call.c
M clang/test/CodeGen/arm_acle.c
M clang/test/CodeGen/asm.c
A clang/test/CodeGen/builtin-stdc-bit-functions.c
M clang/test/CodeGen/builtins-arm64.c
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
M clang/test/DebugInfo/Generic/bounds-checking-debuginfo.c
M clang/test/DebugInfo/Generic/cfi-check-fail-debuginfo.c
M clang/test/DebugInfo/Generic/cfi-icall-generalize-debuginfo.c
M clang/test/DebugInfo/Generic/cfi-icall-normalize2-debuginfo.c
M clang/test/DebugInfo/Generic/ubsan-function-debuginfo.c
M clang/test/DebugInfo/Generic/unsigned-promotion-debuginfo.c
A clang/test/Driver/amdgpu-multilib.yaml
M clang/test/Driver/cl-options.c
M clang/test/Driver/fsanitize-realtime.c
M clang/test/Driver/hexagon-toolchain-picolibc.c
A clang/test/Driver/nvptx-multilib.yaml
M clang/test/Driver/serenity.cpp
M clang/test/Headers/amdgcn-openmp-device-math-complex.c
A clang/test/Interpreter/ftime-report.cpp
M clang/test/Lexer/cxx-features.cpp
M clang/test/OpenMP/metadirective_device_arch_codegen.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
R clang/test/Preprocessor/p2843r3.cpp
M clang/test/Preprocessor/predefined-macros.c
R clang/test/Sema/AArch64/pcdphint-atomic-store.c
A clang/test/Sema/Inputs/stdbit.h
A clang/test/Sema/PowerPC/builtins-post-quantum-crypto-error.c
A clang/test/Sema/builtin-stdc-bit-functions.c
A clang/test/Sema/builtins-ppc-deeply-compressed-weights-error.c
M clang/test/Sema/warn-documentation.cpp
M clang/test/Sema/warn-lifetime-safety-suggestions.cpp
A clang/test/SemaCXX/constexpr-builtin-stdc-bit-functions.cpp
M clang/test/SemaCXX/cxx1z-constexpr-lambdas.cpp
M clang/test/SemaCXX/cxx2a-consteval.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
M clang/test/SemaCXX/void-lambda-return-init.cpp
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.cpp
M clang/test/SemaOpenACC/compute-construct-private-clause.cpp
M clang/test/SemaOpenACC/compute-construct-reduction-clause.cpp
M clang/test/SemaTemplate/GH75426.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/tools/driver/cc1_main.cpp
M clang/unittests/Support/TimeProfilerTest.cpp
M clang/www/cxx_dr_status.html
M clang/www/cxx_status.html
M compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc
M compiler-rt/lib/tysan/tysan.cpp
M cross-project-tests/debuginfo-tests/dexter-tests/memvars/const-branch.c
M cross-project-tests/lit.cfg.py
M flang-rt/lib/cuda/pointer.cpp
M flang-rt/lib/runtime/type-info.cpp
M flang-rt/unittests/Runtime/Descriptor.cpp
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Lower/MultiImageFortran.h
M flang/include/flang/Lower/OpenACC.h
A flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/include/flang/Optimizer/Dialect/CUF/Attributes/CUFAttr.h
M flang/include/flang/Optimizer/Dialect/MIF/MIFOps.td
M flang/include/flang/Optimizer/Transforms/MIFOpConversion.h
M flang/include/flang/Runtime/CUDA/pointer.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Evaluate/fold-implementation.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/MIF/CMakeLists.txt
M flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAllocationConversion.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Evaluate/rewrite01.f90
A flang/test/Evaluate/rewrite09.f90
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/test/Fir/MIF/change_team.mlir
M flang/test/Fir/MIF/change_team2.mlir
A flang/test/Fir/MIF/coarray-alloc.mlir
M flang/test/Fir/MIF/form_team.mlir
M flang/test/Fir/MIF/get_team.mlir
M flang/test/Fir/MIF/sync_team.mlir
M flang/test/Fir/MIF/team_number.mlir
M flang/test/Lower/CUDA/cuda-data-attribute.cuf
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/HLFIR/array-ctor-as-elemental.f90
M flang/test/Lower/HLFIR/array-ctor-as-inlined-temp.f90
M flang/test/Lower/HLFIR/array-ctor-as-runtime-temp.f90
M flang/test/Lower/HLFIR/conditional-expr.f90
M flang/test/Lower/Intrinsics/transfer.f90
A flang/test/Lower/MIF/coarray_allocation.f90
A flang/test/Lower/MIF/coarray_allocation2.f90
A flang/test/Lower/MIF/coarray_allocation3.f90
A flang/test/Lower/MIF/coarray_allocation4.f90
A flang/test/Lower/MIF/coarray_allocation5.f90
A flang/test/Lower/OpenACC/acc-declare-global-component-not-supported.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-host-data-cuda-device.f90
M flang/test/Lower/OpenACC/acc-loop-collapse-force-lowering.f90
A flang/test/Lower/OpenACC/acc-loop-collapse-force-non-tightly-nested.f90
A flang/test/Lower/OpenACC/acc-routine-named-external.f90
M flang/test/Lower/PowerPC/ppc-intrinsics.f90
M flang/test/Lower/PowerPC/ppc-mma-accumulator-move-clear.f90
M flang/test/Lower/PowerPC/ppc-mma-assemble-disassemble.f90
M flang/test/Lower/PowerPC/ppc-mma-outer-product-1.f90
M flang/test/Lower/PowerPC/ppc-mma-outer-product-2.f90
M flang/test/Lower/PowerPC/ppc-pwr10-vec-intrinsics.f90
M flang/test/Lower/PowerPC/ppc-vec-abs.f90
M flang/test/Lower/PowerPC/ppc-vec-add-and-mul-sub-xor.f90
M flang/test/Lower/PowerPC/ppc-vec-any.f90
M flang/test/Lower/PowerPC/ppc-vec-cmp.f90
M flang/test/Lower/PowerPC/ppc-vec-convert.f90
M flang/test/Lower/PowerPC/ppc-vec-cvf-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-load-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-load.f90
M flang/test/Lower/PowerPC/ppc-vec-max-min-madd-nmsub.f90
M flang/test/Lower/PowerPC/ppc-vec-merge-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-merge.f90
M flang/test/Lower/PowerPC/ppc-vec-perm-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-perm.f90
M flang/test/Lower/PowerPC/ppc-vec-sel.f90
M flang/test/Lower/PowerPC/ppc-vec-shift-be-le.f90
M flang/test/Lower/PowerPC/ppc-vec-shift.f90
M flang/test/Lower/PowerPC/ppc-vec-splat-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-store.f90
M flang/test/Lower/PowerPC/ppc-vector-types.f90
M flang/test/Lower/logical-operations.f90
M flang/test/Lower/loops2.f90
M flang/test/Lower/loops3.f90
M flang/test/Lower/memory-alloc.f90
M flang/test/Lower/zero-size.f90
M flang/test/Semantics/OpenACC/acc-collapse-force.f90
M flang/test/Semantics/cuf03.cuf
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/aarch64/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/config/windows/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/wctype_t.h
A libc/hdr/wctype_overlay.h
M libc/include/CMakeLists.txt
M libc/include/limits.yaml
M libc/include/llvm-libc-macros/limits-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/wctype_t.h
M libc/include/llvm-libc-types/x86_64/mcontext_t.h
M libc/include/llvm-libc-types/x86_64/ucontext_t.h
A libc/include/string.h.def
M libc/include/string.yaml
M libc/include/wctype.yaml
M libc/src/CMakeLists.txt
M libc/src/__support/CMakeLists.txt
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/CndVar.h
M libc/src/__support/threads/darwin/futex_utils.h
A libc/src/__support/threads/futex_utils.h
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
A libc/src/__support/wctype_impl.h
M libc/src/__support/wctype_utils.h
M libc/src/semaphore/CMakeLists.txt
M libc/src/semaphore/posix_semaphore.h
M libc/src/strings/strcasecmp.cpp
M libc/src/strings/strncasecmp.cpp
A libc/src/ucontext/CMakeLists.txt
A libc/src/ucontext/getcontext.h
A libc/src/ucontext/setcontext.h
A libc/src/ucontext/x86_64/CMakeLists.txt
A libc/src/ucontext/x86_64/getcontext.cpp
A libc/src/ucontext/x86_64/setcontext.cpp
M libc/src/wctype/CMakeLists.txt
A libc/src/wctype/iswctype.cpp
A libc/src/wctype/iswctype.h
A libc/src/wctype/wctype.cpp
A libc/src/wctype/wctype.h
M libc/test/integration/src/CMakeLists.txt
M libc/test/integration/src/__support/threads/CMakeLists.txt
A libc/test/integration/src/__support/threads/futex_requeue_test.cpp
A libc/test/integration/src/ucontext/CMakeLists.txt
A libc/test/integration/src/ucontext/ucontext_test.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/__support/threads/CMakeLists.txt
A libc/test/src/__support/threads/futex_utils_test.cpp
M libc/test/src/__support/wctype_utils_test.cpp
M libc/test/src/string/strcmp_test.cpp
M libc/test/src/strings/strcasecmp_test.cpp
M libc/test/src/strings/strncasecmp_test.cpp
A libc/test/src/ucontext/CMakeLists.txt
A libc/test/src/ucontext/ucontext_test.cpp
M libc/test/src/wctype/CMakeLists.txt
A libc/test/src/wctype/iswctype_test.cpp
A libc/test/src/wctype/wctype_test.cpp
M libclc/opencl/lib/generic/atomic/atomic_fetch_add.cl
M libclc/opencl/lib/generic/atomic/atomic_fetch_sub.cl
M libcxx/src/ios.cpp
M libcxx/utils/ci/BOT_OWNERS.txt
M libsycl/src/CMakeLists.txt
A libsycl/src/detail/device_image_wrapper.cpp
M libsycl/src/detail/device_image_wrapper.hpp
M libsycl/src/detail/device_impl.hpp
A libsycl/src/detail/device_kernel_info.hpp
R libsycl/src/detail/kernel_id.hpp
M libsycl/src/detail/program_manager.cpp
M libsycl/src/detail/program_manager.hpp
M lldb/include/lldb/API/SBVariablesOptions.h
M lldb/include/lldb/Interpreter/OptionGroupVariable.h
A lldb/include/lldb/Utility/ValueType.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/packages/Python/lldbsuite/test/builders/builder.py
M lldb/packages/Python/lldbsuite/test/builders/darwin.py
M lldb/packages/Python/lldbsuite/test/configuration.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/packages/Python/lldbsuite/test/dotest_args.py
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/API/SBVariablesOptions.cpp
M lldb/source/Commands/CommandObjectDWIMPrint.cpp
M lldb/source/Commands/CommandObjectDisassemble.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Commands/CommandObjectThread.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/CommandReturnObject.cpp
M lldb/source/Interpreter/OptionGroupVariable.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Target/Thread.cpp
M lldb/test/API/commands/expression/ptrauth-auth-traps/Makefile
M lldb/test/API/commands/expression/ptrauth-auth-traps/TestPtrAuthAuthTraps.py
M lldb/test/API/commands/expression/ptrauth-objc/Makefile
M lldb/test/API/commands/expression/ptrauth-objc/TestPtrAuthObjectiveC.py
M lldb/test/API/commands/expression/ptrauth-vtable/Makefile
M lldb/test/API/commands/expression/ptrauth-vtable/TestPtrAuthVTableExpressions.py
M lldb/test/API/commands/expression/ptrauth/Makefile
M lldb/test/API/commands/expression/ptrauth/TestPtrAuthExpressions.py
A lldb/test/API/functionalities/breakpoint/breakpoint_command_auto_continue/Makefile
A lldb/test/API/functionalities/breakpoint/breakpoint_command_auto_continue/TestBreakpointCommandAutoContinue.py
A lldb/test/API/functionalities/breakpoint/breakpoint_command_auto_continue/bpcmd.py
A lldb/test/API/functionalities/breakpoint/breakpoint_command_auto_continue/main.cpp
M lldb/test/API/lang/c/ptrauth/Makefile
M lldb/test/API/lang/c/ptrauth/TestPtrAuth.py
M lldb/test/API/lang/c/ptrauth/main.c
M lldb/test/API/tools/lldb-server/TestGdbRemoteHostInfo.py
M lldb/test/Shell/Commands/command-disassemble-process.yaml
M lldb/test/Shell/Commands/command-disassemble.s
M lldb/test/Shell/Commands/command-list-reach-beginning-of-file.test
M lldb/test/Shell/Commands/command-list-reach-end-of-file.test
M lldb/test/Shell/Driver/LocalLLDBInit.test
M llvm/docs/LFI.rst
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/TargetRegistry.h
M llvm/include/llvm/Transforms/IPO/LowerTypeTests.h
M llvm/include/llvm/Transforms/Utils.h
A llvm/include/llvm/Transforms/Utils/StripConvergenceIntrinsics.h
M llvm/include/llvm/Transforms/Utils/ValueMapper.h
M llvm/lib/CAS/MappedFileRegionArena.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/DebugInfo/DWARF/DWARFCFIPrinter.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/MC/TargetRegistry.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
A llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp
A llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SISchedule.td
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
R llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/Scalar/LoopBoundSplit.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
A llvm/lib/Transforms/Utils/StripConvergenceIntrinsics.cpp
M llvm/lib/Transforms/Utils/ValueMapper.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Analysis/CostModel/AArch64/masked-divrem.ll
M llvm/test/Analysis/CostModel/RISCV/masked-divrem.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-uzp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
M llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sme2-asm.ll
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
M llvm/test/CodeGen/AArch64/branch-relax-cross-section.mir
M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll
M llvm/test/CodeGen/AArch64/jump-table-compress.mir
M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
M llvm/test/CodeGen/AArch64/masked-sdiv-fixed-length.ll
M llvm/test/CodeGen/AArch64/masked-sdiv-scalable.ll
M llvm/test/CodeGen/AArch64/masked-udiv-fixed-length.ll
M llvm/test/CodeGen/AArch64/masked-udiv-scalable.ll
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
R llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/ptrauth-isel.ll
M llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
M llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir
A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-div.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
M llvm/test/CodeGen/AArch64/sve-sext-zext.ll
M llvm/test/CodeGen/AArch64/wineh9.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
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A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
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A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
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A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
A llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
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M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
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M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
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M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
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M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
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M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
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M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
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M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
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M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
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M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
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A llvm/test/CodeGen/BPF/cleanup-section.ll
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A llvm/test/CodeGen/DirectX/strip-convergence-intrinsics.ll
A llvm/test/CodeGen/Hexagon/sext-mul-v2i16.ll
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A llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
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M llvm/test/CodeGen/MIR/Generic/inline-asm-tiedto-missing-colon.mir
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A llvm/test/CodeGen/PowerPC/post-quantum-crypto.ll
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M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir
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A llvm/test/CodeGen/RISCV/cf-branch-isel.ll
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M llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
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M llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll
M llvm/test/CodeGen/RISCV/rvv/masked-urem.ll
M llvm/test/CodeGen/RISCV/rvv/pr99782.ll
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M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/zdinx-spill.ll
M llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
M llvm/test/CodeGen/RISCV/zilsd-spill.ll
M llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll
M llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll
M llvm/test/CodeGen/SPIRV/ExecutionMode_GLCompute.ll
M llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll
M llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll
M llvm/test/CodeGen/SPIRV/OpVectorInsertDynamic.ll
M llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll
M llvm/test/CodeGen/SPIRV/TruncToBool.ll
M llvm/test/CodeGen/SPIRV/assume.ll
M llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchChar.ll
M llvm/test/CodeGen/SPIRV/branching/analyze-branch-opt.ll
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M llvm/test/CodeGen/SPIRV/capability-Shader.ll
M llvm/test/CodeGen/SPIRV/capability-integers.ll
M llvm/test/CodeGen/SPIRV/constant/local-aggregate-constant.ll
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M llvm/test/CodeGen/SPIRV/constant/local-float-point-constants.ll
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M llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll
M llvm/test/CodeGen/SPIRV/constant/local-vector-matrix-constants.ll
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M llvm/test/CodeGen/SPIRV/exec_mode_float_control_khr.ll
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M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_relaxed_printf_string_address_space/non-constant-printf.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomic_bfloat16_load_store_xchg.ll
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M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomic_int16_load_store_xchg_cmpxchg.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomicrmw_faddfsub_bfloat16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomicrmw_fminfmax_bfloat16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_bf16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_checked.ll
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M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_joint_matrix/cooperative_matrix_tf32.ll
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M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-load-store-struct.ll
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M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_faddfsub_vec_float16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_fminfmax_vec_float16.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
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M llvm/test/CodeGen/SPIRV/extensions/unused-but-allowed-SPV_INTEL_arbitrary_precision_integers.ll
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M llvm/test/CodeGen/SPIRV/function/identity-function.ll
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M llvm/test/CodeGen/SPIRV/function/trivial-function-definition.ll
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M llvm/test/CodeGen/SPIRV/function/variadics-lowering-builtin-substr-in-name.ll
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M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll
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M llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll
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M llvm/test/CodeGen/SPIRV/instructions/unreachable.ll
M llvm/test/CodeGen/SPIRV/instructions/vector-bitwise-operations.ll
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M llvm/test/CodeGen/SPIRV/instructions/vector-integer-arithmetic.ll
M llvm/test/CodeGen/SPIRV/linkage/LinkOnceODR.ll
M llvm/test/CodeGen/SPIRV/linkage/LinkOnceODRFun.ll
M llvm/test/CodeGen/SPIRV/linked-list.ll
M llvm/test/CodeGen/SPIRV/lit.local.cfg
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/debugtrap.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/nearbyint.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/sqrt.ll
M llvm/test/CodeGen/SPIRV/logical-access-chain.ll
M llvm/test/CodeGen/SPIRV/mangled_function.ll
M llvm/test/CodeGen/SPIRV/multi_md.ll
M llvm/test/CodeGen/SPIRV/no_capability_shader.ll
M llvm/test/CodeGen/SPIRV/opaque_pointers.ll
M llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll
M llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll
M llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll
M llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll
M llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll
M llvm/test/CodeGen/SPIRV/opencl/get_num_groups.ll
M llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll
M llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll
M llvm/test/CodeGen/SPIRV/opencl/metadata/opencl_version_metadata.ll
M llvm/test/CodeGen/SPIRV/opencl/vstore2.ll
M llvm/test/CodeGen/SPIRV/physical-layout/generator-magic-number.ll
M llvm/test/CodeGen/SPIRV/physical-layout/spirv-version.ll
M llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll
M llvm/test/CodeGen/SPIRV/preprocess-metadata.ll
M llvm/test/CodeGen/SPIRV/pstruct.ll
M llvm/test/CodeGen/SPIRV/read_image.ll
M llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll
A llvm/test/CodeGen/SPIRV/smulextended-builtin.ll
M llvm/test/CodeGen/SPIRV/spec_const_decoration.ll
M llvm/test/CodeGen/SPIRV/spirv-tools-dis.ll
M llvm/test/CodeGen/SPIRV/spirv.Queue.ll
M llvm/test/CodeGen/SPIRV/spirv_param_decorations_quals.ll
M llvm/test/CodeGen/SPIRV/store.ll
A llvm/test/CodeGen/SPIRV/struct-null-pointer-member.ll
M llvm/test/CodeGen/SPIRV/transcoding/DecorationMaxByteOffset.ll
M llvm/test/CodeGen/SPIRV/transcoding/GlobalFunAnnotate.ll
M llvm/test/CodeGen/SPIRV/transcoding/NoSignedUnsignedWrap.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpConstantBool.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpConstantSampler.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageReadMS.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpenCL/sub_group_mask.ll
M llvm/test/CodeGen/SPIRV/transcoding/RelationalOperators.ll
M llvm/test/CodeGen/SPIRV/transcoding/RelationalOperatorsFUnord.ll
M llvm/test/CodeGen/SPIRV/transcoding/ReqdSubgroupSize.ll
M llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll
M llvm/test/CodeGen/SPIRV/transcoding/TransFNeg.ll
M llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll
M llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll
M llvm/test/CodeGen/SPIRV/transcoding/optional-core-features-multiple.ll
M llvm/test/CodeGen/SPIRV/transcoding/readonly.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll
M llvm/test/CodeGen/SPIRV/transcoding/vec8.ll
M llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll
M llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
A llvm/test/CodeGen/SPIRV/umulextended-builtin.ll
M llvm/test/CodeGen/SPIRV/vk-pushconstant-access.ll
M llvm/test/CodeGen/SPIRV/vk-pushconstant-layout-natural.ll
M llvm/test/CodeGen/SystemZ/twoaddr-kill.mir
M llvm/test/CodeGen/Thumb/high-reg-clobber.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
M llvm/test/CodeGen/Thumb2/high-reg-spill.mir
M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
M llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
M llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
M llvm/test/CodeGen/X86/avx-vperm2x128.ll
A llvm/test/CodeGen/X86/block-placement-triangle-profile-likely-prob.mir
M llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir
M llvm/test/CodeGen/X86/callbr-asm-kill.mir
M llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel-m32.ll
M llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/X86/callbr-asm-outputs-regallocfast.mir
M llvm/test/CodeGen/X86/cfi-xmm.ll
M llvm/test/CodeGen/X86/early-clobber.mir
M llvm/test/CodeGen/X86/flags-copy-lowering.mir
M llvm/test/CodeGen/X86/fp16-reload.mir
M llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
M llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
M llvm/test/CodeGen/X86/insertps-combine.ll
M llvm/test/CodeGen/X86/machine-copy-prop.mir
M llvm/test/CodeGen/X86/masked_gather_scatter.ll
M llvm/test/CodeGen/X86/peephole-copy.mir
A llvm/test/CodeGen/X86/pr192034.ll
M llvm/test/CodeGen/X86/pr86880.mir
M llvm/test/CodeGen/X86/regallocfast-callbr-asm-spills-after-reload.mir
M llvm/test/CodeGen/X86/scheduler-asm-moves.mir
M llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll
M llvm/test/CodeGen/X86/stack-clash-small-alloc-medium-align.ll
M llvm/test/CodeGen/X86/stack-folding-bmi2.mir
M llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/switch-jmp-edge-split.mir
M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
M llvm/test/CodeGen/X86/var-permute-128.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/var-permute-512.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/Other/fatlto.ll
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/ThinLTO/X86/lower_type_test_phi.ll
A llvm/test/Transforms/FunctionImport/Inputs/inline-history.ll
A llvm/test/Transforms/FunctionImport/inline-history.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
A llvm/test/Transforms/LoopVectorize/AArch64/splice-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/predicated-reverse-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/runtime-check-dependent-on-stride.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/pr109581-unused-blend.ll
M llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
A llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/vplan-native-path-inner-loop-with-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
M llvm/test/Transforms/LowerTypeTests/drop_type_test.ll
M llvm/test/Transforms/LowerTypeTests/drop_type_test_phi.ll
M llvm/test/Transforms/LowerTypeTests/drop_type_test_select.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-call-between-operands.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/same-node-reused.ll
M llvm/test/Transforms/SLPVectorizer/X86/bottom-to-top-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
M llvm/test/Transforms/SLPVectorizer/X86/operand-reorder-with-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll
M llvm/test/Transforms/SLPVectorizer/X86/shll1-add-sub-combined.ll
A llvm/test/Transforms/StripConvergenceIntrinsics/basic.ll
M llvm/test/Verifier/AArch64/intrinsic-immarg.ll
A llvm/test/tools/llvm-cas/mapping-size-too-small.test
M llvm/test/tools/llvm-mca/AMDGPU/gfx12-pseudo-scalar-trans.s
M llvm/test/tools/llvm-objcopy/ELF/strip-preserve-atime.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/MC/TargetRegistry.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/lit/lit/Test.py
M llvm/utils/lit/lit/TestTimes.py
M llvm/utils/lit/lit/discovery.py
A llvm/utils/lit/tests/Inputs/malformed-test-times/a.txt
A llvm/utils/lit/tests/Inputs/malformed-test-times/b.txt
A llvm/utils/lit/tests/Inputs/malformed-test-times/lit.cfg
A llvm/utils/lit/tests/Inputs/malformed-test-times/lit_test_times
M llvm/utils/lit/tests/filter-failed-delete.py
M llvm/utils/lit/tests/filter-failed-rerun.py
M llvm/utils/lit/tests/filter-failed.py
A llvm/utils/lit/tests/malformed-test-times.py
M mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Async/IR/Async.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.h
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/Transform/IR/TransformOps.td
M mlir/include/mlir/Dialect/Transform/IR/TransformTypes.td
M mlir/include/mlir/Dialect/Transform/Interfaces/CMakeLists.txt
M mlir/include/mlir/Dialect/Transform/Interfaces/TransformInterfaces.h
M mlir/include/mlir/Dialect/Transform/Interfaces/TransformInterfaces.td
M mlir/include/mlir/IR/BuiltinOps.h
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitDeclare.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
M mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Dialect/Transform/IR/TransformAttrs.cpp
M mlir/lib/Dialect/Transform/IR/TransformDialect.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/Transform/IR/TransformTypes.cpp
M mlir/lib/Dialect/Transform/Interfaces/TransformInterfaces.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/IR/ODSSupport.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/MemRef/ops.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-declare.mlir
A mlir/test/Dialect/OpenACC/compute-region-canonicalize.mlir
M mlir/test/Dialect/SPIRV/IR/group-ops.mlir
M mlir/test/Dialect/SPIRV/IR/logical-ops.mlir
M mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-pro-fp-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-pro-fp-valid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
A mlir/test/Dialect/Transform/normal-forms.mlir
M mlir/test/Dialect/Transform/ops-invalid.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/vector-contract-to-matrix-intrinsics-transforms.mlir
M mlir/test/Dialect/XeGPU/xegpu-vector-linearize.mlir
A mlir/test/IR/invalid-properties.mlir
M mlir/test/IR/operation-equality.mlir
M mlir/test/Target/SPIRV/logical-ops.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Transform/CMakeLists.txt
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.h
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.td
M mlir/unittests/Dialect/OpenACC/CMakeLists.txt
A mlir/unittests/Dialect/OpenACC/OpenACCCGOpsTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M offload/include/Shared/APITypes.h
M offload/include/device.h
M offload/include/omptarget.h
M offload/liboffload/src/OffloadImpl.cpp
M offload/libomptarget/device.cpp
M offload/libomptarget/interface.cpp
M offload/libomptarget/omptarget.cpp
M offload/libomptarget/private.h
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/include/RecordReplay.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
M offload/test/api/omp_indirect_call_table_manual.c
M offload/test/api/omp_indirect_func_array.c
M offload/test/api/omp_indirect_func_struct.c
M offload/test/mapping/map_ordering_tgt_exit_data_always_always.c
M offload/test/mapping/map_ordering_tgt_exit_data_delete_from.c
M offload/test/mapping/map_ordering_tgt_exit_data_delete_from_assumedsize.c
M offload/test/mapping/map_ordering_tgt_exit_data_from_delete_assumedsize.c
M offload/test/offloading/ompx_coords.c
A offload/test/tools/omp-kernel-replay/record-replay-diff-teams-threads.cpp
A offload/test/tools/omp-kernel-replay/record-replay-diff-threads.cpp
M offload/tools/deviceinfo/llvm-offload-device-info.cpp
M offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
M openmp/device/src/Misc.cpp
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
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