[all-commits] [llvm/llvm-project] 27769d: [RISCV] Support MachineOutlinerRegSave for RISCV (...

[Piyou Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 27769d7b5976c40f43f535ef19bcc6f8603fc3f6
      https://github.com/llvm/llvm-project/commit/27769d7b5976c40f43f535ef19bcc6f8603fc3f6
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2026-04-17 (Fri, 17 Apr 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/test/CodeGen/RISCV/machine-outliner-call-x5-liveout.mir
    A llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir
    A llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave-rv32e.mir
    A llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave.mir

  Log Message:
  -----------
  [RISCV] Support MachineOutlinerRegSave for RISCV (#191351)

This patch adds support for the RegSave strategy in the RISC-V
MachineOutliner pass. It uses t1–t6 to preserve the t0 value across the
outlined function call when t0 is unavailable. This enables more
potential outlining candidates.

---------

Co-authored-by: Craig Topper <craig.topper at sifive.com>



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