[all-commits] [llvm/llvm-project] 0a984e: [Hexagon] Optimize sext + mul pattern to use vmpyh...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Thu Apr 16 09:56:40 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slp-normalize-copyable-operand-order-via-majority-voting
Home: https://github.com/llvm/llvm-project
Commit: 0a984edbcd2e2f094f45e5ec009d444a947aea18
https://github.com/llvm/llvm-project/commit/0a984edbcd2e2f094f45e5ec009d444a947aea18
Author: Chandana Mudda <quic_csinderi at quicinc.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatterns.td
A llvm/test/CodeGen/Hexagon/sext-mul-v2i16.ll
Log Message:
-----------
[Hexagon] Optimize sext + mul pattern to use vmpyh instruction (#190316)
This patch adds TableGen patterns to recognize and optimize the pattern:
(v2i32 (mul (sext v2i16), (sext v2i16)))
And transforms it to use the M2_vmpy2s_s0 instruction which generates
the efficient vmpyh (vector multiply halfwords) instruction.
The transform is guarded by `nsw` because `M2_vmpy2s_s0` performs a
saturating signed multiply (`vmpyh(...):sat`), so the replacement is
only semantics-preserving when signed overflow is undefined in the IR.
Currently, this pattern expands to:
r3:2 = vsxthw(r0) // Sign extend
r1:0 = vsxthw(r1) // Sign extend
r1 = mpyi(r3,r1) // Scalar multiply
r0 = mpyi(r2,r0) // Scalar multiply
With this patch, it generates:
r1:0 = vmpyh(r0,r1):sat // Single vector multiply
Co-authored-by: Santanu Das <quic_santdas at quicinc.com>
Commit: fce45b3e961cac33e6b26725405a14a5b1f5d733
https://github.com/llvm/llvm-project/commit/fce45b3e961cac33e6b26725405a14a5b1f5d733
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/lib/Frontend/CompilerInstance.cpp
A clang/test/Interpreter/ftime-report.cpp
M clang/tools/driver/cc1_main.cpp
M clang/unittests/Support/TimeProfilerTest.cpp
Log Message:
-----------
[Frontend] Consolidate frontend timer setup in CompilerInstance::ExecuteAction. NFC (#192266)
Move the frontend timer creation (-ftime-report) and TimeTraceScope
("ExecuteCompiler") from cc1_main into CompilerInstance::ExecuteAction
via a new private PrepareForExecution() method. This ensures all tools
that use ExecuteAction (cc1, clang-repl, libclang, etc.) get consistent
timing infrastructure without duplicating setup code.
Commit: 5467e556a3756304e5c9a8aa93e309da755eff28
https://github.com/llvm/llvm-project/commit/5467e556a3756304e5c9a8aa93e309da755eff28
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
M llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
M llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
A llvm/test/CodeGen/RISCV/calls-cf-branch.ll
M llvm/test/CodeGen/RISCV/calls.ll
A llvm/test/CodeGen/RISCV/cf-branch-isel.ll
M llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
M llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
M llvm/test/CodeGen/RISCV/lpad.ll
M llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir
M llvm/test/CodeGen/RISCV/nest-register.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
M llvm/test/CodeGen/RISCV/pr97304.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
Log Message:
-----------
[RISCV] Generate landing pad based on cf-protection-branch flag only (#179960)
Previously, the backend generated lpad instructions when the Zicfilp
extension was enabled. This patch changes the behavior to generate lpad
instructions only when the cf-protection-branch module flag is set
(typically from -fcf-protection=branch).
This aligns with the Clang frontend's intent, which has a comment saying
"Always generate Zicfilp lpad insns, Non-zicfilp CPUs would read them as
NOP".
The Zicfilp extension is no longer required for lpad generation - only
the module flag matters. Tests that previously used
-mattr=+experimental-zicfilp to trigger lpad generation now use the
cf-protection-branch module flag.
Additionally, the selection of NonX7 variants for indirect
branches/calls is now based on the cf-protection-branch module flag
instead of the Zicfilp extension. This ensures consistent behavior: when
cf-protection-branch is enabled, X7 is reserved for landing pad labels
and cannot be used for indirect branch/call target addresses.
Commit: f4e43c43ea7da30c580d5edb1e2f5e12623d1184
https://github.com/llvm/llvm-project/commit/f4e43c43ea7da30c580d5edb1e2f5e12623d1184
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/pr109581-unused-blend.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
Log Message:
-----------
[VPlan] Remove ComputeAnyOfResult, use ComputeReductionResult. (#190039)
ComputeAnyOfResult is simply a boolean OR reduction. Remove the
dedicated opcode and model directly via ComputeReductionResult.
This simplifies and unifies the code, as well as enabling trivial
constant folding.
PR: https://github.com/llvm/llvm-project/pull/190039
Commit: 9d923ec59516041609038fabeaae8202026adec6
https://github.com/llvm/llvm-project/commit/9d923ec59516041609038fabeaae8202026adec6
Author: Lei Huang <lei at ca.ibm.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/lib/Headers/altivec.h
M clang/lib/Sema/SemaPPC.cpp
A clang/test/CodeGen/PowerPC/builtins-ppc-deeply-compressed-weights.c
A clang/test/Sema/builtins-ppc-deeply-compressed-weights-error.c
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
A llvm/test/CodeGen/PowerPC/deeply-compressed-weights.ll
Log Message:
-----------
[PowerPC] Implement Deeply Compressed Weights Builtins (#184666)
Add support for the following deeply compressed weights builtins for ISA
Future.
- vec_uncompresshn(vector unsigned char, vector unsigned char)
- vec_uncompressln(vector unsigned char, vector unsigned char)
- vec_uncompresshb(vector unsigned char, vector unsigned char)
- vec_uncompresslb(vector unsigned char, vector unsigned char)
- vec_uncompresshh(vector unsigned char, vector unsigned char)
- vec_uncompresslh(vector unsigned char, vector unsigned char)
- vec_unpack_hsn_to_byte(vector unsigned char)
- vec_unpack_lsn_to_byte(vector unsigned char)
- vec_unpack_int4_to_bf16(vector unsigned char, uint2)
- vec_unpack_int8_to_bf16(vector unsigned char, uint1)
- vec_unpack_int4_to_fp32(vector unsigned char, uint3)
- vec_unpack_int8_to_fp32(vector unsigned char, uint2)
Assisted by AI.
Commit: 82467159043f3007e41e81fb921c81beaa234a14
https://github.com/llvm/llvm-project/commit/82467159043f3007e41e81fb921c81beaa234a14
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for add_min/max intrinsics (#192356)
Commit: 04cae92976cc89c9747cb057c9d88a4c1bc25db6
https://github.com/llvm/llvm-project/commit/04cae92976cc89c9747cb057c9d88a4c1bc25db6
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/Basic/Targets/SPIR.cpp
M clang/test/Preprocessor/predefined-macros.c
Log Message:
-----------
[SPIRV] Conditionally define `__AMDGCN_UNSAFE_FP_ATOMICS__` for AMDGCN flavoured SPIR-V (#192136)
Client apps rely on the `__AMDGCN_UNSAFE_FP_ATOMICS__` macro to guide
optimised execution pathways. We were not defining it for AMDGCN
flavoured SPIR-V, which led to pessimisation.
Commit: 547197d200cbaf7b24b9f14c756310e3b60c8850
https://github.com/llvm/llvm-project/commit/547197d200cbaf7b24b9f14c756310e3b60c8850
Author: woruyu <1214539920 at qq.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
Log Message:
-----------
[NFC][AMDGPU] Rename AMDGPUUnifyDivergentExitNodes to AMDGPUUnifyDivergentExitNodesLegacy (#192399)
### Summary
This NFC patch renames the legacy pass wrapper class for
`AMDGPUUnifyDivergentExitNodes` to
`AMDGPUUnifyDivergentExitNodesLegacy`. This makes the old pass manager
wrapper explicit and avoids ambiguity. No behavior change is intended.
Commit: 1b433e936fbeef8fc1c649ad223719df897d311f
https://github.com/llvm/llvm-project/commit/1b433e936fbeef8fc1c649ad223719df897d311f
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
A mlir/test/Dialect/OpenACC/compute-region-canonicalize.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
Log Message:
-----------
[mlir][acc] Add canonicalization patterns for compute_region (#192376)
This PR improves the APIs for navigating through acc.compute_region
block arguments and also adds canonicalization patterns for those
arguments to remove unused ones and merge duplicates.
Commit: a81621a7b14ffd33d1b3fd7b6134a083f51ea1d3
https://github.com/llvm/llvm-project/commit/a81621a7b14ffd33d1b3fd7b6134a083f51ea1d3
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for perm_pk16_b{4,6,8}_u4 (#192368)
Commit: 1317890e1b81b952dbbd6d4011fc9113d4722488
https://github.com/llvm/llvm-project/commit/1317890e1b81b952dbbd6d4011fc9113d4722488
Author: Jiahao Guo <eoonguo at gmail.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Lower NEON vrsra_n intrinsics (#191129)
### Summary
Implement CIR lowering for all intrinsics in
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right-and-accumulate
This PR references the implementation from the ClangIR incubator:
https://github.com/llvm/clangir/blob/main/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp#L4854
AArch64 does not provide a dedicated "rounding shift right by immediate"
instruction. Instead, the `SRSHL` / `URSHL` intrinsics take a signed
per-lane shift amount where a negative value means right shift, so an
immediate right shift by `n` is encoded as a signed vector splat of
`-n`. The three infrastructure changes below exist to support this
encoding at the call site:
- extends `emitNeonShiftVector` with a `neg` parameter so the
right-shift-as-negative-left-shift encoding is handled inside the
helper;
- adds `getSignChangedVectorType` (also mirroring the incubator) used to
construct the signed shift-amount vector type for the unsigned path;
- replaces the `errorNYI` in `emitNeonCallToOp`'s `shift == j` branch
with an actual call to `emitNeonShiftVector`.
Tests: new CHECK lines in clang/test/CodeGen/AArch64/neon/intrinsics.c
under section 2.1.3.2.4.
Part of #185382.
Commit: 7aa2b040236bfa8b60ebec69af60f5a334ee160e
https://github.com/llvm/llvm-project/commit/7aa2b040236bfa8b60ebec69af60f5a334ee160e
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll
M llvm/test/CodeGen/X86/stack-clash-small-alloc-medium-align.ll
Log Message:
-----------
[X86] Use unsigned comparison for stack clash probing loop (#192355)
The stack clash probing loop generated in `EmitLoweredProbedAlloca` used
a signed comparison (`X86::COND_GE`) to determine when the allocation
target had been reached.
In 32-bit mode, memory addresses above `0x80000000` have the sign bit
set. If the stack pointer lands in this region, treating the addresses
as signed integers causes the comparison logic to fail. This leads to
incorrect loop execution, resulting in an infinite loop and a crash
(segmentation fault) when setting up custom stacks for pthreads mapped
above `0x80000000` in a 32b process.
This patch changes the condition code to `X86::COND_AE` (Above or
Equal), which generates an unsigned comparison. This ensures that
addresses are treated correctly as unsigned quantities on all targets.
On 64-bit systems, this change has no practical effect on valid
user-space addresses because they do not use the sign bit (being
restricted to the lower half of the address space). However, using
unsigned comparison is the correct behavior for pointer arithmetic and
bounds checks.
Reported-by: Wonsik Kim <wonsik at google.com>
Commit: dcfe195ef1cb7590207cc7a89765482cfb164767
https://github.com/llvm/llvm-project/commit/dcfe195ef1cb7590207cc7a89765482cfb164767
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
Log Message:
-----------
[MCP][NFC] Opinionated refactoring (#186239)
There are a few minor inconsistencies across the pass which I found mildly distracting:
* The use of `Def`/`Dest`/`Dst` to refer to the same thing
* Inconsistent declaration order of `Dst`/`Src` vs `Src`/`Dst`
* Lots of `->getReg()->asMCReg()`, and uses of `Register` when the pass
is always running after RA anyway.
* Some places explicitly `assert(isCopyInstr)` while others just deref
the `optional`.
Standardize on `Dst`/`Src` to match the metaphor and ordering of
`DestSourcePair`.
Assume `std::optional::operator*` will assert in any reasonable
implementation, even though this may technically be undefined behavior.
When asserts are disabled it would be anyway.
The refactor uses structured bindings for a couple reasons:
* Naturally enforces consistent order of `Dst`-then-`Src`
* Requires the use of `auto`, which ensures the declaration is not
implicitly converting from `MCRegister` back to `Register`.
In both cases the explicitness of the name `getDstSrcMCRegs` hopefully
makes the meaning at the callsite clear (`Dst, Src = DstSrc`, and
explicitly mentioning `MCReg`).
Change-Id: Ic58f555e03535d726cdad38dbe3f9c6df1b86460
Commit: ffde06f4c11927c60936802fb439a5195ac0742e
https://github.com/llvm/llvm-project/commit/ffde06f4c11927c60936802fb439a5195ac0742e
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Transforms/Utils.h
A llvm/include/llvm/Transforms/Utils/StripConvergenceIntrinsics.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
R llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
A llvm/lib/Transforms/Utils/StripConvergenceIntrinsics.cpp
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
A llvm/test/CodeGen/DirectX/strip-convergence-intrinsics.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
A llvm/test/Transforms/StripConvergenceIntrinsics/basic.ll
Log Message:
-----------
[NFC][SPIRV] Move `SPIRVStripConvergenceIntrinsics` to Utils (#188537)
The `SPIRVStripConvergenceIntrinsic` pass was written as a spirv pass as
it is the currently the only target that emits convergence tokens during
codegen. There is nothing target specific to the pass, and, we plan to
emit convergence tokens when targeting DirectX (and all targets in
general), so move the pass to a common place.
The previous pass used temporary `Undef`s, as part of moving the pass we
can simply reverse the traverse order to remove the use of `Undef` as it
is deprecated.
Enables the pass for targeting DirectX and is a pre-req for:
https://github.com/llvm/llvm-project/pull/188792.
Assisted by: Github Copilot
Commit: 9e45a7a4fa86dae50569308df5c5d5ab9a441bdc
https://github.com/llvm/llvm-project/commit/9e45a7a4fa86dae50569308df5c5d5ab9a441bdc
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
Log Message:
-----------
[clang][OpenMP] Fix __llvm_omp_indirect_call_lookup signature for targets with non-default program AS (#192470)
The argument and return value for `__llvm_omp_indirect_call_lookup` are
function pointers so make sure they are in the correct address space.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 7328b74dceed9764b9195e42f1e6f08f04727157
https://github.com/llvm/llvm-project/commit/7328b74dceed9764b9195e42f1e6f08f04727157
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Lower/PowerPC/ppc-vec-convert.f90
M flang/test/Lower/PowerPC/ppc-vec-load-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-load.f90
M flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-store.f90
Log Message:
-----------
[flang] Handle ub.poison in lowering (#192454)
This patch is to add the UB dialect registration and UBToLLVM conversion
interface in lowering.
Commit: 90fff557b9e2dba6649bee0c38ccbd787713d953
https://github.com/llvm/llvm-project/commit/90fff557b9e2dba6649bee0c38ccbd787713d953
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-16 (Thu, 16 Apr 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Frontend/CompilerInstance.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Headers/altivec.h
M clang/lib/Sema/SemaPPC.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
A clang/test/CodeGen/PowerPC/builtins-ppc-deeply-compressed-weights.c
A clang/test/Interpreter/ftime-report.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
M clang/test/Preprocessor/predefined-macros.c
A clang/test/Sema/builtins-ppc-deeply-compressed-weights-error.c
M clang/tools/driver/cc1_main.cpp
M clang/unittests/Support/TimeProfilerTest.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Lower/PowerPC/ppc-vec-convert.f90
M flang/test/Lower/PowerPC/ppc-vec-load-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-load.f90
M flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-store.f90
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Transforms/Utils.h
A llvm/include/llvm/Transforms/Utils/StripConvergenceIntrinsics.h
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
R llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
A llvm/lib/Transforms/Utils/StripConvergenceIntrinsics.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
A llvm/test/CodeGen/DirectX/strip-convergence-intrinsics.ll
A llvm/test/CodeGen/Hexagon/sext-mul-v2i16.ll
A llvm/test/CodeGen/PowerPC/deeply-compressed-weights.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
M llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
M llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
A llvm/test/CodeGen/RISCV/calls-cf-branch.ll
M llvm/test/CodeGen/RISCV/calls.ll
A llvm/test/CodeGen/RISCV/cf-branch-isel.ll
M llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
M llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
M llvm/test/CodeGen/RISCV/lpad.ll
M llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir
M llvm/test/CodeGen/RISCV/nest-register.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
M llvm/test/CodeGen/RISCV/pr97304.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
M llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll
M llvm/test/CodeGen/X86/stack-clash-small-alloc-medium-align.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/pr109581-unused-blend.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
A llvm/test/Transforms/StripConvergenceIntrinsics/basic.ll
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
A mlir/test/Dialect/OpenACC/compute-region-canonicalize.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
Log Message:
-----------
Rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/9908a04be1c5...90fff557b9e2
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