[all-commits] [llvm/llvm-project] 131789: [CIR][AArch64] Lower NEON vrsra_n intrinsics (#191...

[Jiahao Guo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1317890e1b81b952dbbd6d4011fc9113d4722488
      https://github.com/llvm/llvm-project/commit/1317890e1b81b952dbbd6d4011fc9113d4722488
  Author: Jiahao Guo <eoonguo at gmail.com>
  Date:   2026-04-16 (Thu, 16 Apr 2026)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
    M clang/test/CodeGen/AArch64/neon-intrinsics.c
    M clang/test/CodeGen/AArch64/neon/intrinsics.c

  Log Message:
  -----------
  [CIR][AArch64] Lower NEON vrsra_n intrinsics (#191129)

### Summary
Implement CIR lowering for all intrinsics in
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right-and-accumulate

This PR references the implementation from the ClangIR incubator:
https://github.com/llvm/clangir/blob/main/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp#L4854

AArch64 does not provide a dedicated "rounding shift right by immediate"
instruction. Instead, the `SRSHL` / `URSHL` intrinsics take a signed
per-lane shift amount where a negative value means right shift, so an
immediate right shift by `n` is encoded as a signed vector splat of
`-n`. The three infrastructure changes below exist to support this
encoding at the call site:

- extends `emitNeonShiftVector` with a `neg` parameter so the
right-shift-as-negative-left-shift encoding is handled inside the
helper;
- adds `getSignChangedVectorType` (also mirroring the incubator) used to
construct the signed shift-amount vector type for the unsigned path;
- replaces the `errorNYI` in `emitNeonCallToOp`'s `shift == j` branch
with an actual call to `emitNeonShiftVector`.

Tests: new CHECK lines in clang/test/CodeGen/AArch64/neon/intrinsics.c
under section 2.1.3.2.4.

Part of #185382.



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