[all-commits] [llvm/llvm-project] 232251: [AArch64] Correct comparator in regalloc hints to ...

[Leonardo Román Carrillo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 232251164fe1fe7336450bfd61810aa9b812c6bb
      https://github.com/llvm/llvm-project/commit/232251164fe1fe7336450bfd61810aa9b812c6bb
  Author: Leonardo Román Carrillo <leonardoroman at google.com>
  Date:   2026-04-16 (Thu, 16 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

  Log Message:
  -----------
  [AArch64] Correct comparator in regalloc hints to satisfy strict weak ordering (#192383)

The current comparator will have a strict-weak ordering violation for
the following scenario:
a = GoodReg ((!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) == true) && !Op1Reg
b = BadReg ((!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) == false) && !Op1Reg
c = Op1Reg

Then we would have:
a vs c
A != B && B == Op1Reg && (!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) = true && true && true ->
a < c

a vs b
A != B && B == Op1Reg && (!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) =true && false && false ->
a ~ b

b vs c
A != B && B == Op1Reg && (!CSRs.contains(A) || !MRI.def_empty(A) ||
Matrix->isPhysRegUsed(A)) = true && true && false ->
b ~ c

That will result in a strict-weak ordering violation (a < c && a ~ c),
with the new implementation we define that a < b && a < c.



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