[all-commits] [llvm/llvm-project] 75b9b7: [clang-format] Skip protected data blocks in Veril...

[sstwcw via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 75b9b7197dee865e8ca73ed26373d944c837ed09
      https://github.com/llvm/llvm-project/commit/75b9b7197dee865e8ca73ed26373d944c837ed09
  Author: sstwcw <su3e8a96kzlver at posteo.net>
  Date:   2026-04-15 (Wed, 15 Apr 2026)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/FormatTokenLexer.cpp
    M clang/lib/Format/FormatTokenLexer.h
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Skip protected data blocks in Verilog (#190695)

A Verilog file can have encrypted stuff (sections 34 and O in the spec).
This patch makes the formatter skip it. Previously the formatter could
mess it up by treating it as ordinary code.

Now the entire block following the `pragma protect` line is treated as a
single token.

The keywords added in this patch only mean special things in the pragma
lines. Thus they are not added to `VerilogExtraKeywords`.

While the files containing the stuff are machine generated, it is a bad
idea for a formatter to break code. For example, one may wish to run the
formatter on an entire project containing both ordinary and encrypted
files. Another use case is formatting the prototypes in files that
contain clear text prototypes in and encrypted implementation.



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