[all-commits] [llvm/llvm-project] d0b782: [MachineScheduler] Improve handling of phys regs i...

[Jonas Paulsson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d0b78277f0322b627e192324ac77274ebfedc210
      https://github.com/llvm/llvm-project/commit/d0b78277f0322b627e192324ac77274ebfedc210
  Author: Jonas Paulsson <paulson1 at linux.ibm.com>
  Date:   2026-04-15 (Wed, 15 Apr 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineScheduler.h
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp

  Log Message:
  -----------
  [MachineScheduler] Improve handling of phys regs in GenericScheduler. (NFC). (#187572)

Factor out the handling of coalesced preg COPYs from SystemZMachineScheduler.cpp into MachineScheduler.cpp. 

This extends the handling to other types of instructions than COPYs or immediate
loads, such as Load Address and takes care of maintaining the original input
order if both SUs are biased the same way in the same zone.

Another target that uses GenericScheduler can enable this by setting the new
MachineSchedPolicy member BiasPRegsExtra to true (default false). In a derived
scheduling strategy, this could be used either by passing /*BiasPRegsExtra=*/true
to biasPhysReg() (extra instruction detection), or by calling tryBiasPhysRegs()
instead which also preserves the original order if biased the same way.



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