[all-commits] [llvm/llvm-project] c8d6c8: [AMDGPU][NFC] Update MIR tests to use symbolic INL...

Ivan Kosarev via All-commits all-commits at lists.llvm.org
Wed Apr 15 05:26:19 PDT 2026 

  Branch: refs/heads/users/kosarev/symbolic-mir-inlineasm-update-tests
  Home:   https://github.com/llvm/llvm-project
  Commit: c8d6c8d8096d9c9d95fa600629d2fcb0da80cb16
      https://github.com/llvm/llvm-project/commit/c8d6c8d8096d9c9d95fa600629d2fcb0da80cb16
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-04-15 (Wed, 15 Apr 2026)

  Changed paths:
    M llvm/lib/CodeGen/MIRPrinter.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    M llvm/test/CodeGen/AArch64/aarch64-sme2-asm.ll
    M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
    M llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
    M llvm/test/CodeGen/AArch64/branch-relax-cross-section.mir
    M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
    M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
    M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
    M llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
    M llvm/test/CodeGen/AArch64/ptrauth-isel.ll
    M llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
    M llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
    M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
    M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
    M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
    M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
    M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
    M llvm/test/CodeGen/AMDGPU/spill-regpressure-less.mir
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
    M llvm/test/CodeGen/AMDGPU/swdev282079.mir
    M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
    M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
    M llvm/test/CodeGen/AMDGPU/vopc-remat.mir
    M llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
    M llvm/test/CodeGen/ARM/inlineasmbr-if-cvt.mir
    M llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
    M llvm/test/CodeGen/ARM/machine-outliner-unoutlinable.mir
    M llvm/test/CodeGen/LoongArch/inline-asm-clobbers-fcc.mir
    M llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
    M llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
    M llvm/test/CodeGen/MIR/X86/inline-asm-rm-exhaustion.mir
    M llvm/test/CodeGen/MIR/X86/inline-asm.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
    M llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll
    M llvm/test/CodeGen/PowerPC/callbr-asm-outputs-indirect-isel.ll
    M llvm/test/CodeGen/PowerPC/shrink-wrap.mir
    M llvm/test/CodeGen/RISCV/branch-rel.mir
    M llvm/test/CodeGen/RISCV/rvv/pr99782.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/zdinx-spill.ll
    M llvm/test/CodeGen/RISCV/zilsd-spill.ll
    M llvm/test/CodeGen/SystemZ/twoaddr-kill.mir
    M llvm/test/CodeGen/Thumb/high-reg-clobber.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
    M llvm/test/CodeGen/Thumb2/high-reg-spill.mir
    M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
    M llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
    M llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir
    M llvm/test/CodeGen/X86/callbr-asm-kill.mir
    M llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel-m32.ll
    M llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll
    M llvm/test/CodeGen/X86/callbr-asm-outputs-regallocfast.mir
    M llvm/test/CodeGen/X86/cfi-xmm.ll
    M llvm/test/CodeGen/X86/early-clobber.mir
    M llvm/test/CodeGen/X86/flags-copy-lowering.mir
    M llvm/test/CodeGen/X86/fp16-reload.mir
    M llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
    M llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
    M llvm/test/CodeGen/X86/peephole-copy.mir
    M llvm/test/CodeGen/X86/pr86880.mir
    M llvm/test/CodeGen/X86/scheduler-asm-moves.mir
    M llvm/test/CodeGen/X86/stack-folding-bmi2.mir
    M llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir
    M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
    M llvm/test/CodeGen/X86/switch-jmp-edge-split.mir
    M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll

  Log Message:
  -----------
  [AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications

More information about the All-commits mailing list