[all-commits] [llvm/llvm-project] 4a37b0: [AArch64][ISel] Add lowering for fixed-width `cttz...

[Harry Ramsey via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4a37b03357a9c5a40be292818969523c666c3115
      https://github.com/llvm/llvm-project/commit/4a37b03357a9c5a40be292818969523c666c3115
  Author: Harry Ramsey <harryramseybusiness at gmail.com>
  Date:   2026-04-14 (Tue, 14 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/AArch64/cttz.ll
    M llvm/test/CodeGen/AArch64/cttz.ll

  Log Message:
  -----------
  [AArch64][ISel] Add lowering for fixed-width `cttz` intrinsic (#190988)

This patch enables NEON to generate more efficient `cttz` intrinsics by
utilising `rbit` and `ctlz` instructions when they are legal.

# Alive Proof
https://alive2.llvm.org/ce/z/qgrT_7
```
define <8 x i8> @src_v8i8(<8 x i8> %a) {
#0:
  %r = cttz <8 x i8> %a, 1
  ret <8 x i8> %r
}
=>
define <8 x i8> @tgt_v8i8(<8 x i8> %a) {
#0:
  %rbit = bitreverse <8 x i8> %a
  %clz = ctlz <8 x i8> %rbit, 0
  ret <8 x i8> %clz
}
Transformation seems to be correct!


----------------------------------------
define <16 x i8> @src_v16i8(<16 x i8> %a) {
#0:
  %r = cttz <16 x i8> %a, 1
  ret <16 x i8> %r
}
=>
define <16 x i8> @tgt_v16i8(<16 x i8> %a) {
#0:
  %rbit = bitreverse <16 x i8> %a
  %clz = ctlz <16 x i8> %rbit, 0
  ret <16 x i8> %clz
}
Transformation seems to be correct!
```



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