[all-commits] [llvm/llvm-project] b6c9cb: [AArch64] C1-Ultra Scheduling model (#182251)

[Nashe Mncube via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b6c9cbe69d96ac80c3ed42b09c19dddc15df464e
      https://github.com/llvm/llvm-project/commit/b6c9cbe69d96ac80c3ed42b09c19dddc15df464e
  Author: Nashe Mncube <nashe.mncube at arm.com>
  Date:   2026-04-14 (Tue, 14 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64Processors.td
    A llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
    M llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
    M llvm/lib/Target/AArch64/AArch64SchedPredicates.td
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-basic-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-bf16-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-complxnum-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-flag-manipulation-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-forwarding.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-fp16fml-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-fptoint-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-i8mm-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-mte-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-rcpc-immo-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
    A llvm/test/tools/llvm-mca/AArch64/Inputs/flag-manipulation-instructions.s

  Log Message:
  -----------
  [AArch64] C1-Ultra Scheduling model (#182251)

This patch adds the C1-Ultra scheduling model. This model is largely
based on the Neoverse V3 scheduling model with appropriate changes made
based on information available in the software optimization guide for
this core.

https://developer.arm.com/documentation/111079/3-0



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