[all-commits] [llvm/llvm-project] 56ce7e: [AArch64] Fix strict weak ordering violation in re...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 56ce7ede7d290758bc00dd8596f65639d1c3544f
      https://github.com/llvm/llvm-project/commit/56ce7ede7d290758bc00dd8596f65639d1c3544f
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2026-04-14 (Tue, 14 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

  Log Message:
  -----------
  [AArch64] Fix strict weak ordering violation in regalloc hints sort. (#192055)

This fixes an error with expensive checks after landing #190139.

The issue was:

Error: comparison doesn't meet irreflexive requirements, assert(!(a <
a)).

because it could have previously returned 'true' in the ordering
function if registers A and B were equal.

Also made NFC change to rename 'HandleMatchCmpPredicateHint' ->
'HandleDestructivePredicateHint' (that was missed in the review).



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