[all-commits] [llvm/llvm-project] 0756e5: [AArch64] Hint regalloc to choose distinct predica...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0756e5985f0c329365c0b0de9fb66dad6abd5d76
      https://github.com/llvm/llvm-project/commit/0756e5985f0c329365c0b0de9fb66dad6abd5d76
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2026-04-14 (Tue, 14 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/active_lane_mask.ll
    M llvm/test/CodeGen/AArch64/combine-storetomstore.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
    M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
    M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
    M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
    M llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
    M llvm/test/CodeGen/AArch64/rcpc3-sve.ll
    M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
    M llvm/test/CodeGen/AArch64/sve-bf16-compares.ll
    M llvm/test/CodeGen/AArch64/sve-cmp-select.ll
    A llvm/test/CodeGen/AArch64/sve-distinct-predicate-dst.ll
    M llvm/test/CodeGen/AArch64/sve-fcvt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-stores.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-insert-element.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
    M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
    M llvm/test/CodeGen/AArch64/sve-load-compare-store.ll
    M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
    M llvm/test/CodeGen/AArch64/sve-masked-compressstore.ll
    M llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-brk.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpge.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpgt.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmphi.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmphs.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmplo.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpls.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmplt.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpne.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-log.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-match.ll
    M llvm/test/CodeGen/AArch64/sve-punpklo-combine.ll
    A llvm/test/CodeGen/AArch64/sve-regalloc-hint-unique-predicate-dst.mir
    M llvm/test/CodeGen/AArch64/sve-scmp.ll
    M llvm/test/CodeGen/AArch64/sve-select.ll
    M llvm/test/CodeGen/AArch64/sve-setcc.ll
    M llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
    M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
    M llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-ucmp.ll
    M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
    M llvm/test/CodeGen/AArch64/sve-vector-compress.ll

  Log Message:
  -----------
  [AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)

For some cores it is preferable to choose a destination predicate
register that does not match the governing predicate.

The hint is conservative in that it tries not to pick a callee-save
register if it's not already used/allocated for other purposes, as that
would introduce new spills/fills. Note that this might be preferable if
the instruction is executed in a loop, but it might also be less
preferable for small functions that have an SVE interface (p4-p15 are
caller-preserved).

It is enabled for all cores by default, but it can be disabled by adding
the `disable-distinct-dst-reg-cmp-match` feature. This feature can also
be added to specific cores if this behaviour is undesirable.



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