[all-commits] [llvm/llvm-project] 6d39df: [AArch64] Add tablegen patterns for store of high-...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6d39df0104136fc7e459a3d3a1787644d0621942
      https://github.com/llvm/llvm-project/commit/6d39df0104136fc7e459a3d3a1787644d0621942
  Author: David Green <david.green at arm.com>
  Date:   2026-04-13 (Mon, 13 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-stur.ll
    M llvm/test/CodeGen/AArch64/merge-store.ll
    M llvm/test/CodeGen/AArch64/st1-lane.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll

  Log Message:
  -----------
  [AArch64] Add tablegen patterns for store of high-half. (#190320)

This helps remove the extract but mean less efficient addressing modes.



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