[all-commits] [llvm/llvm-project] 2ae041: [RISCV] Expand vp.fma, fp.fmuladd, vp.fneg, vp.fpe...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ae04112967e16e8cddfd4c1d35de7c74504b8c0
      https://github.com/llvm/llvm-project/commit/2ae04112967e16e8cddfd4c1d35de7c74504b8c0
  Author: Luke Lau <luke at igalia.com>
  Date:   2026-04-13 (Mon, 13 Apr 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/pr171231.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

  Log Message:
  -----------
  [RISCV] Expand vp.fma, fp.fmuladd, vp.fneg, vp.fpext (#190589)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This PR expands four intrinsics before codegen, but doesn't remove the
codegen handling yet as both DAGCombiner and type legalization can
create these nodes.

vp.fneg and vp.fpext are expanded in lockstep with the fma/fmuladd
intrinsics since some test cases for vfmacc etc. also use these
intrinsics, and mixing dynamic and constant vls causes some of the more
complex patterns to be missed.

The fixed-length VP vfmacc, vfmsac, vfnmacc and vfnmsac tests also need
to replace the EVL of the vp.merge/vp.select with an immediate otherwise
the resulting vmerge.vvm can't be folded into them. This only happens
for fixed vector intrinsics with no passthru, since we end up with a
constant vl from the fixed vector and dynamic vl from the vp.merge that
prevents folding.

As far as I'm aware we don't emit fixed length vp.merges in practice,
since we only emit vp.merge in the loop vectorizer, and we only use it
with EVL tail folding which requires a scalable VF.



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