[all-commits] [llvm/llvm-project] 9b645a: [AArch64][llvm] Add GICv5 ICH_PPI_HVIR{0, 1}_EL2 sy...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/users/jthackray/gic_ich_ppi_hvir_regs
  Home:   https://github.com/llvm/llvm-project
  Commit: 9b645ae7c3ce795f7a1ca78a49765a85271a9f61
      https://github.com/llvm/llvm-project/commit/9b645ae7c3ce795f7a1ca78a49765a85271a9f61
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-04-13 (Mon, 13 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SystemOperands.td
    M llvm/test/MC/AArch64/armv9.7a-gcie.s

  Log Message:
  -----------
  [AArch64][llvm] Add GICv5 ICH_PPI_HVIR{0,1}_EL2 system registers

Add GICv5 `ICH_PPI_HVIR{0,1}_EL2` system registers (Interrupt
Controller PPI Hide Virtual Interrupt Registers). These registers
are added because a hypervisor may want to only expose a subset of the
PPIs to the virtual machine and hide the remaining PPIs.

The only way the hypervisor can do this is by trapping all the PPI ICV
registers which leads to additional code complexity and adds performance
overhead especially for nested virtualization.

These are documented here:
  https://developer.arm.com/documentation/111107/latest/AArch64-Registers/ICH-PPI-HVIR-n--EL2--Interrupt-Controller-PPI-Hide-Virtual-Interrupt-Registers



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