[all-commits] [llvm/llvm-project] 93c10f: [AMDGPU] Use WriteSALUDummy for v_mad_u64_u32 (#19...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 93c10f0820cd94a460f2ed5ee21b48372f322152
      https://github.com/llvm/llvm-project/commit/93c10f0820cd94a460f2ed5ee21b48372f322152
  Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
  Date:   2026-04-10 (Fri, 10 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SISchedule.td
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/bypass-div.ll
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
    M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll

  Log Message:
  -----------
  [AMDGPU] Use WriteSALUDummy for v_mad_u64_u32 (#191500)

Updates the the new Write*Dummy HWWriteRes to maintain latency -- this
is to ensure SchedModel->computeOperandLatency calls are unchanged.

This also uses the new HWWriteRes for v_mad_u64_u32 and v_mad_i64_i32. 

For an explanation of why we want to do this , see
https://github.com/llvm/llvm-project/pull/190095 . In short, the
scheduler will not try to cover the full latency of the instructions
without this new modelling.

This causes a good amount of lit churn since these instructions are well
covered.



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