[all-commits] [llvm/llvm-project] af95b0: [AMDGPU] Remove implicit super-reg defs on mov64 p...

Mon Apr 6 14:11:28 PDT 2026

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af95b0a615260a2868e5581d5fa18b9379b1c8ff
      https://github.com/llvm/llvm-project/commit/af95b0a615260a2868e5581d5fa18b9379b1c8ff
  Author: Joe Nash <joseph.nash at amd.com>
  Date:   2026-04-06 (Mon, 06 Apr 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
    M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/av_movimm_pseudo_expansion.mir
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
    M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
    M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
    M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
    M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/lrint.ll
    M llvm/test/CodeGen/AMDGPU/lround.ll
    M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
    M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
    M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/roundeven.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/swdev380865.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll

  Log Message:
  -----------
  [AMDGPU] Remove implicit super-reg defs on mov64 pseudos   (#190379)

The mov64 pseudo is split into two 32 bit movs, but those 32 bit movs
had the full 64-bit register still implicitly defined. VOPD formation is
affected, so we can emit more of them.

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