[all-commits] [llvm/llvm-project] 0546b3: [DA] Add test for GCD MIV missing dependency due t...
Michael Kruse via All-commits
all-commits at lists.llvm.org
Thu Apr 2 04:49:11 PDT 2026
Branch: refs/heads/users/meinersbur/runtimes_flangrt-common
Home: https://github.com/llvm/llvm-project
Commit: 0546b3f565b9350761f08574471ee3370fd8953c
https://github.com/llvm/llvm-project/commit/0546b3f565b9350761f08574471ee3370fd8953c
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
Log Message:
-----------
[DA] Add test for GCD MIV missing dependency due to overflow (NFC) (#172002)
Add a test case where the GCD MIV test misses a dependency due to
overflow. This will be fixed by #172003 .
Commit: 2b439327026d45bf53e59159c8e40fccf87930b6
https://github.com/llvm/llvm-project/commit/2b439327026d45bf53e59159c8e40fccf87930b6
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/DeclTemplate.cpp
A clang/test/SemaTemplate/GH188759.cpp
Log Message:
-----------
[clang] fix getReplacedTemplateParameter for function template specializations (#189559)
Commit: d43d9022c189210f0c3c52e34a47f3bd3edd4e43
https://github.com/llvm/llvm-project/commit/d43d9022c189210f0c3c52e34a47f3bd3edd4e43
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
Log Message:
-----------
[LV] Regen vplan-predicate-switch test with UTC (NFC) (#189581)
Commit: 0cecacd971a5471803b79f2b4a976ce75a2539b2
https://github.com/llvm/llvm-project/commit/0cecacd971a5471803b79f2b4a976ce75a2539b2
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/arm/adddf3.S
A compiler-rt/test/builtins/Unit/adddf3new_test.c
A compiler-rt/test/builtins/Unit/subdf3new_test.c
Log Message:
-----------
[compiler-rt][ARM] Optimized double precision FP add/sub (#179921)
The one new assembly source file, `arm/adddf3.S`, implements both
addition and subtraction via cross-branching after flipping signs, since
both operations must provide substantially the same logic. The new cmake
properties introduced in a prior commit are used to arrange that
including `adddf3.S` supersedes the C versions of both addition and
subtraction, and also informs the test suite that both functions are
available to test.
Commit: caecca035ab9fdccd1fd1b1b17452b415f89b366
https://github.com/llvm/llvm-project/commit/caecca035ab9fdccd1fd1b1b17452b415f89b366
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/test/API/commands/target/create-deps/TestTargetCreateDeps.py
M lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/TestBreakInLoadedDylib.py
M lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
M lldb/test/API/functionalities/load_after_attach/TestLoadAfterAttach.py
M lldb/test/API/functionalities/load_lazy/TestLoadUsingLazyBind.py
M lldb/test/API/functionalities/load_unload/TestLoadUnload.py
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
Log Message:
-----------
[lldb] add getFullLibName to PlatformContext (#188772)
This patch introduces `PlatformContext.getFullLibName` which returns the
full dylib name for any platform based on the base name of the dylib.
Example:
```
# Windows
PlatformContext.getFullLibName("Foo") -> "Foo.dll"
# Linux
PlatformContext.getFullLibName("Foo") -> "libFoo.so"
```
Commit: 5d2d17957514e682ee53e2512cd5ec7ffff6c1e7
https://github.com/llvm/llvm-project/commit/5d2d17957514e682ee53e2512cd5ec7ffff6c1e7
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
Log Message:
-----------
[DA] Add overflow check in GCD MIV (#172003)
Add an overflow check in the GCD MIV test. Fix the test case added in #172002 .
Commit: 66c45a3b4964106abfa6388056fba57edfde216d
https://github.com/llvm/llvm-project/commit/66c45a3b4964106abfa6388056fba57edfde216d
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/exact-rdiv-delta-overflow.ll
Log Message:
-----------
[DA] Fix overflow in the Exact RDIV test (#189578)
This patch adds an overflow check for the computation of `Delta` in the
Exact RDIV test. If an overflow is detected, the analysis bails out.
Commit: 97b78d6ff3fa1d87fc0ba6a235f1d331990918a3
https://github.com/llvm/llvm-project/commit/97b78d6ff3fa1d87fc0ba6a235f1d331990918a3
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
Log Message:
-----------
[MLIR][NVVM] Fix predicate operand index in BasicPtxBuilderInterface (#189552)
Predicate index computation was incorrect, it was not counting
write/readwrite symbols.
Wrong case
```
// CHECK: %{{.*}} = llvm.inline_asm has_side_effects asm_dialect = att "@$1 ex2.approx.ftz.f32 $0, $1;", "=f,f,b" %{{.*}}, %{{.*}} : (f32, i1) -> f32
%1 = nvvm.inline_ptx "ex2.approx.ftz.f32 {$w0}, {$r0};" ro (%input : f32), predicate = %pred -> f32
```
PR fixes, predicate index became `@$2`
```
// CHECK: %{{.*}} = llvm.inline_asm has_side_effects asm_dialect = att "@$2 ex2.approx.ftz.f32 $0, $1;", "=f,f,b" %{{.*}}, %{{.*}} : (f32, i1) -> f32
%1 = nvvm.inline_ptx "ex2.approx.ftz.f32 {$w0}, {$r0};" ro (%input : f32), predicate = %pred -> f32
```
Commit: 95db43fdb4704fd7f177eb257b0f69c1de1dc110
https://github.com/llvm/llvm-project/commit/95db43fdb4704fd7f177eb257b0f69c1de1dc110
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
Log Message:
-----------
[clang][NFC] ItaniumMangle: polish comments (#183030)
Commit: 6ddb2be00a95b8ad21168c7264a2d9e549cd24d8
https://github.com/llvm/llvm-project/commit/6ddb2be00a95b8ad21168c7264a2d9e549cd24d8
Author: Fady Farag <com.webkit.iidmsa at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/test/CodeGenObjC/constant-string-class-1.m
Log Message:
-----------
[clang][test] Add missing FileCheck pipe in constant-string-class-1.m (#189514)
The test had a CHECK directive that was never executed because the RUN
line did not pipe output to FileCheck.
Commit: fd43a646fc05758650c5edae15f199221cb1a2e4
https://github.com/llvm/llvm-project/commit/fd43a646fc05758650c5edae15f199221cb1a2e4
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
Log Message:
-----------
[clang][NFC] ItaniumMangle: modernize code style (#183027)
- Use structured bindings.
- Use if-init-statements to replace nested `if`.
- Use `using` instead of `typedef`.
---------
Co-authored-by: Timm Baeder <tbaeder at redhat.com>
Commit: c6b3da6b3eef3d49b5704950db052c10aabdcbf7
https://github.com/llvm/llvm-project/commit/c6b3da6b3eef3d49b5704950db052c10aabdcbf7
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
Log Message:
-----------
[lldb] Remove memory_tagged from MemoryRegionInfo (#189617)
By turning SetMemoryTagged into a builder method (returns a reference to
self). Then only using that in the tests that need to change the default
of "don't know".
Commit: 20562cefb033b29f5e897d4e74afceb8de8ad9f6
https://github.com/llvm/llvm-project/commit/20562cefb033b29f5e897d4e74afceb8de8ad9f6
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
Log Message:
-----------
[Clang][NFC] Remove redundant DeclContext workaround for local extern decls (#186665)
This patch removes an out-of-date FIXME.
The underlying issue was already fixed by
`Sema::adjustContextForLocalExternDecl` introduced by
https://github.com/llvm/llvm-project/commit/541b38be7bf3afded3269a33586418254d82d7b3
Commit: 68a91f3d36531dbd9d8635f45f53368179361af9
https://github.com/llvm/llvm-project/commit/68a91f3d36531dbd9d8635f45f53368179361af9
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] Remove ExtraGCD from GCD MIV (NFC) (#172004)
As some code was removed in #169927, `ExtraGCD` in `gcdMIVtest` is no
longer necessary. This patch removes it and also adjust the comments.
Commit: 914fca472009f8052867704f00b24c27d79ca5d5
https://github.com/llvm/llvm-project/commit/914fca472009f8052867704f00b24c27d79ca5d5
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[llc] Change `TargetMachine` allocation assert to error (#189541)
As we shouldn't assert an allocation (which can fail).
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: f14b865ff54d60901b43e7f7e96d91b9fa82ba9f
https://github.com/llvm/llvm-project/commit/f14b865ff54d60901b43e7f7e96d91b9fa82ba9f
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
Log Message:
-----------
[lldb] Remove "flash" and "blocksize" from MemoryRegionInfo constructor (#189636)
These are only set to non-default values after calling a constructor.
Removing them removes noise from many tests that make MemoryRegionInfos.
Commit: 161c53f66ea8044e6618d7c7829ba90196c72a79
https://github.com/llvm/llvm-project/commit/161c53f66ea8044e6618d7c7829ba90196c72a79
Author: David Truby <david.truby at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M openmp/cmake/modules/LibompUtils.cmake
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/LibompGetArchitecture.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_atomic.cpp
A openmp/runtime/src/kmp_invoke_microtask.cpp
M openmp/runtime/src/kmp_os.h
M openmp/runtime/src/kmp_platform.h
M openmp/runtime/src/kmp_runtime.cpp
M openmp/runtime/src/thirdparty/ittnotify/ittnotify_config.h
M openmp/runtime/src/z_Linux_asm.S
M openmp/runtime/src/z_Linux_util.cpp
M openmp/runtime/src/z_Windows_NT-586_util.cpp
M openmp/runtime/test/misc_bugs/many-microtask-args.c
Log Message:
-----------
[openmp] Add support for arm64ec to libomp (#176151)
This patch adds arm64ec support to libomp.
Note that this support isn't entirely usable on Windows hosts as libomp
requires LLVM_PER_TARGET_RUNTIME_DIR=On for to work correctly when
multiple runtimes are built, which is unsupported on Windows. A
following patch will add arm64x support to the build to rectify this.
Commit: 67d4842910b8cb79f31b9041bdf56c206cd768e9
https://github.com/llvm/llvm-project/commit/67d4842910b8cb79f31b9041bdf56c206cd768e9
Author: ambergorzynski <120007557+ambergorzynski at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
Log Message:
-----------
[NFC][AMDGPU] New test for untested case in SILowerSGPRSpills (#189426)
[This
case](https://github.com/llvm/llvm-project/blob/f380a878d515024fe02662471e81cd72a8b3eb93/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp#L343-L345)
is not covered by any existing tests (checked using code coverage and by
inserting an `abort` at that line). I propose a new test that tests this
line.
This is demonstrated by showing that it is the only test that fails in
the presence of the `abort`.
Commit: a839e500e8a1934d3ad0a346d3789904c2a865a9
https://github.com/llvm/llvm-project/commit/a839e500e8a1934d3ad0a346d3789904c2a865a9
Author: ambergorzynski <120007557+ambergorzynski at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-infer-fnptr-todo-type.ll
Log Message:
-----------
[NFC][SPIRV] Add test for untested case in SPIRVEmitIntrinsics (#189413)
[This
case](https://github.com/llvm/llvm-project/blob/af98e3c2cb07af90029785a78e49c2761f20088e/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp#L1233-L1236)
is not tested by any existing test (checked using code coverage and by
inserting an `abort`). The case marks type deduction as incomplete.
I suggest a new test to cover this case; it's specific to
`-mtriple=spirv64-amd-amdhsa`.
Commit: 5d051f628c61fcec3ef6d23ce09be169454d9f27
https://github.com/llvm/llvm-project/commit/5d051f628c61fcec3ef6d23ce09be169454d9f27
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
Log Message:
-----------
clang: Remove unnecessary isAMDGCN wrapper (#189640)
Commit: d5f7acdbc15fd15244bf6f3e4d4e3ea5a7bd2781
https://github.com/llvm/llvm-project/commit/d5f7acdbc15fd15244bf6f3e4d4e3ea5a7bd2781
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
Log Message:
-----------
[mlir][spirv] Add Cast/Rescale ops in TOSA Ext Inst Set (#189028)
This patch introduces the following operators:
spirv.Tosa.Cast
spirv.Tosa.Rescale
Also dialect and serialization round-trip tests have been added.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: a30a8e9474f75000d9746b5d02800d2e47903f44
https://github.com/llvm/llvm-project/commit/a30a8e9474f75000d9746b5d02800d2e47903f44
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/linear_modifier.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-simd-linear.mlir
Log Message:
-----------
Reland "[flang][OpenMP] Fix lowering of LINEAR iteration variables (#183794)" (#188851)
Linear iteration variables were being treated as private. This fixes
one of the issues reported in #170784.
The regression reported in #188536 occurred because
LinearClauseProcessor was rewriting all basic blocks whose names
contained a given substring, including those that were not part of the
translated SIMD region.
This didn't cause problems before because linear variables were always
privatized, which doesn't happen with this change.
The issue is fixed by rewriting only the basic blocks that correspond to
the omp.simd operation.
Commit: 26e67aeefaed0392fbb365335dd3cc7d8f1f459a
https://github.com/llvm/llvm-project/commit/26e67aeefaed0392fbb365335dd3cc7d8f1f459a
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/test/MC/AArch64/armv8.9a-prfm-slc.s
M llvm/test/MC/AArch64/basic-a64-instructions.s
M llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt
M llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
M llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
Log Message:
-----------
[AArch64] Always print the PRFM operation name (#182035)
When the encoding in the "Rt" field of the PRFM instruction maps to a
`<prfop>` value, the name of the prefetch operation should be printed
regardless of whether the associated feature (e.g. FEAT_PRFMSLC)
is available. If the feature is not available, the instruction is a nop.
All other encodings are printed as an immediate.
Commit: 76ed0ad3577e0c96406601d23552befb5a250c6a
https://github.com/llvm/llvm-project/commit/76ed0ad3577e0c96406601d23552befb5a250c6a
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/CodeView/LazyRandomTypeCollection.h
M llvm/include/llvm/DebugInfo/PDB/Native/TpiStream.h
M llvm/lib/DebugInfo/CodeView/LazyRandomTypeCollection.cpp
M llvm/lib/DebugInfo/PDB/Native/TpiStream.cpp
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
A llvm/unittests/DebugInfo/PDB/TpiStreamTest.cpp
Log Message:
-----------
[CodeView] Expose fallible type accessors in TpiStream (#188299)
`LazyRandomTypeCollection` already has fallible functions for
`getType(TypeIndex)` this exposes them in `TpiStream` and does a mini
cleanup in `LazyRandomTypeCollection`'s `GetType`.
Context: #186948 saw a crash in LLDB where we call `GetType` without
checking the type index before calling the method. In `GetType` we
called `error(std::move(EC))`, which ignores the error in release mode.
The cause was the type index `0x80000169` in an `S_LOCAL`.
We now do a soft fail in release mode - we already check the error, so
we might as well return an empty value.
Aside: The type index there feels really unusual, the type indices in
other records around the `S_LOCAL` were in a similar range. Almost looks
like some integer over-/underflow.
Commit: 5b010134abd44bfe7543f89bb636852a5fa09a3b
https://github.com/llvm/llvm-project/commit/5b010134abd44bfe7543f89bb636852a5fa09a3b
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/ADT/bit.h
Log Message:
-----------
[ADT] implement countl_zero_constexpr and reuse it for countl_zero & bit_width_constexpr (#189111)
Implement constant evaluated `countl_zero_constexpr` similar to
`countr_zero_constexpr` and use it for `countl_zero` and
`bit_width_constexpr`.
Also, `countl_zero` now use fast intrinsic path for `uint8/uint16` types
(use `sizeof(T) <= 4` instead `sizeof(T) == 4`).
Commit: 74e84c0cf5f1f0df9671090c2e73714f6730ec16
https://github.com/llvm/llvm-project/commit/74e84c0cf5f1f0df9671090c2e73714f6730ec16
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGException.cpp
A clang/test/CodeGen/async-exceptions.c
Log Message:
-----------
[Clang] Fix getTerminator() use for -fasync-exceptions (#189644)
Commit: 027475071e73bb72f874652c90f91f4ec483d578
https://github.com/llvm/llvm-project/commit/027475071e73bb72f874652c90f91f4ec483d578
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Support/APInt.cpp
M llvm/unittests/ADT/APIntTest.cpp
Log Message:
-----------
[Support][APint] Fix APInt::urem for edge case. Use `U.pVal[0] instead getZExtValue() (#189441)
Use `U.pVal[0]` instead of `getZExtValue()` in the
`APInt::urem(uint64_t)` power-of-two fast path. `getZExtValue()`
requires the entire APInt to fit into 64 bits, but this code can be
reached for multi-word values, which may trigger assertions
(`assert(getActiveBits() <= 64 && "Too many bits for uint64_t")`) or
otherwise mis-handle wide integers.
Also add simple test for edge cases.
Improvement for https://github.com/llvm/llvm-project/pull/189245
Commit: 935cf7ec2261a0d4c753f0efbbfc9ef3c9f0c409
https://github.com/llvm/llvm-project/commit/935cf7ec2261a0d4c753f0efbbfc9ef3c9f0c409
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/unittests/ADT/APIntTest.cpp
Log Message:
-----------
[Support][APint] Added more unit tests for clearBits / clearBitsSlowCase (#189434)
Commit: 33fc8fca62449130ae98ebbb95f1c33d74ee180d
https://github.com/llvm/llvm-project/commit/33fc8fca62449130ae98ebbb95f1c33d74ee180d
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Support/APInt.cpp
Log Message:
-----------
[Support][APint] Optimize fallback case in APInt::reverseBits (#189291)
Commit: 0ef10d62d756e15e4e49e0603da286bd144e88b7
https://github.com/llvm/llvm-project/commit/0ef10d62d756e15e4e49e0603da286bd144e88b7
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll
Log Message:
-----------
[SPIR-V] Fix OpCooperativeMatrixLengthKHR operand type (#189630)
related to #188703
Commit: d08ebbe8eba1dd2453a00ae0a0a6bd04b0d88d51
https://github.com/llvm/llvm-project/commit/d08ebbe8eba1dd2453a00ae0a0a6bd04b0d88d51
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A clang/include/clang/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphSummary.h
M clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
M clang/lib/Driver/CMakeLists.txt
M clang/lib/FrontendTool/CMakeLists.txt
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractor.cpp
M clang/tools/clang-ssaf-format/CMakeLists.txt
M clang/tools/clang-ssaf-linker/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/CMakeLists.txt
M clang/unittests/ScalableStaticAnalysisFramework/Registries/SummaryExtractorRegistryTest.cpp
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/FrontendTool/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysisFramework/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysisFramework/BUILD.gn
Log Message:
-----------
[clang][ssaf] Add CallGraph summary and extractor (#188753)
rdar://170258016
Commit: e3b6426d737295c8d079c348235a40c94269d0d2
https://github.com/llvm/llvm-project/commit/e3b6426d737295c8d079c348235a40c94269d0d2
Author: Sam Parker <sam.parker at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
Log Message:
-----------
[NFC][WebAssembly] CodeGen test (#189626)
Commit: 14311077f809afa494ec73d160c6aa719fbea9f2
https://github.com/llvm/llvm-project/commit/14311077f809afa494ec73d160c6aa719fbea9f2
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll
Log Message:
-----------
[LLVM][ConstantFold] Ensure scalar type is queried when determining denormal mode. (#189600)
Fixes https://github.com/llvm/llvm-project/issues/187928
Commit: 9f8fc658abf8548029d2e613279f17fd314fcc74
https://github.com/llvm/llvm-project/commit/9f8fc658abf8548029d2e613279f17fd314fcc74
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
Log Message:
-----------
[Passes] Remove some optsize checks (#189369)
LibCallsShrinkWrapPass and PGOMemOPSizeOpt already check for optsize
attributes internally, so there is no need to handle this in the pass
pipeline.
The context here is that I'd like to make the pass pipeline completely
independent of Os/Oz so that we know for sure that function-level
optsize/minsize attributes behave identically to the pipeline-level
option.
Commit: d5d32d3052d1156947d88787ac425a94a593c622
https://github.com/llvm/llvm-project/commit/d5d32d3052d1156947d88787ac425a94a593c622
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/TargetParser/Triple.cpp
Log Message:
-----------
Triple: Expose parseArch as a public method (#189648)
Clang has some code which is doing a direct arch name
string compare which should really be recognizing anything
usable as a triple architecture. It makes more sense to
directly parse the architecture than to construct a temporary
triple just to see what the parsed arch is.
For some reason the existing public parsing method is
getArchTypeForLLVMName. I'm not fully sure what the difference
between the 2 is supposed to be. My current guess is
getArchTypeForLLVMName is only supposed to handle the
canonical architecture name.
Commit: 10ea3deb8702af4a744f92d411513a6f3a5d6dfd
https://github.com/llvm/llvm-project/commit/10ea3deb8702af4a744f92d411513a6f3a5d6dfd
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/raise.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/raise.cpp
Log Message:
-----------
[libc][syscall] lift raise to syscall wrapper (#189507)
Commit: 7d0bf88581ff03feb3d9dcef6548cf22cd6d1dd9
https://github.com/llvm/llvm-project/commit/7d0bf88581ff03feb3d9dcef6548cf22cd6d1dd9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
Log Message:
-----------
OpenMP: Match all Triple recognized arch aliases (#189649)
This liberalizes match(device = {arch(some_arch)} to recognize
other names for some_arch.
Previously this compared against getArchTypeForLLVMName, which
only matches a subset of names (which seems to be the canonical
architecture names). There was a special case hack for "x86_64",
which is one of the "x86-64" aliases accepted by parseArch, but is
not the canonical architecture name.
Commit: 46dd9d6f522d3007b0c5fe121805e09fc58fe012
https://github.com/llvm/llvm-project/commit/46dd9d6f522d3007b0c5fe121805e09fc58fe012
Author: natanelh-mobileye <natanelh at mobileye.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
Log Message:
-----------
[SDAG][abd] Combine abd of small types (#181538)
It is beneficial to combine abd of illegal, small types (types that get promoted to wider scalar size).
Commit: e7483770c71dc502462fa717623b808161b47ad6
https://github.com/llvm/llvm-project/commit/e7483770c71dc502462fa717623b808161b47ad6
Author: John Harrison <harjohn at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Correct attaching by program basename. (#188886)
Fixes an issue where attaching by program would fail if the program name
was a partial name (e.g. "foobar" instead of "/path/to/foobar").
We failed to create the target which caused the attach to fail. Now we
fallback to the dummy target and update to the real target after the
attach completes.
Here is an example launch configuration that fail:
```
{
"type": "lldb-dap",
"name": "Attach (wait)",
"request": "attach",
"program": "foobar",
"waitFor": true
},
```
Commit: 5a89da7d13e1e9e428db35c28e49c31df8f10996
https://github.com/llvm/llvm-project/commit/5a89da7d13e1e9e428db35c28e49c31df8f10996
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/siginfo_t.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/sigaction.cpp
M libc/src/signal/linux/signal_utils.h
Log Message:
-----------
[libc][signal] cleanup sigaction implementation (#189512)
Commit: aca71454e4f9b970fc3e4065456f277202030ae0
https://github.com/llvm/llvm-project/commit/aca71454e4f9b970fc3e4065456f277202030ae0
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/test/MC/AArch64/armv9.6a-pcdphint.s
Log Message:
-----------
[AArch64][llvm] Fix encoding for `stshh` instruction (#189588)
The encoding for `stshh` was incorrect, and has been fixed. This
has been checked against the Arm ARM.
Commit: efbd59631091fdf4ed3c0f33343ccd63dd896e00
https://github.com/llvm/llvm-project/commit/efbd59631091fdf4ed3c0f33343ccd63dd896e00
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[AMDGPU][NFCI] CustomOperand to have a default type (#189584)
Most of the time, we should not need to care about the type at all, so
having it as a mandatory parameter confuses people and invites using
i1/i8/i16 where not necessary.
Commit: acc609bc296e9ddc3c1aff188a4411bc19802043
https://github.com/llvm/llvm-project/commit/acc609bc296e9ddc3c1aff188a4411bc19802043
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/23.rst
Log Message:
-----------
[libc++][NFC] Removed an EOL stray white space in Release Notes (#189654)
Commit: bb55c4bcfe30146b50def8bf21617647d6b0167a
https://github.com/llvm/llvm-project/commit/bb55c4bcfe30146b50def8bf21617647d6b0167a
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/test/CIR/CodeGen/nonzeroinit-struct.cpp
A clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
M clang/tools/cir-opt/cir-opt.cpp
M clang/utils/TableGen/CIRLoweringEmitter.cpp
Log Message:
-----------
[CIR] Implement member-pointer members lowering/CXX ABI lowering (#187327)
Record types with a member pointer as a member require quite a bit of
work to get to function properly. First, we have to wire them through
the AST->CIR lowering to make sure we properly represent them, and
represent them when they're zero initializable. We also have to properly
initialize elements when we're NOT zero initializable.
More importantly, we have to implement the CXXABILowering of record
types. Before this patch, we just assumed that all RecordTypes were
legal, since we didn't have the above lowering. A vast majority of this
patch is around getting RecordTypes to lower properly. There isn't
really a good way to test this without the FE changes, so it wasn't
split off.
We accomplish this in 2 phases: First, we transform each individual
record type along the way, giving it a new cxx-abi specific name. We
have to ensure that recursive evaluation works correctly, so we pulled
the solution from the LLVM-IR dialect for that. Secondly, we rename all
of the RecordType's back. This is safe only after we have 'removed' all
references to the untransformed RecordType due to the way RecordStorage
works, however it'll assert if we get this wrong. We do this second
stage to minimize the impact on tests as well as the IR: otherwise EVERY
RecordType would have their names changed. In addition to massive test
changes, this would be an ugly change everywhere.
One additional concern with RecordType lowering, is that it makes most
of RecordTypes potentially 'illegal'. Thus, any attribute that
'references' a record type is required to be transformed as well, so
this patch implements attribute legalization and transformation.
This quite a few NYIs around lowering of these, though most are probably
not really accessible.
Commit: 2c5af14e9faaf384e2a33544a6e506b928b5211e
https://github.com/llvm/llvm-project/commit/2c5af14e9faaf384e2a33544a6e506b928b5211e
Author: Sam Parker <sam.parker at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
Log Message:
-----------
[NFC][WebAssembly] More codegen tests (#189671)
Commit: 09c54a8f7afcd30c83862ab2792eacdb53c77a8f
https://github.com/llvm/llvm-project/commit/09c54a8f7afcd30c83862ab2792eacdb53c77a8f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/TargetAndABI.h
M mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
M mlir/test/Conversion/SCFToSPIRV/for.mlir
M mlir/test/Conversion/SCFToSPIRV/while.mlir
Log Message:
-----------
[mlir][SPIR-V] Support spirv.loop_control attribute on scf.for and scf.while (#189392)
Propagate the `spirv.loop_control` attribute from `scf.for` and
`scf.while` operations to the generated `spirv.mlir.loop` during
SCFToSPIRV conversion
Commit: ff4e229f8c758bc547d8bb42dbd9209306603f94
https://github.com/llvm/llvm-project/commit/ff4e229f8c758bc547d8bb42dbd9209306603f94
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/predicated-reverse-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
Revert "[VPlan] Extract reverse mask from reverse accesses" (#189637)
Reverts llvm/llvm-project#155579
Assertion added triggers on some buildbots
clang:
/home/tcwg-buildbot/worker/clang-aarch64-sve2-vla/llvm/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp:3840:
virtual InstructionCost
llvm::VPWidenMemoryRecipe::computeCost(ElementCount, VPCostContext &)
const: Assertion `!IsReverse() && "Inconsecutive memory access should
not have reverse order"' failed.
PLEASE submit a bug report to
https://github.com/llvm/llvm-project/issues/ and include the crash
backtrace, preprocessed source, and associated run script.
Stack dump:
0. Program arguments:
/home/tcwg-buildbot/worker/clang-aarch64-sve2-vla/stage1.install/bin/clang
-DNDEBUG -mcpu=neoverse-v2 -mllvm -scalable-vectorization=preferred -O3
-std=gnu17 -fcommon -Wno-error=incompatible-pointer-types -MD -MT
MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/CMakeFiles/timberwolfmc.dir/finalpin.c.o
-MF CMakeFiles/timberwolfmc.dir/finalpin.c.o.d -o
CMakeFiles/timberwolfmc.dir/finalpin.c.o -c
/home/tcwg-buildbot/worker/clang-aarch64-sve2-vla/test/test-suite/MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/finalpin.c
Commit: 38c0f53a14f41989e7156698e779bb15a3fd95c7
https://github.com/llvm/llvm-project/commit/38c0f53a14f41989e7156698e779bb15a3fd95c7
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
Log Message:
-----------
[SLP][NFC] Add a test for incorrect fma-conversion for fmuls with multi uses
Commit: e891812cacde0c6561b73173d24d37309aeb93dc
https://github.com/llvm/llvm-project/commit/e891812cacde0c6561b73173d24d37309aeb93dc
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_minimum, vp_maximum (#189550)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off two intrinsics from #179622.
Commit: 67c34294a6b3e161a84ed4697c326d04d651d7ff
https://github.com/llvm/llvm-project/commit/67c34294a6b3e161a84ed4697c326d04d651d7ff
Author: AidinT <at.aidin at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/docs/Interfaces.md
M mlir/docs/Tools/mlir-reduce.md
Log Message:
-----------
[mlir][docs] dialect interfaces and mlir reduce documentation fix (#189258)
Two modifications:
1. Reflect newly added dialect interface methods in the documentation
2. Remove the bug in the `MLIR Reduce` documentation
Commit: b66d98afb9e09864f5857ab17ec2e6ee344ee31d
https://github.com/llvm/llvm-project/commit/b66d98afb9e09864f5857ab17ec2e6ee344ee31d
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
Log Message:
-----------
[lldb][bytecode] Improvements to compiler generated Swift (#189425)
Following feedback from @benrimmington in
https://github.com/apple/swift-collections/pull/607, this changes the
following:
1. Uses `objectFormat()` compiler conditional instead of `os()` (see
"Cross-platform object file format support" in
[SE-0492](https://github.com/swiftlang/swift-evolution/blob/main/proposals/0492-section-control.md#cross-platform-object-file-format-support))
2. Uses a raw identifier for the generated Swift symbol name, instead of
an escaped name (see
[SE-0451](https://github.com/swiftlang/swift-evolution/blob/main/proposals/0451-escaped-identifiers.md))
Commit: 720b8ea893da2168121622bbfb536a78b35ffa32
https://github.com/llvm/llvm-project/commit/720b8ea893da2168121622bbfb536a78b35ffa32
Author: David Truby <david.truby at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/CMakeLists.txt
M llvm/runtimes/CMakeLists.txt
M openmp/runtime/CMakeLists.txt
A openmp/runtime/cmake/arm64x.cmake
Log Message:
-----------
[openmp] Add support for Arm64X to libomp (#176157)
This patch allows building libomp.dll and libomp.lib as Arm64X binaries
containing both arm64 and arm64ec code and useable from applications
compiled for both architectures.
Commit: 4087c5f30d133087b7706db80e27b2d35dd334af
https://github.com/llvm/llvm-project/commit/4087c5f30d133087b7706db80e27b2d35dd334af
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
Log Message:
-----------
[lldb][bytecode] Add append mode for compiler output (#189693)
Commit: 6477f3aa166b0af1677cd36300097f088bdff510
https://github.com/llvm/llvm-project/commit/6477f3aa166b0af1677cd36300097f088bdff510
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
Log Message:
-----------
[mlir][ArithToSPIRV] Fix invalid SPIRV and crashes when lowering integer ops on i1 (#189239)
Several arith integer operations on i1 / vector<Ni1> types were either
crashing or producing invalid SPIRV. The i1 type maps to spirv.bool in
SPIRV, not to a SPIRV integer — so standard integer SPIRV ops
(spirv.IAdd, spirv.UDiv, spirv.GLSMax, etc.) are illegal on it.
Add dedicated boolean patterns for all affected arith integer ops, each
with benefit=2 to take priority over the generic elementwise patterns.
The semantics for i1 follow from treating true = 1 / false = 0 with
two's complement wrapping:
- addi, subi → spirv.LogicalNotEqual (XOR on bits)
- muli, divui, divsi → spirv.LogicalAnd
- remui, remsi, shli, shrui → spirv.LogicalAnd(a, spirv.LogicalNot(b))
(a & ~b)
- shrsi → identity (arithmetic right shift of a 1-bit signed value is
always the input)
- maxui, minsi → spirv.LogicalOr (unsigned max / signed min treats true
as larger)
- maxsi, minui → spirv.LogicalAnd (signed max / unsigned min treats
false as larger)
Fixes #61162
Assisted-by: Claude Code
Commit: 728de262fcc0320b7dabf2a1ac52940b4fe1f7c0
https://github.com/llvm/llvm-project/commit/728de262fcc0320b7dabf2a1ac52940b4fe1f7c0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/neon-abd.ll
Log Message:
-----------
[NFC][AArch64] neon-abd.ll - remove unnecessary entry labels to reduce diff size in #186659 (#189690)
Commit: c98e4386fc45e35ceacb083f6677622f54f656a9
https://github.com/llvm/llvm-project/commit/c98e4386fc45e35ceacb083f6677622f54f656a9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
[Bazel] Port b544ad57039588d0fe24a1f512202cc5c0bd3a67
Commit: fce3a66f5e2f247890c57ac01a2c9847358c0f27
https://github.com/llvm/llvm-project/commit/fce3a66f5e2f247890c57ac01a2c9847358c0f27
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/mod-file.h
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/Inputs/modfile84.f90
A flang/test/Semantics/modfile84.f90
Log Message:
-----------
[flang] Preserve UseErrorDetails in module files (#189423)
When the same name is USE-associated with two or more distinct ultimate
symbols, and they are not both generic procedure interfaces, it's not an
error unless the name is actually referenced in the scope. But when the
scope is itself a module or submodule, our module files don't preserve
the error for later diagnosis -- instead, the UseErrorDetails symbol
that serves as a "poison pill" in case of later use is discarded when
the module file is generated. So emit additional USE statements to the
module file so that a UseErrorDetails symbol is created anew when the
module file is read.
Commit: 7ff0dc4b9fdee840de0901e969ea11880a28d433
https://github.com/llvm/llvm-project/commit/7ff0dc4b9fdee840de0901e969ea11880a28d433
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] Add iterator support to depend clause (#189090)
Extend the depend clause to support `!omp.iterated<Ty>` handles
alongside plain depend vars, so the IR can represent both forms.
Assisted with copilot
This is part of feature work for
https://github.com/llvm/llvm-project/issues/188061
Commit: 85d7927c08b5563f050d56d2bf88a6c152489c41
https://github.com/llvm/llvm-project/commit/85d7927c08b5563f050d56d2bf88a6c152489c41
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
R flang/test/Lower/OpenMP/Todo/depend-clause.f90
A flang/test/Lower/OpenMP/depend-iterator.f90
Log Message:
-----------
[Flang][OpenMP] Support iterator modifier in depend clause (#189412)
Lower the iterator modifier on depend clause to omp.iterator. Iterated
depend objects emit `!omp.iterated<!llvm.ptr>` by using
`getDataOperandBaseAddr` to generate base address and
`genIteratorCoordinate` to get the addr+offset. The non-iterated objects
in depend clause still use existing lowering path.
This patch is part of feature work for #188061.
Assisted with copilot.
Commit: 9e77a4593526a04cd2308a724039e94d8fbe9445
https://github.com/llvm/llvm-project/commit/9e77a4593526a04cd2308a724039e94d8fbe9445
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[mlir][OpenMP][NFC] Refactor fillAffinityIteratorLoop (#189418)
Extract affinity-specific logic from fillAffinityIteratorLoop into a
callback so that the iterator loop codegen logic can be shared with
other clauses such as depend clause and target clause.
Commit: 65720adc15da80a65817a2bed3a506cf099d2aa7
https://github.com/llvm/llvm-project/commit/65720adc15da80a65817a2bed3a506cf099d2aa7
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
Log Message:
-----------
[MLIR][XeGPU] Switch to the new sg to wi pass (#188627)
This PR has changes required to switch the pipeline to use the new sg to
wi pass.
Commit: d47190223930ce8379afa2a183ed9c407414b1a3
https://github.com/llvm/llvm-project/commit/d47190223930ce8379afa2a183ed9c407414b1a3
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
Log Message:
-----------
[CIR] Implement reference type of record ptr in initCatchParam (#185214)
Implement the reference type of record ptr in initCatchParam
Commit: 0e0a0458ce3aeccb27c677b15abe02e72cf18a50
https://github.com/llvm/llvm-project/commit/0e0a0458ce3aeccb27c677b15abe02e72cf18a50
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[Bazel] Port d08ebbe8eba1dd2453a00ae0a0a6bd04b0d88d51
Commit: c4e6cf0abff628f9c018428e0d4beed8788efdf9
https://github.com/llvm/llvm-project/commit/c4e6cf0abff628f9c018428e0d4beed8788efdf9
Author: Zhen Wang <37195552+wangzpgi at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang-rt/lib/cuda/registration.cpp
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-device-address.mlir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[flang][cuda] Support non-allocatable module-level managed variables (#188526)
Add support for non-allocatable module-level CUDA managed variables
using pointer indirection through a companion global in
__nv_managed_data__. The CUDA runtime populates this pointer with the
unified memory address via __cudaRegisterManagedVar and
__cudaInitModule.
1. Create a .managed.ptr companion global in the __nv_managed_data__
section and register it with _FortranACUFRegisterManagedVariable
(CUFAddConstructor.cpp)
2. Call __cudaInitModule after registration to populate the managed
pointer (registration.cpp)
3. Annotate managed globals in gpu.module with nvvm.managed for PTX
.attribute(.managed) generation (cuda-code-gen.mlir)
4. Suppress cuf.data_transfer for assignments to/from non-allocatable
module managed variables, since cudaMemcpy would target the shadow
address rather than the actual unified memory (tools.h)
5. Preserve cuf.data_transfer for device_var = managed_var assignments
where explicit transfer is still required
Commit: 9c64cb6dca0693b8ae873ba6e40025a554d15c39
https://github.com/llvm/llvm-project/commit/9c64cb6dca0693b8ae873ba6e40025a554d15c39
Author: Medha Tiwari <medhavns1 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/LowerEmuTLS.cpp
M llvm/test/CodeGen/AArch64/emutls.ll
A llvm/test/CodeGen/ARM/emutls-alignment.ll
Log Message:
-----------
Fix emulated TLS alignment for large variables (#171037)
Fix emulated TLS alignment for larger variables (>= 32 bytes) to use
preferred alignment.
Fixes #167219
Commit: 8a5e029072f75d6097031f9f102483881027a392
https://github.com/llvm/llvm-project/commit/8a5e029072f75d6097031f9f102483881027a392
Author: Steven Perron <stevenperron at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
Log Message:
-----------
[HLSL] Fix test writing to an output files (#189684)
The Texture2D-mips-errors.hlsl test was writing it output to a file, but
that is not needed.
Commit: f74f32b529c35531198621fd104cde5d2cf77e0c
https://github.com/llvm/llvm-project/commit/f74f32b529c35531198621fd104cde5d2cf77e0c
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
M lldb/test/Shell/ScriptInterpreter/Python/python-bytecode.test
Log Message:
-----------
[lldb][bytecode] Remove "Generated with" comment (#189704)
In most cases, some other script/tool will call the compiler, and it's
the invocation of that script that ought to be documented in the output.
Commit: e04f8bb754bb783279822cb77ff3505c073b7b1d
https://github.com/llvm/llvm-project/commit/e04f8bb754bb783279822cb77ff3505c073b7b1d
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGenOpenMP/omp-module-attrs.c
Log Message:
-----------
[CIR] Add OMP module attributes to MLIR module (#189394)
This patch adds OpenMP attributes to the MLIR module op used to
communicate various settings e.g. thread options and offloading
information.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 293623ce99d4d6819378311c1506c5ab08d1d860
https://github.com/llvm/llvm-project/commit/293623ce99d4d6819378311c1506c5ab08d1d860
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/CodeGen/X86/known-fpclass.ll
Log Message:
-----------
[X86] Add initial computeKnownFPClass test case (#189707)
Example test case for #137943 / #189583 / #189585 - failure to recognise ISD::SQRT is never neginf
Commit: ec45f95799f39f92ec22828abb9be9cd80bd0f1f
https://github.com/llvm/llvm-project/commit/ec45f95799f39f92ec22828abb9be9cd80bd0f1f
Author: lntue <lntue at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/src/__support/CMakeLists.txt
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/setjmp/aarch64/CMakeLists.txt
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdlib/CMakeLists.txt
Log Message:
-----------
[libc] Add libc_set_definition and libc_add_definition to properly pass definitions to MSVC. (#189664)
Commit: 42d5fdd47fc62169671f84cf8896c80e29a1cb15
https://github.com/llvm/llvm-project/commit/42d5fdd47fc62169671f84cf8896c80e29a1cb15
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/X86/addcarry.ll
M llvm/test/CodeGen/X86/subcarry.ll
Log Message:
-----------
[X86] Add i686 32-bit coverage to addcarry.ll/subcarry.ll tests (#189713)
Inspired by #189018
Commit: 28efe7b554f8d9fbd2405542c27919a612d8288e
https://github.com/llvm/llvm-project/commit/28efe7b554f8d9fbd2405542c27919a612d8288e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
Log Message:
-----------
OpenMP: Reimplement getOffloadArch (#189561)
This function made no sense at all. It was scanning through
the feature map looking for something that parsed as an OffloadArch.
Directly compute the arch from the target device.
I don't know why there isn't just an OffloadArch in TargetOpts,
this shouldn't really require parsing.
Commit: be9b162a795ca362e9dceb945ed2e2618de8cf18
https://github.com/llvm/llvm-project/commit/be9b162a795ca362e9dceb945ed2e2618de8cf18
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
Log Message:
-----------
[LoadStoreVectorizer] Add tests for mixed-type vectorization (#189716)
Precommitting this test to reflect impact of the mixed-type
vectorization PR #177908. NFC.
Commit: 5c71351cf79471845aaa94fff187b9c9d0ac145f
https://github.com/llvm/llvm-project/commit/5c71351cf79471845aaa94fff187b9c9d0ac145f
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/source/Core/Module.cpp
Log Message:
-----------
[lldb][Module] Add logging when script import fails (#189695)
We already log the import attempt. This patch logs the failure to load
the script since otherwise the log may be misleading. Didn't think it
was worth adding a test-case for this.
Commit: 07893e30f4a64a176601fe2ab1e2d327e19dd1e1
https://github.com/llvm/llvm-project/commit/07893e30f4a64a176601fe2ab1e2d327e19dd1e1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV] Fix typo STD_RISCVPackedShift->SDT_RISCVPackedShift. NFC (#189678)
Commit: 49dbeca38d8faeef42d7cb03db649fbfb4c195c4
https://github.com/llvm/llvm-project/commit/49dbeca38d8faeef42d7cb03db649fbfb4c195c4
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
A clang/test/CIR/CodeGen/return-in-if-with-cleanups.cpp
Log Message:
-----------
[CIR] Fix missing terminators in regions with cleanup (#187604)
When a cleanup scope was created within an if operation's then or else
region and the source scope ended with a return, we would fail to
terminate the region following the cleanup scope, which surrounded the
return operation, resulting in an MLIR verification error. This change
forces the addition of terminators in the if's then and else regions.
Commit: a7438859265548c8443436d9c0c996338976ad85
https://github.com/llvm/llvm-project/commit/a7438859265548c8443436d9c0c996338976ad85
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/test/CIR/CodeGen/throws.cpp
Log Message:
-----------
[CIR] Add support for throwing destructed type (#188644)
This adds handling for throwing an object of a type that has a
non-trivial destructor.
Commit: ccfba7736f2d39434ae768ae9c9c0165b1959c4b
https://github.com/llvm/llvm-project/commit/ccfba7736f2d39434ae768ae9c9c0165b1959c4b
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
A clang/test/CIR/CodeGen/delegating-ctor-exceptions.cpp
Log Message:
-----------
[CIR] Add support for cleanups after calling a delegating ctor (#189513)
This adds support for calling the destructor of types with a non-trivial
destructor if the initialization throws an exception after a delegating
constructor has been called.
Commit: 282fb05292cab555010a645cef88d62c846511d4
https://github.com/llvm/llvm-project/commit/282fb05292cab555010a645cef88d62c846511d4
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/Support/Alignment.h
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/LLVMContextImpl.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Metadata.cpp
Log Message:
-----------
[IR] Store Metadata attachments in vector (#189551)
Metadata is accessed rather often, so store metadata attachments in a
vector indexed by a number instead of a map from Value*; inside the
vector, the metadata attachments form a linked list. Instruction and
GlobalObject store the first metadata attachment index directly. Care is
taken that the offset in the structures is identical.
In addition to substantial performance improvements, this also leads to
a measurable reduction in memory usage -- several instructions have
metadata in debug builds (debug metadata) and release builds (primarily
TBAA), causing the hash table to become quite large.
In Instruction, this uses 4 padding bytes (it might be debatable whether
this is the best use for this space); GlobalObject grows by 4 bytes.
However, should we want grow Instruction by 8 bytes in the future, the
additionally used memory will be ~similar to the memory saved here, so
we could do so without causing a release-to-release memory regression.
This also makes the HasMetadata bit redundant, cleanup will follow
separately -- this is a bit annoying, because this should be inline, but
Value can't access subclass members.
Commit: 9e6968b502bc75803238c10a234e935464142cc1
https://github.com/llvm/llvm-project/commit/9e6968b502bc75803238c10a234e935464142cc1
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
Log Message:
-----------
[CIR][NFC] Add test for catch with MemberPointer type (#185217)
Add test for catch with MemberPointer type
Commit: af6521fb3a36149cd69d83bfdf87ed26e59a14a2
https://github.com/llvm/llvm-project/commit/af6521fb3a36149cd69d83bfdf87ed26e59a14a2
Author: Srividya Sundaram <srividya.sundaram at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/include/clang/Driver/SyclInstallationDetector.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/SYCL.cpp
A clang/test/Driver/Inputs/SYCL/libLLVMSYCL.ll
R clang/test/Driver/Inputs/SYCL/libsycl.ll
M clang/test/Driver/link-device-code.test
M clang/test/Driver/sycl-offload-jit.cpp
Log Message:
-----------
[Driver] Update SYCL runtime library name and path for target-specific directories (#189053)
This patch updates the Clang driver to support the renamed SYCL runtime
library (libsycl.so → libLLVMSYCL.so) and its new location in
target-specific directories. These changes align with PR
#[188770](https://github.com/llvm/llvm-project/pull/188770), which
standardizes the SYCL runtime library naming and directory structure to
match other LLVM runtime libraries.
**Changes**
**Library Naming**
- **Old**: libsycl.so
- **New**: libLLVMSYCL.so
**Directory Structure**
Both build and install directories now use target-specific
subdirectories:
- **Old:** lib/libsycl.so
- **New:** lib/target-triple/libLLVMSYCL.so
For example, on x86_64-unknown-linux-gnu:
- **Old**: build/lib/libsycl.so → install/lib/libsycl.so
- **New**: build/lib/x86_64-unknown-linux-gnu/libLLVMSYCL.so →
install/lib/x86_64-unknown-linux-gnu/libLLVMSYCL.so
Commit: 899a78cbc4b9422e5567f2bfe4f563efed119756
https://github.com/llvm/llvm-project/commit/899a78cbc4b9422e5567f2bfe4f563efed119756
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M offload/test/offloading/target_critical_region.cpp
Log Message:
-----------
[offload][lit] Disable target_critical_region.cpp on Intel GPU (#189682)
Already disabled on other GPU platforms and sporadically failing on our
builder, so this test seems not be doing too hot.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 8af44b7867747cd6942688eef5c5324ef859428b
https://github.com/llvm/llvm-project/commit/8af44b7867747cd6942688eef5c5324ef859428b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
Log Message:
-----------
clang: Avoid some conversions of Triple to std::string (#189728)
Commit: c6d770fece415d7e8a55dcd495fd24862b3b1ca6
https://github.com/llvm/llvm-project/commit/c6d770fece415d7e8a55dcd495fd24862b3b1ca6
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/test/Transforms/FIRToMemRef/array-coor-slice-shift.mlir
Log Message:
-----------
[flang] Fix FIRToMemRef index computation for array_coor with slice and shape_shift (#189496)
Use shift instead of sliceLb only when the array_coor has an explicit
slice (indicesAreFortran case). When the slice comes from an embox,
the indices are 1-based section indices and must subtract 1.
Commit: 78c5d68029c0507123de28ecbe242490ee487b16
https://github.com/llvm/llvm-project/commit/78c5d68029c0507123de28ecbe242490ee487b16
Author: PiJoules <leonardchan at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_errors.cpp
M compiler-rt/lib/asan/asan_errors.h
M compiler-rt/lib/asan/asan_flags.inc
M compiler-rt/lib/asan/asan_report.cpp
M compiler-rt/lib/asan/asan_report.h
A compiler-rt/test/asan/TestCases/Linux/free_aligned_sized_mismatch.cpp
A compiler-rt/test/asan/TestCases/Linux/free_sized_mismatch.cpp
Log Message:
-----------
[asan] Add size/alignment checks for free_[aligned_]sized (#189216)
Historically, alignment and size weren't taken into account when freeing
allocations since `free` just takes a pointer. With `free_sized` and
`free_aligned_sized`, we can do these size and alignment checks in asan
now. This adds a new report type specifically for these functions.
Checking is hidden behind a new env flag `free_size_mismatch` which is
enabled by default, but downstream users can opt out of it.
The bulk of this PR was generated by gemini but thoroughly reviewed and
edited by me to the best of my ability.
Commit: 05dd3ae10cf26c22eba2e23ecb4e043b9c2576eb
https://github.com/llvm/llvm-project/commit/05dd3ae10cf26c22eba2e23ecb4e043b9c2576eb
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
A llvm/test/Transforms/InstCombine/printf-puts-not-emittable.ll
Log Message:
-----------
[SimplifyLibCalls] Prevent orphaned global string literals (#189502)
When `printf` is simplified to `puts`, `SimplifyLibCalls` would eagerly
create a global string for the argument before checking if `puts` is
emittable. If `puts` is not emittable (e.g. because it's an unextracted
bitcode libfunc), the optimization aborts, leaving an orphaned global
string in the module. Under expensive checks, this triggers a fatal
error because the function pass modified the module without reporting
it.
This change defers the creation of the global string until after
checking if `puts` is emittable.
(This PR was created with the help of Gemini CLI.)
Commit: da173bfbf5a0bcf9450b15998ba454f4a4fbf1f6
https://github.com/llvm/llvm-project/commit/da173bfbf5a0bcf9450b15998ba454f4a4fbf1f6
Author: Laxman Sole <lsole at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.h
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
Log Message:
-----------
[NVPTX] Do not emit .debug_pubnames and .debug_pubtypes for NVPTX backend (#187328)
This change adds a mechanism to stop emitting `.debug_pubname`,
`.debug_pubtypes` sections for a particular target.
This is particularly useful for cases where IR is generated by frontends
that do not explicitly disable these sections (as `Clang` does for
`NVPTX`), but still use `llc` for code generation.
Currently, only `NVPTX` uses this to disable these sections.
Commit: 6669fa5806c5fbe607abaa307cb06ce89dd972db
https://github.com/llvm/llvm-project/commit/6669fa5806c5fbe607abaa307cb06ce89dd972db
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
A llvm/test/CodeGen/SPIRV/function/variadics-lowering-builtin-substr-in-name.ll
M llvm/test/CodeGen/SPIRV/printf.ll
Log Message:
-----------
[SPIR-V] Don't lower builtin variadic functions (#188517)
In https://github.com/llvm/llvm-project/pull/178980 I tried to remove
the special handling for `printf`, but the fix was wrong, the pass
expects that `printf` abides by the variadic ABI (single buffer passed
in, args extracted by caller), which isn't how it works.
However the root issue is with any builtin, they are just replaced
directly with instructions, and the only place that could generate code
to honor the variadic ABI would bei in the SPIR-V backend, and it would
be pretty complicated for pretty much no benefit.
It's much simpler to teach the pass to skip certain functions, as we did
before, but this time skip all SPIR-V builtin.
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: de84be21ec500a201ede42bc74b51f2913fe8266
https://github.com/llvm/llvm-project/commit/de84be21ec500a201ede42bc74b51f2913fe8266
Author: Demetrius Kanios <demetrius at kanios.net>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
Log Message:
-----------
[WebAssembly][GlobalISel] `G_ADD` (and in-reg ext/trunc related) legalization & selection (#183694)
This PR enables `G_ADD` and immediate dependencies (relavent ext and
trunc related ops) to be fully legalized and selected.
The most important change made is getting the boilerplate for
RegBankSelect working.
Split from #157161.
Commit: bf76fa758247c712b1b4879e0f0b17b5450ff141
https://github.com/llvm/llvm-project/commit/bf76fa758247c712b1b4879e0f0b17b5450ff141
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
Log Message:
-----------
[AtomicExpandPass][NFC] Refactor processAtomicInstr to be more readable (#186547)
While working on
https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomicrmw/90134/5
I found this `processAtomicInstr` to be a little hard to read, with
casing on the instruction type all over the place. I think it reads
nicer to just case on the instruction type once.
Commit: 626f942073b93b427e1c41e22c297becaa7bb9ae
https://github.com/llvm/llvm-project/commit/626f942073b93b427e1c41e22c297becaa7bb9ae
Author: Alex Langford <alangford at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbutil.py
Log Message:
-----------
[lldb] Increase timeout on lldbutil.wait_for_file_on_target (#189471)
I've been tracking sporadic timeouts waiting for a file to appear on
macOS buildbots (and occasionally local development environments). I
believe I've tracked it down to a regression in process launch
performance in macOS.
What I noticed is that running multiple test suites simultaneously
almost always triggered these failures and that the tests were always
waiting on files created by the inferior. Increasing this timeout no
longer triggers the failures on my loaded machine locally.
This timeout moves from about 16 seconds of total wait time to about 127
seconds of total wait time. This may feel a bit extreme, but this is a
performance issue. While I was here, I cleaned up logging code I was
using to investigate the test failures.
rdar://172122213
Commit: cb32b8bffbf32fd7936808ad260764c28e3197db
https://github.com/llvm/llvm-project/commit/cb32b8bffbf32fd7936808ad260764c28e3197db
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
A llvm/test/Transforms/LoopUnroll/RISCV/runtime-unroll-max-trip-count.ll
M llvm/test/Transforms/LoopUnroll/debug.ll
M llvm/test/Transforms/LoopUnroll/runtime-small-upperbound.ll
Log Message:
-----------
[LoopUnrollPass] Don't pre-set `UP.Count` before legality checks in `computeUnrollCount()` (#185979)
We currently set `UP.Count` to `TripCount` and `MaxTripCount` prior to
full and upper bound unrolling, respectively. This was likely done to
ensure that calls to `UCE.getUnrolledLoopSize(UP)` use the appropriate
trip count. However, we can use `UCE.getUnrolledLoopSize(UP,
FullUnrollTripCount)` instead.
To prevent unintentional unrolling, we set `UP.Count = 0` when
early-exiting `computeUnrollCount()`. (Note: this does not occur
[here](https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1190-L1198).
This seems like a bug.)
We only perform early exits when evaluating runtime unrolling. At that
point, [we know `TripCount` is
false](https://github.com/justinfargnoli/llvm-project/blob/3fb31e7b06f6f6d08c7310506a2f363d198a6790/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1157-L1158),
and thus we could not have leaked `TripCount`. However, we [could've
leaked
`MaxTripCount`](https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1102-L1110).
It seems like:
https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1181-L1188
was supposed to handle this case. However:
- It uses `<` instead of `<=`. This breaks the existing convention
[[1]](https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L869)
[[2]](https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1103)
for how `UP.MaxUpperBound` is treated.
- It's ignored when a target sets `UP.Force = true`.
Thus:
- When `UP.Force == false`, we leak `MaxTripCount` into runtime
unrolling when `MaxTripCount && (UP.UpperBound || MaxOrZero) &&
MaxTripCount == UP.MaxUpperBound`
- When `UP.Force == true`, we leak `MaxTripCount` into runtime unrolling
when `MaxTripCount && (UP.UpperBound || MaxOrZero) && MaxTripCount <=
UP.MaxUpperBound`.
This PR:
- Uses `UCE.getUnrolledLoopSize(UP, FullUnrollTripCount)`
- Stops setting `TripCount` and `MaxTripCount` prior to calling
`shouldFullUnroll()`
- Removes the `UP.Count = 0` safeguards
- Swaps `<` with `<=`, to address the `UP.Force == false` case
- Adds a test to document the behavior change (no longer leaking
`MaxTripCount`) in the `UP.Force == true` case.
Commit: cd8a8e953adb6f7ef000d8f67be21cb362d6dc9c
https://github.com/llvm/llvm-project/commit/cd8a8e953adb6f7ef000d8f67be21cb362d6dc9c
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
Log Message:
-----------
[CIR] Add OpenMP and OpenACC dialect dependencies (#189726)
This patch adds dependencies on OpenMP and OpenACC dialects to prevent
link errors when compiling with shared libraries.
Commit: 284e5d79cdf292f4693ee835cbcbb6760ac63889
https://github.com/llvm/llvm-project/commit/284e5d79cdf292f4693ee835cbcbb6760ac63889
Author: Jacob Lambert <jacob.lambert at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/BinaryFormat/MsgPackDocument.h
M llvm/lib/BinaryFormat/MsgPackDocument.cpp
M llvm/unittests/BinaryFormat/MsgPackDocumentTest.cpp
Log Message:
-----------
[MsgPackDocument]: Fix DocNode comparison and add copyNode (#189436)
Fix two bugs in DocNode's comparison operators and add a new
Document::copyNode() method:
1. operator== was implemented via operator<, which hits llvm_unreachable
for Array/Map nodes. Implement operator== directly with recursive value
comparison for all node types.
2. operator< compared KindAndDoc pointers, causing cross-document nodes
of the same type and value to silently produce wrong results. Compare by
kind then by value instead.
3. Add Document::copyNode() for deep copying nodes between Documents
with independent memory ownership.
Commit: c97561ced12d8c7bed9f2fe07733a971247333c7
https://github.com/llvm/llvm-project/commit/c97561ced12d8c7bed9f2fe07733a971247333c7
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-kernel-pre16.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-non-extinst.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath.ll
Log Message:
-----------
[SPIR-V] Derive FPFastMathMode from nofpclass attributes on OpenCL builtins (#188984)
Commit: 6aa2e496489d6309611b3d3c1ec9d0efd6cc81dd
https://github.com/llvm/llvm-project/commit/6aa2e496489d6309611b3d3c1ec9d0efd6cc81dd
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseDeclCXX.cpp
A clang/test/Parser/decltype-gh188014.cpp
Log Message:
-----------
[clang][Parser] Fix an assertion during decltype error recovery with missing ; (#188123)
Fix an assertion failure in `ParseDecltypeSpecifier` when parsing
malformed expressions e.g. `decltype(union { ... )`.
When a class/union definition is missing a semicolon, clang's error
recovery may synthetically set the current token to `tok::semi` without
actually inserting it into the preprocessor's backtrack cache, see
https://github.com/llvm/llvm-project/blob/9096c9cda3df4d09c9c6e4efa1a07a232a9ac8f8/clang/lib/Parse/ParseDeclCXX.cpp#L1920-L1927
If `ParseDecltypeSpecifier` later encounters this synthetic semicolon
during its own error recovery, its attempts to revert the cache and
re-lex the tokens will lead to reading unexpected tokens from the
historical stream, failing the strict
`Tok.is(tok::semi)` assertion.
This patch removes this assertion, acknowledging that during invalid
parses and error recovery, the preprocessor's cache state may not
strictly align with the parser's simulated state.
Fixes: #188014
Commit: fd1a89163ab76c26cf3bfd2e822905cc55eeef97
https://github.com/llvm/llvm-project/commit/fd1a89163ab76c26cf3bfd2e822905cc55eeef97
Author: Florian Mayer <fmayer at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
Log Message:
-----------
[NFC] [clang] swap parameters to checkTargetOptions (#187608)
This is the correct order according to the function prototype.
This should be NFC, because for PCH, AllowCompatibleDifferences
is always false: it is only used in isAcceptableASTFile, which
calls readASTFileControlBlock, which explicitely passes false.
We explicitely pass in `nullptr` for Diag, so the incorrect error
message isn't printed.
Commit: f9ded0e30a24d5faf4c810888da1837b41cbe718
https://github.com/llvm/llvm-project/commit/f9ded0e30a24d5faf4c810888da1837b41cbe718
Author: Artemiy <notlebedev at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
A clang/test/CIR/IR/string-trailing-zeros.cir
Log Message:
-----------
[CIR] Fix incorrect ConstArrayAttr trailing_zeros parsing (#188742)
Closes #187699 .
Fix incorrect parsing of `ConstArrayAttr`. `parse` method incorrectly
used type of `elts` parameter as type of the whole array. This means
that when reading back text or bytecode clangir files attribute did not
have correct type and correct `trailingZerosNum`. Type was always of
inner `elts`, meaning smaller then actual type if any trailing zeros
were present and `trailingZerosNum` was always zero.
Commit: 0454de8b54f92b80a4993c1d59c485daa0c176f9
https://github.com/llvm/llvm-project/commit/0454de8b54f92b80a4993c1d59c485daa0c176f9
Author: Artem Gindinson <gindinson at roofline.ai>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
Log Message:
-----------
[mlir][Arith] Avoid sign overflow when narrowing signed operations (#189676)
Whether an arith operation can be truncated to a given bitwidth should
also depend on the sign semantics of the operation itself. Consider:
```
%input = /* upper bound > INT32_MAX, <= UINT32_MAX */ : index
%c0 = arith.constant 0 : index
%cmp = arith.cmpi sle, %input, %c0 : index
```
Previously, `checkTruncatability()` would correctly judge that only an
unsigned truncation could be legal, however the narrowing would still
proceed despite the fact that the `sle` predicate treated the MSB as the
sign.
Ensure that the sign is checked for signed comparison predicates and for
signed elementwise operations by enforcing a `CastKind::Signed`
restriction, whereby the narrowing patterns bail out on incompatible
input range/operation signedness.
**AI tooling usage disclaimer**
LIT tests were expanded from manual reproducer examples with LLM
assistance. Those additional test cases were verified to
regression-test, proofread and edited manually in accordance with the
"Human in the loop" policy. LLMs/generative tooling were not used for
implementation/documentation purposes.
---------
Signed-off-by: Artem Gindinson <gindinson at roofline.ai>
Co-authored-by: GPT 5.4 <codex at openai.com>
Commit: 3ed48bf648cb6d94d8385c336bc72aadcd59f4f2
https://github.com/llvm/llvm-project/commit/3ed48bf648cb6d94d8385c336bc72aadcd59f4f2
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang-rt/lib/cuda/registration.cpp
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-device-address.mlir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
Revert "[flang][cuda] Support non-allocatable module-level managed variables" (#189745)
Reverts llvm/llvm-project#188526
Commit: c1ebd2f1c07f1dc51df1c1a56891fe564cbadc19
https://github.com/llvm/llvm-project/commit/c1ebd2f1c07f1dc51df1c1a56891fe564cbadc19
Author: Samuel Thibault <samuel.thibault at ens-lyon.org>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/test/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Disable asan tests on GNU/Hurd (#169209)
Like OpenBSD, asan does not support GNU/Hurd yet.
Commit: f43ee18e988d923ef5529f1df3910bd2af09e825
https://github.com/llvm/llvm-project/commit/f43ee18e988d923ef5529f1df3910bd2af09e825
Author: cmtice <cmtice at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/StackFrame.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/source/ValueObject/ValueObject.cpp
Log Message:
-----------
[LLDB] Add allow_var_updates to DIL and CanUpdateVar to SetValueFromInteger (#186421)
In preparation for updating DIL to handle assignments, this adds a
member variable to the DIL Interpreter indicating whether or not
updating program variables is allowed. For invocations from the LLDB
command prompt (through "frame variable") we want to allow it, but from
other places we might not. Therefore we also add new StackFrame
ExpressionPathOption, eExpressionPathOptionsAllowVarUpdates, which we
add to calls from CommandObjectFrame, and which is checked in
GetValueForVariableExpressionPath. Finally, we also add a parameter,
can_update_vars, with a default value of true, to
ValueObject::SetValueFromInteger, as that will be the main function used
to by assignment in DIL.
Commit: 96fd2318ee27ffc67ab1c36d67a5d59f387ac33e
https://github.com/llvm/llvm-project/commit/96fd2318ee27ffc67ab1c36d67a5d59f387ac33e
Author: Vineet Kumar <173554+vntkmr at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/docs/C++style.md
Log Message:
-----------
[flang] Add guidelines for referencing the Fortran Standard (#188591)
In response to [[RFC] Qualifying syntax rule numbers with Fortran
standard version in
comments](https://discourse.llvm.org/t/rfc-qualifying-syntax-rule-numbers-with-fortran-standard-version-in-comments/90167)
this PR adds a section on guidelines for referencing the Fortran
Standard.
Commit: b813b0b4e485b0323b51071aca7a415b30c3aa6f
https://github.com/llvm/llvm-project/commit/b813b0b4e485b0323b51071aca7a415b30c3aa6f
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/IR/MemRef.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
Log Message:
-----------
[mlir][MemRef] Migrate memref dialect alias op folding to interface (#187168)
This PR adds code to FoldMemRefAliasOps / --fold-memref-alias-ops to use
the new IndexedMemoryAccessOpInterface and
IndexedMemCopyOpInterface and implement those operations for relevant
operations in the memref dialect.
This is a reordering of the changes planned in #177014 and #177016 to
make them more testable.
There are no behavior changes expected for how memref.load and
memref.store behave within the alias ops folding pass, though support
for new operations, like memref.prefetch, has been added.
Some error messages have been updated because certain laws of
memref.load/memref.store have been moved to IndexedAccessOpInterface.
Assisted-by: Claude 4.6 (helped deal with some of the boilerplate in the
rewrite patterns and with extracting the patch)
Commit: 6e82a24f4cc585c8b2f69b1ff2cbee443f367187
https://github.com/llvm/llvm-project/commit/6e82a24f4cc585c8b2f69b1ff2cbee443f367187
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
Log Message:
-----------
[RISCV][P-ext] Rename simm8_unsigned/simm10_unsigned used PLUI/PLI. NFC (#188808)
Replace unsigned with plui or pli_b to better indicate their usage.
Templatize the render function and rename it addSExtImm instead of
addSImm*Unsigned.
Commit: f2f54b6874a3f2b0635866953e43348b0a746029
https://github.com/llvm/llvm-project/commit/f2f54b6874a3f2b0635866953e43348b0a746029
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rv32p.ll
Log Message:
-----------
[RISCV][P-ext] Support i32 avgfloors/avgflooru on RV32. (#189736)
Commit: 911dc4139dce1999c72144a9656f65caffca555b
https://github.com/llvm/llvm-project/commit/911dc4139dce1999c72144a9656f65caffca555b
Author: PiJoules <leonardchan at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/test/asan/TestCases/Linux/free_aligned_sized_mismatch.cpp
Log Message:
-----------
[compiler-rt][asan] Forward fix for free_aligned_sized_mismatch.cpp (#189760)
Mark this test as UNSUPPORTED for android since android's libc doesn't
seem to support aligned_alloc.
Commit: d8e9e0af1cb6e08659f703697b44895e614a3a21
https://github.com/llvm/llvm-project/commit/d8e9e0af1cb6e08659f703697b44895e614a3a21
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/docs/SandboxVectorizer.md
A llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/PassRegistry.def
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizerPassBuilder.cpp
A llvm/test/Transforms/SandboxVectorizer/load_store_vec.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec][LoadStoreVec] Initial pass implementation (#188308)
This patch implements a new simple region pass that can vectorize
store-load chains.
Commit: b7dc4ff0abee9f5210ba225d6e3c83bac338eae3
https://github.com/llvm/llvm-project/commit/b7dc4ff0abee9f5210ba225d6e3c83bac338eae3
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[TargetLowering] Replace always true if with an assert. NFC (#189750)
We already returned for UADDSAT/USUBSAT leaving SADDSAT/SSUBSAT as the
only opcodes that can get here.
Commit: 89dec12692c7654455977932cf99d643e58b3157
https://github.com/llvm/llvm-project/commit/89dec12692c7654455977932cf99d643e58b3157
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/Platform.h
M lldb/source/Core/Module.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
M lldb/source/Target/Platform.cpp
M lldb/unittests/Platform/PlatformDarwinTest.cpp
M lldb/unittests/Platform/PlatformTest.cpp
Log Message:
-----------
[lldb][Platform] Handle LoadScriptFromSymFile per-module FileSpec (#189696)
This patch changes the `Platform::LocateXXX` to return a map from
`FileSpec` to `LoadScriptFromSymFile` enum.
This is needed for https://github.com/llvm/llvm-project/pull/188722,
where I intend to set `LoadScriptFromSymFile` per-module.
By default the `Platform::LocateXXX` set the value to whatever the
target's current `target.load-script-from-symbol-file` is set to. In
https://github.com/llvm/llvm-project/pull/188722 we'll allow overriding
this per-target setting on a per-module basis.
Drive-by:
* Added logging when we fail to load a script.
Commit: c9bc317d6dea4b5aef40c35a443cc3083aab65c7
https://github.com/llvm/llvm-project/commit/c9bc317d6dea4b5aef40c35a443cc3083aab65c7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rv32p.ll
Log Message:
-----------
[RISCV][P-ext] Support i32 ushlsat on RV32. (#189730)
We have a sshl instruction on RV32 in the 0.21 spec. Unfortunately,
we don't have a SSLLI instruction, but we can put a constant shift
amount in a register.
Commit: cdce9cd4a19f15b9a100b3aeb6b37a79395a0c53
https://github.com/llvm/llvm-project/commit/cdce9cd4a19f15b9a100b3aeb6b37a79395a0c53
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes b813b0b (#189759)
This fixes b813b0b4e485b0323b51071aca7a415b30c3aa6f.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: c19e28d854e22b336d7aad78b88946864cd6eb13
https://github.com/llvm/llvm-project/commit/c19e28d854e22b336d7aad78b88946864cd6eb13
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/test/CMakeLists.txt
M llvm/test/TableGen/intrinsic-arginfo-error.td
A llvm/test/TableGen/intrinsic-overload-dependent-type-validation.td
Log Message:
-----------
[NFC][LLVM] Simplify `TypeInfoGen` in Intrinsics.td (#189278)
Eliminate `MappingRIdx` by making it an identity function. Currently,
`MappingRIdx` is used to map the index of an `llvm_any*` type in an
intrinsic type signature to its overload index. Eliminating this mapping
means that dependent types in LLVM intrinsic definitions (like
`LLVMMatchType` and its subclasses) should use the overload index to
reference the overload type that it depends on (and not the index within
the llvm_any* subset of overloaded types).
See
https://discourse.llvm.org/t/rfc-simplifying-intrinsics-type-signature-iit-info-generation-encoding-in-intrinsicemitter-cpp/90383
Commit: 5d624b5b937ce0965efbd101defbad956d0f8e4d
https://github.com/llvm/llvm-project/commit/5d624b5b937ce0965efbd101defbad956d0f8e4d
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
A llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
Log Message:
-----------
[VPlan] Stop outerloop vectorization from vectorizing nonvector intrinsics (#185347)
In outer-loop VPlan, avoid emitting vector intrinsic calls for intrinsics
without a vector form. In VPRecipeBuilder, detect missing vector intrinsic
mapping and emit scalar handling instead of a vector call.
Also fix assertion when `llvm.pseudoprobe` in VPlan's native path is being
treated as a `WIDEN-INTRINSIC`.
Reproducer: https://godbolt.org/z/GsPYobvYs
Commit: c20e233020c43e87be08f36d0ca5287bb69ea9f4
https://github.com/llvm/llvm-project/commit/c20e233020c43e87be08f36d0ca5287bb69ea9f4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/constant-based-reductions.ll
Log Message:
-----------
[SLP] Replace TrackedToOrig DenseMap with parallel SmallVector in reduction
Replace the DenseMap<Value*, Value*> TrackedToOrig with a SmallVector<Value*>
indexed in parallel with Candidates. This avoids hash-table overhead for the
tracked-value-to-original-value mapping in horizontal reduction processing.
Fixes #189686
Commit: bf50489eeba2126c526c8d57f73448fa48429d3f
https://github.com/llvm/llvm-project/commit/bf50489eeba2126c526c8d57f73448fa48429d3f
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
A llvm/test/Transforms/SampleProfile/pseudo-probe-emit-macho.ll
Log Message:
-----------
[Psuedoprobe][MachO] Enable pseudo probes emission for MachO (#185758)
Enable pseudo probes emission for MachO. Due to the 16 character limit
of MachO segment and section, the file sections will be
`__PSEUDO_PROBE,__probes` and `__PSEUDO_PROBE,__probe_descs`.
Commit: 3f2a9c6f5486e4202ec01e61fbef0e7d094e2371
https://github.com/llvm/llvm-project/commit/3f2a9c6f5486e4202ec01e61fbef0e7d094e2371
Author: jinge90 <ge.jin at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/lib/builtins/int_math.h
M compiler-rt/lib/builtins/muldc3.c
Log Message:
-----------
[NFC][compiler-rt] Use __builtin_huge_val for CRT_INFINITY for double precision (#188197)
Commit: 2f8c0cbac0d755240112e3b62a628c59655be317
https://github.com/llvm/llvm-project/commit/2f8c0cbac0d755240112e3b62a628c59655be317
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
Log Message:
-----------
[RISCV] Use a switch default+llvm_unreachable instead of an assert. NFC (#189770)
Commit: 2b98f7fc3db5f99c6b1c152affb5d5906896154d
https://github.com/llvm/llvm-project/commit/2b98f7fc3db5f99c6b1c152affb5d5906896154d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Slightly optimize insertVSETMTK. NFC (#189771)
Sink the hasTKOp and hasTMOp checks into the switch.
Commit: f8b0a8c631eb3d88c990fb96b4488e4e02e137fc
https://github.com/llvm/llvm-project/commit/f8b0a8c631eb3d88c990fb96b4488e4e02e137fc
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
Log Message:
-----------
[CIR] Scoped atomic fetch uinc/dec (#189688)
Commit: 9085f74018a4f465afa84815d64af850f09b733f
https://github.com/llvm/llvm-project/commit/9085f74018a4f465afa84815d64af850f09b733f
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/Support/Parallel.h
M llvm/lib/Support/Parallel.cpp
Log Message:
-----------
[Support] Optimize parallel `TaskGroup` (#189196)
Two improvements to reduce `TaskGroup::spawn()` overhead:
1. Replace mutex-based `Latch::inc()` with atomic `fetch_add`. `dec()`
retains the mutex to prevent a race where `sync()` observes Count==0
and destroys the Latch while `dec()` is still running.
2. Pass `Latch&` through `Executor::add()` so the worker calls `dec()`
directly, eliminating the wrapper lambda that previously captured
both the user's callable and the Latch reference. This avoids one
`std::function` construction and potential heap allocation per spawn.
Commit: 7fce7631a0983b09abc968d24038e01ec1d02962
https://github.com/llvm/llvm-project/commit/7fce7631a0983b09abc968d24038e01ec1d02962
Author: Krzysztof Drewniak <krzysdrewniak at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/include/mlir/IR/ExtensibleDialect.h
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/Interfaces/InferTypeOpInterface.td
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/CAPI/Interfaces/Interfaces.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/WasmSSA/IR/WasmSSAOps.cpp
M mlir/lib/IR/ExtensibleDialect.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/Target/IRDLToCpp/Templates/PerOperationDecl.txt
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/unittests/Debug/FileLineColLocBreakpointManagerTest.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M mlir/unittests/IR/VerifierTest.cpp
M mlir/unittests/Interfaces/MemorySlotUtilsTest.cpp
M mlir/unittests/Transforms/DialectConversion.cpp
Log Message:
-----------
[mlir] Refactor opaque properties to make them type-safe (#185157)
At its core, this commit changes `OpaqueProperties` (aka a void*) to
`PropertyRef`, which is a {TypeID, void*}, where the TypeID is the ID of
the storage type of the given property (which can, as is often the case
for operations, be a struct of other properties).
Long-term, this change will allow for
1) Some sort of getFooPropertyRef() on property structs, allowing
individual members to be extracted generically
2) By having a property kind that is an OwningProprtyRef, generic
parsing (in combination with a bunch of other changes) 3) Probably a
safer C/Python API because we'll be able to indicate what's supposed to
be under a given void*
---------
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 6581d588193ce6c51700b426072da350895b95a2
https://github.com/llvm/llvm-project/commit/6581d588193ce6c51700b426072da350895b95a2
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/test/Analysis/DependenceAnalysis/PR188098.ll
Log Message:
-----------
[DA] Revise test `PR188098.ll` (NFC) (#189564)
This patch revises the test `Analysis/DependenceAnalysis/PR188098.ll`
added in #189428, primary to improve readability. I confirmed that this
test cashes without the change added in #188098.
Commit: d52a5e8a5ac47fea1b1d82669eb7d1bf5283d147
https://github.com/llvm/llvm-project/commit/d52a5e8a5ac47fea1b1d82669eb7d1bf5283d147
Author: AidinT <at.aidin at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ConvertToEmitC/CMakeLists.txt
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[MLIR] convert ConvertToEmitCPatternInterface to ODS (#188621)
This PR converts `ConvertToEmitCPatternInterface` dialect interface to ODS. Also makes changes to derived classes.
Commit: 585e2a015b29c1a53c4acddeda1b64b3fb3aac39
https://github.com/llvm/llvm-project/commit/585e2a015b29c1a53c4acddeda1b64b3fb3aac39
Author: AidinT <at.aidin at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A mlir/include/mlir/Bytecode/BytecodeDialectInterface.td
M mlir/include/mlir/Bytecode/BytecodeImplementation.h
M mlir/include/mlir/Bytecode/CMakeLists.txt
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[MLIR] Convert BytecodeDialectInterface to ods (#188852)
This PR converts `BytecodeDialectInterface` to ODS.
Commit: aefca764062a8dd0f6a26d94f78f9ef6a3731aa4
https://github.com/llvm/llvm-project/commit/aefca764062a8dd0f6a26d94f78f9ef6a3731aa4
Author: Thurston Dang <thurston at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
Log Message:
-----------
[msan] Add missing non-mem PMOV handling (#189768)
This adds support for the remaining non-memory PMOV intrinsics, using
the existing handlers.
handleAVX512VectorDownConvert() is slightly updated to handle cases
where there are fewer than 8 output elements (for which the mask is
still supplied as 8 bits).
Commit: 512071941da849587b8988f7e74c30c46b377a2c
https://github.com/llvm/llvm-project/commit/512071941da849587b8988f7e74c30c46b377a2c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
Log Message:
-----------
[RISCV] Add codegen support for SATI and USATI. (#189532)
Implementation is largely based on ARM which has similar instructions.
Commit: fe6d15ddbfd44d4a95fd2d292b1b0b431377a0dd
https://github.com/llvm/llvm-project/commit/fe6d15ddbfd44d4a95fd2d292b1b0b431377a0dd
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Modules/pr189415.cppm
Log Message:
-----------
[C++20] [Modules] Fix thread_local variable handling in modules (#189796)
Close https://github.com/llvm/llvm-project/issues/189415
The function shouldVarGenerateHereOnly should also handle thread_local
variables, not just static variables. This fixes incorrect code
generation for thread_local variables in named modules.
Commit: 1d549d9a777a6faef6d425cb6482ab1fa6b91bb7
https://github.com/llvm/llvm-project/commit/1d549d9a777a6faef6d425cb6482ab1fa6b91bb7
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_lrint, vp_llrint (#189714)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off two intrinsics from #179622.
We need to use the other intrinsic constructor in
ExpandVectorPredication.cpp because llrint has multiple overloaded types
Commit: 3068132e32c11839c2626347d5288f16d6623bea
https://github.com/llvm/llvm-project/commit/3068132e32c11839c2626347d5288f16d6623bea
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Use bind_front in tryToOptimizeInductionTruncate (NFC) (#189763)
Commit: 7e8449a96d552e22c927eccc439882464a3f2f28
https://github.com/llvm/llvm-project/commit/7e8449a96d552e22c927eccc439882464a3f2f28
Author: Weibo He <NewSigma at 163.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
Log Message:
-----------
[CoroSplit] Drop assumption that promise alloca is not accessed before coro.begin (NFC) (#189521)
There is an inconsistency in that the code assumes the promise alloca is
not modified before coro.begin, yet it handles such accesses later. This
patch proposes dropping that assumption and analyzing accesses before
coro.begin from the outset, allowing #189295 to erase promise alloca
without analyse it afterwards.
Commit: 8edbf230980a038f120e754439a79cec68ad9356
https://github.com/llvm/llvm-project/commit/8edbf230980a038f120e754439a79cec68ad9356
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/cxx26.cpp
Log Message:
-----------
[clang][bytecode] Revisit reference variables as constexpr-unknown in C++26 (#187918)
When revisiting `const T& range = f(T());`, we do mark the variable for
`range` as constexpr-unknown, but not the temporary variable we create
for `T()`. Change that.
Then we also need to ignore constexpr-unknown pointers in
`CheckInvoke()`.
Fixes https://github.com/llvm/llvm-project/issues/187775
Commit: 21f94950a8411d0a10eaf3380ae44b411f65a0d3
https://github.com/llvm/llvm-project/commit/21f94950a8411d0a10eaf3380ae44b411f65a0d3
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M compiler-rt/test/sanitizer_common/TestCases/Linux/soft_rss_limit_mb_test.cpp
Log Message:
-----------
[compiler-rt] Try bumping soft_rss_limit again (#188441)
Previous instance: #171469
Commit: 6a31be68e38e4656354edddfcb137b0c8234a01c
https://github.com/llvm/llvm-project/commit/6a31be68e38e4656354edddfcb137b0c8234a01c
Author: Lukas Sommer <lukas.sommer at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
Log Message:
-----------
[mlir][NFC] Remove conditionally unused type alias (#189894)
The `RawType` type alias is unused (`-Wunused-local-typedef`) in build
with asserts deactivated. In combination with `-Werror`, this causes
builds to fail.
Signed-off-by: Lukas Sommer <lukas.sommer at amd.com>
Commit: 2e51fdaa774be8e0d6b4d6743a2f77cdb3a71e3c
https://github.com/llvm/llvm-project/commit/2e51fdaa774be8e0d6b4d6743a2f77cdb3a71e3c
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/include/lldb/lldb-private-enumerations.h
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Commands/CommandObjectMemory.cpp
M lldb/source/Expression/IRMemoryMap.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
M lldb/source/Plugins/Process/NetBSD/NativeProcessNetBSD.cpp
M lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
M lldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Target/MemoryRegionInfo.cpp
M lldb/source/Target/Process.cpp
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
M lldb/unittests/Target/MemoryRegionInfoTest.cpp
Log Message:
-----------
[lldb] Replace OptionalBool with LazyBool (#189652)
The only difference between them is that OptionalBool's third state
is "unknown" and LazyBool's is "calculate". We don't need to tell
the difference in a single context, so I've made a new eLazyBoolDontKnow
which is an alias of eLazyBoolCalculate.
Commit: eeb2fae5c00586e0764be907336e3de27af2b3b1
https://github.com/llvm/llvm-project/commit/eeb2fae5c00586e0764be907336e3de27af2b3b1
Author: David Green <david.green at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/dup.ll
Log Message:
-----------
[AArch64][GISel] Do not bitcast nonpower2 element size G_CONCATs (#189911)
This currently gets stuck in a loop, unable to make progress throught
the
bitcast concat. Limit it to legal element sizes so that we always make
progress
and at least fall back to SDAG as opposed to crashing or getting stuck.
Commit: 2313989499b5ee9befd9865310f6fa02f561cf63
https://github.com/llvm/llvm-project/commit/2313989499b5ee9befd9865310f6fa02f561cf63
Author: VASU SHARMA <44048872+vasu-the-sharma at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A clang/test/CodeGen/ubsan-aggregate-null-align.c
Log Message:
-----------
[UBSAN] [NFC] pre-commit tests for null, alignment, bounds checks (#176210)
PR to add precommit tests to document current UBSAN behavior for
aggregate copy operations.
The test covers:
- Sanitizers: null, alignment, bounds
- Type variants: plain, _Atomic (C), volatile (C)
- Operand forms: arr[idx], *ptr
- Operations: assignment, initialization, initializer list, variadic
args, nested member access
- C++ specific: direct/brace/copy-list init, new expressions, casts,
operator=, virtual base init
- Bounds checking: in-bounds access, past-the-end access (index ==
size), beyond bounds access, dynamic index
---------
Co-authored-by: vasu-ibm <Vasu.Sharma2 at ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil at gmail.com>
Commit: b1f8c285597925428d1f110ad7c1accff70eb885
https://github.com/llvm/llvm-project/commit/b1f8c285597925428d1f110ad7c1accff70eb885
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/unittests/IR/AttributeTest.cpp
Log Message:
-----------
[MLIR] Validate APInt bitwidth in IntegerAttr::get(Type, APInt) (#188725)
IntegerAttr::get(Type, APInt) did not validate that the APInt's bit
width matched the expected bit width for the given type. For integer
types, the APInt width must equal the integer type's width. For index
types, the APInt width must equal IndexType::kInternalStorageBitWidth
(64 bits).
Passing an APInt with the wrong bit width could cause a
non-deterministic crash in StorageUniquer when comparing two IntegerAttr
instances for the same type but with different APInt widths.
This commit adds assertions in the get(Type, APInt) builder to catch
such misuse early in debug builds, providing a clear error message at
the call site rather than a cryptic crash in the storage uniquer.
Fixes #56401
Assisted-by: Claude Code
Commit: 249e871fa4ef9acc38f8aa02f124322f85635756
https://github.com/llvm/llvm-project/commit/249e871fa4ef9acc38f8aa02f124322f85635756
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
Log Message:
-----------
[MLIR][ArithToLLVM] Fix index_cast on memref types generating invalid LLVM IR (#189227)
`arith.index_cast` and `arith.index_castui` accept memref operands (via
`IndexCastTypeConstraint`), but `IndexCastOpLowering::matchAndRewrite`
did not handle this case. When the operand was a memref, the conversion
framework substituted the converted LLVM struct type, and the lowering
incorrectly attempted to emit `llvm.sext`/`llvm.zext`/`llvm.trunc` on a
struct value, producing invalid LLVM IR.
Since LLVM uses opaque pointers, all memrefs with integer or index
element types lower to the same `\!llvm.struct<(ptr, ptr, i64, ...)>`
type, making `arith.index_cast` on memrefs a no-op at the LLVM level.
Add a check that treats the memref case as an identity conversion (same
as the same-bit-width path).
Fixes #92377
Assisted-by: Claude Code
Commit: 5651490992f3f5da7f39b228f019631725ff9d7f
https://github.com/llvm/llvm-project/commit/5651490992f3f5da7f39b228f019631725ff9d7f
Author: lrzlin <linrunze at loongson.cn>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
A llvm/test/CodeGen/LoongArch/mergestores.ll
Log Message:
-----------
[LoongArch] Implement canMergeStoresTo to avoid crash while NoImplicitFloat attribute is set (#188005)
Currently, when the `NoImplicitFloat` attribute is set, consecutive
64-bit load
and store operations will be combined into 128-bit ones, which is
illegal
because that attribute makes floating point and SIMD unavailable.
By implementing the canMergeStoresTo, we can prevent this incorrect
merging.
Fixes https://github.com/llvm/llvm-project/issues/186645
Commit: 6b2b0da40de1495ace2b100799a35711f7ad7b21
https://github.com/llvm/llvm-project/commit/6b2b0da40de1495ace2b100799a35711f7ad7b21
Author: lonely eagle <2020382038 at qq.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Transforms/CSE.cpp
Log Message:
-----------
[mlir][CSE] Fix double-counting of numCSE statistic (#189802)
This PR fixes a regression where the numCSE statistic was being
incremented twice for a single operation elimination. The numCSE counter
is already internally incremented within the replaceUsesAndDelete
function. Manually incrementing it again after the function call leads
to an inaccurate total count. This is part of the
https://github.com/llvm/llvm-project/pull/180556.
Commit: 71cc59400c531d1f9c4a928dae62d20cca3690bd
https://github.com/llvm/llvm-project/commit/71cc59400c531d1f9c4a928dae62d20cca3690bd
Author: Ruoyu Qiu <cabbaken at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] add debug log in findGCD (#189537)
Commit: c5363f2166710b0c6e728d5ee11efc99ccf42d87
https://github.com/llvm/llvm-project/commit/c5363f2166710b0c6e728d5ee11efc99ccf42d87
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/IR/Core.cpp
M llvm/tools/llvm-c-test/echo.cpp
Log Message:
-----------
[IR] Fix C API after getTerminator() change (#189922)
The C API function LLVMGetBasicBlockTerminator should return NULL when
the basic block is not well-formed.
Commit: 6bf794a02a509bf051c50fe2f14009e117ef50ed
https://github.com/llvm/llvm-project/commit/6bf794a02a509bf051c50fe2f14009e117ef50ed
Author: Daniil Fukalov <dfukalov at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/test/CodeGenCUDA/fp-contract.cu
M llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-alloca-issue-155902.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
Log Message:
-----------
[AMDGPU] Disable generic DAG combines at -O0 to preserve debuggability. (#176304)
Disable generic DAG combines for AMDGPU at -O0 via
disableGenericCombines() to preserve instructions that users may want to
set breakpoints on during debugging.
Assisted-by: Cursor / Claude Opus 4.6
Commit: 97562e7e5cae5d6dc019b8f3275eb9639978c05f
https://github.com/llvm/llvm-project/commit/97562e7e5cae5d6dc019b8f3275eb9639978c05f
Author: Andrew Marshall <planetmarshall at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M compiler-rt/cmake/Modules/CheckAssemblerFlag.cmake
Log Message:
-----------
pass target triple to `check_assembler_flag` (#188521)
Target specific flags (Notably `-mimplict=always` for ARM) are not
recognized by the clang assembler unless the target is specified. This
PR passes the value of `CMAKE_C_COMPILER_TARGET` to the assembler so
that target specific flags are recognized.
## Previous behaviour
When configuring builtins for an ARMv7 target:
```
-- Builtin supported architectures: armv7
-- Checking for assembler flag -mimplicit-it=always
-- Checking for assembler flag -mimplicit-it=always - Not accepted
-- Checking for assembler flag -Wa,-mimplicit-it=always
-- Checking for assembler flag -Wa,-mimplicit-it=always - Not accepted
CMake Warning at CMakeLists.txt:462 (message):
Don't know how to set the -mimplicit-it=always flag in this assembler; not
including Arm optimized implementations
```
## New behaviour
```
-- Builtin supported architectures: armv7
-- Checking for assembler flag -mimplicit-it=always
-- Checking for assembler flag -mimplicit-it=always - Accepted
```
## Steps to reproduce:
```
$ cmake -S compiler-rt/lib/builtins -B build \
-DCMAKE_C_COMPILER=clang \
-DCMAKE_C_COMPILER_TARGET=armv7-unknown-linux-gnueabihf \
-DCOMPILER_RT_DEFAULT_TARGET_ONLY=ON
```
Commit: d6cd15901a7b17657687c330afa7ee974e27e3be
https://github.com/llvm/llvm-project/commit/d6cd15901a7b17657687c330afa7ee974e27e3be
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/test/MC/AArch64/armv9a-tlbip.s
Log Message:
-----------
[AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (#178913)
Change the gating of `tlbip` instructions (`sysp` aliases) containing
`*E1IS*`, `*E1OS*`, `*E2IS*` or `*E2OS*` to be used with `+tlbid` or
`+d128`. This is because the 2025 Armv9.7-A MemSys specification says:
```
All TLBIP *E1IS*, TLBIP *E1OS*, TLBIP *E2IS* and TLBIP *E2OS*
instructions that are currently dependent on FEAT_D128 are updated
to be dependent on FEAT_D128 or FEAT_TLBID
```
See also change #178912 where the gating of `+d128` for `sysp` was
removed.
Commit: f6ffdbcbaec23f54a9254c7e19df002f1a0a9425
https://github.com/llvm/llvm-project/commit/f6ffdbcbaec23f54a9254c7e19df002f1a0a9425
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/test/Dialect/Affine/scalrep.mlir
Log Message:
-----------
[MLIR][Affine] Fix dead store elimination for vector stores with different types (#189248)
affine-scalrep's findUnusedStore incorrectly classified an
affine.vector_store as dead when a subsequent store wrote to the same
base index but with a smaller vector type. A vector<1xi64> store at
[0,0] does not fully overwrite a vector<5xi64> store at [0,0], so the
first store must be preserved.
The loadCSE function in the same file already had the correct
type-equality check for loads; this patch adds the analogous check for
stores in findUnusedStore.
Fixes #113687
Assisted-by: Claude Code
Commit: f2685fabc5bbe33a8b95b665dc4e24223c42fdd9
https://github.com/llvm/llvm-project/commit/f2685fabc5bbe33a8b95b665dc4e24223c42fdd9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode] Disable tail calls on sparc (#189887)
Looks like this causes problems there as well:
https://lab.llvm.org/buildbot/#/builders/114/builds/252
Interp.cpp:2572:21: error: cannot tail-call: target is not able to
optimize the call into a sibling call
2572 | MUSTTAIL return Fn(S, PC);
| ~~^~~~~~~
Commit: effcd181e580c6f83dfc88a0362705ddb6601f5b
https://github.com/llvm/llvm-project/commit/effcd181e580c6f83dfc88a0362705ddb6601f5b
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for VP float rounding intrinsics (#189896)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off seven intrinsics from #179622.
We now generate vfcvt.rtz for llvm.vp.roundtozero. It looks like we
should have been using the codegen for llvm.trunc for it, but we somehow
missed that.
Commit: 0d33a15d3320567639dd8f043c7aa22a55653dab
https://github.com/llvm/llvm-project/commit/0d33a15d3320567639dd8f043c7aa22a55653dab
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/test/Modules/pr189415.cppm
Log Message:
-----------
Add a target triple to clang/test/Modules/pr189415.cppm (#189937)
Not all targets support thread_local, so in some environments the test
would fail with:
tools/clang/test/Modules/Output/pr189415.cppm.tmp/counter.cppm:6:1:
error: thread-local storage is not supported for the current target
Follow-up to #189796
Commit: 5249f5ad4d91826507fae4b7d776d1eeabc9bb2a
https://github.com/llvm/llvm-project/commit/5249f5ad4d91826507fae4b7d776d1eeabc9bb2a
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
M llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
Log Message:
-----------
[MCA] Make `ResourceSizeMask` const (#189453)
This patch marks the already effectively constant `ResourceSizeMask` as
`const`. It adds a helper `computeResourceSizeMask()` to initialize it
in the member initializer list.
Commit: 8a06085c610a49739beb0af716a30714f073540c
https://github.com/llvm/llvm-project/commit/8a06085c610a49739beb0af716a30714f073540c
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
Log Message:
-----------
[CodeGen] Add listener support to the rematerializer (NFC) (#184338)
This change adds support for adding listeners to the target-independent
rematerializer; listeners can catch certain rematerialization-related
events to implement some additional functionality on top of what the
rematerializer already performs.
This is NFC and has no user at the moment, but the plan is to have
listeners start being responsible for secondary/optional functionalities
that are at the moment integrated with the rematerializer itself. Two
examples of that are:
1. rollback support (currently optional), and
2. region tracking (currently mandatory, but not fundamentally necessary
to the rematerializer).
Commit: 042997bd15a52ef435673e9182ed5cd2453f8ab0
https://github.com/llvm/llvm-project/commit/042997bd15a52ef435673e9182ed5cd2453f8ab0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
Log Message:
-----------
[RISCV] combine-is_fpclass.ll - add initial tests showing failure to constant fold ISD::IS_FPCLASS nodes (#189940)
Commit: 3b1125b1edf997e261ebafdf31b1828f5c458ebb
https://github.com/llvm/llvm-project/commit/3b1125b1edf997e261ebafdf31b1828f5c458ebb
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
Log Message:
-----------
[SCEV] Add canonical SCEV pointer and construct canonical SCEVs (NFC) (#188858)
Add a canonical SCEV pointer to SCEV, to support comparing SCEVs for
equality, even with different use-specific flags.
Currently this should be NFC, as nothing yet sets use flags.
Compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=13f1fd006243f756417c3ae992342c0674e3f04e&to=e7f46bcf8bef62c619380fbcccbe6073300b69fe&stat=instructions:u
+0.03% - +0.05% on stage1 configs
-0.03% surprisingly for stage2-O3
PR: https://github.com/llvm/llvm-project/pull/188858
Commit: 26b755c09bfa5b5e31c3cef8d4118316b2937cdd
https://github.com/llvm/llvm-project/commit/26b755c09bfa5b5e31c3cef8d4118316b2937cdd
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/Value.h
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Value.cpp
Log Message:
-----------
[IR] Remove Value::HasMetadata (#189917)
Metadata already has two separate implementations, one for GlobalObject
and one for Instruction. Instruction was already separate due to special
MD_dbg handling, so move the GlobalObject-specific metadata parts from
Value to GlobalObject.
The HasMetadata bit, originally an optimization to avoid the hash table
lookup when a value has no metadata, is no longer needed, because the
information is now stored directly in Instruction/GlobalObject's
MetadataIndex field.
This also fixes MSan builds, currently ~Value clears metadata and
therefore needs to access the subclass's MetadataIndex field, which was
already destructed at this point.
Commit: c67092066e1812bdbec10e4a3628a5f77faa8f9f
https://github.com/llvm/llvm-project/commit/c67092066e1812bdbec10e4a3628a5f77faa8f9f
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/lib/Lex/TokenLexer.cpp
M clang/test/Lexer/gnu-flags.c
A clang/test/Lexer/gnu-zero-variadic-macro-argument-fixit.c
M clang/test/Preprocessor/macro_fn.c
Log Message:
-----------
[clang] Suggest using __VA_OPT__(,) instead of GNU zero variadic macro argument (#188624)
Also provide an appropriate fixit.
Commit: 96db944036a09e773d1e3fff4fa3805a4f75e59e
https://github.com/llvm/llvm-project/commit/96db944036a09e773d1e3fff4fa3805a4f75e59e
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/spec_const_decoration.ll
Log Message:
-----------
[NFC][SPIR-V] Remove stale XFAIL for spec_const_decoration.ll (#189934)
The test no longer fails with expensive_checks enabled
```
Unexpectedly Passed Tests (1):
LLVM :: CodeGen/SPIRV/spec_const_decoration.ll
```
after
https://github.com/llvm/llvm-project/commit/18e695890306c6824cc15779e1acb7e5956cbec1
(https://github.com/llvm/llvm-project/pull/134016)
also add `-verify-machineinstrs` as per #188703
Commit: 69b116d07503061026ffddbaf74e4b33615fc205
https://github.com/llvm/llvm-project/commit/69b116d07503061026ffddbaf74e4b33615fc205
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
Log Message:
-----------
[SPIR-V] Fix OpVectorExtractDynamic operand type (#189635)
vID is a register class for integer vector registers only. vfID (float
vector registers) should be also accepted. Aligning the definition with
other instructions of this kind
related to #188703
Commit: ed48aeadf37ad811f5fa999e2de07f1ae05d1e24
https://github.com/llvm/llvm-project/commit/ed48aeadf37ad811f5fa999e2de07f1ae05d1e24
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
Log Message:
-----------
[lldb][AArch64][Linux] Add support for SME only systems (#165413)
This is the implementation part of #138717, tests and documentation will
be in a separate PR.
SME only systems have SME but not SVE. Previously we assumed that you
would either have SVE, SVE+SME, or neither. On an SME only system, the
SVE register state exists only in streaming mode. SVE instructions may
be used, but only in streaming mode. The Linux kernel will report that
such a processor has SME features but no SVE features.
This means that the non-streaming SVE ptrace register set is
inaccessible (with one exception mentioned below). So the main change
here is around the management of FP registers.
* In non-streaming mode, FP registers must be accessed via the FP
register set. Not the non-streaming SVE register set.
* In streaming mode, FP registers are a subset of the streaming SVE
registers, accessed via the streaming SVE register set.
The one exception the kernel allows is:
> On systems that do not support SVE it is permitted to use SETREGSET to
write SVE_PT_REGS_FPSIMD formatted data via NT_ARM_SVE, in this case the
vector length should be specified as 0. This allows streaming mode to be
disabled on systems with SME but not SVE.
https://docs.kernel.org/arch/arm64/sve.html
This is how we are able to restore to a non-streaming state when an
expression leaves us in streaming mode.
The major changes to LLDB are:
* If we receive only SVG in the expedited registers, we now assume it's
an SME only system and therefore VG == SVG.
* A new state SVEState::StreamingFPSIMD is added to mark the mode where
we are in FPSIMD mode on an SME only system (as opposed to the FPSIMD
state of an SVE or SVE+SME system).
* CalculateFprOffset now returns different results depending on whether
we have only SIMD or we have streaming SVE. In the latter case, the
stored register offsets are relative to the SVE registers, but actual
accesses need to be relative to the ptrace FP register set.
* In WriteAllRegisters, if we have an FP set to restore on an SME only
system we assume we must have been in non-streaming mode at the time of
the save. So we restore it using the previously mentioned non-streaming
SVE write.
* GetSVERegSet and ConfigureRegisterContext were updated to handle the
new StreamingFPSIMDOnly state.
Commit: d14888121db01f9d8f772fa6daaeb4d293085de0
https://github.com/llvm/llvm-project/commit/d14888121db01f9d8f772fa6daaeb4d293085de0
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
Log Message:
-----------
[Mips] Correctly report sizes for PATCHABLE_* (#188229)
Report the size of the xray sled.
This came up while working on
https://github.com/llvm/llvm-project/pull/187703.
Commit: 5639c0bb3f721fea802b03aacd531d2a3ac71ac0
https://github.com/llvm/llvm-project/commit/5639c0bb3f721fea802b03aacd531d2a3ac71ac0
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[llvm][docs] Add release note for LLDB AArch64 Linux SME only support (#189367)
And highlights that some earlier versions have a critical issue on such
systems. This is not something we are able to fix (because the branches
are closed), but users and packagers have some options which are listed
in the issue.
Relates to #138717.
Commit: ab4b689258c21c5e47d1a865b8b980e01395aac7
https://github.com/llvm/llvm-project/commit/ab4b689258c21c5e47d1a865b8b980e01395aac7
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
Log Message:
-----------
[AMDGPU][SIFoldOperands] Fix OR -1 fold (#189655)
In SIFoldOperands, folding `or x, -1` to `v_mov_b32 -1` removed
`Src1Idx`, which is incorrect because `-1` is in `Src0Idx` (after
canonicalization).
Closes https://github.com/llvm/llvm-project/issues/189677.
Commit: 2cff995e91c3ff2fe21ae2e5c0bfb7c6746c3029
https://github.com/llvm/llvm-project/commit/2cff995e91c3ff2fe21ae2e5c0bfb7c6746c3029
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.h
A llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll
Log Message:
-----------
[AMDGPU] Fix crash with dead frame indices in debug values (#183297)
When spill slots are eliminated (VGPR-to-AGPR, SGPR-to-VGPR lanes),
debug values referencing these frame indices were not always properly
cleaned up. This caused an assertion failure in getObjectOffset() when
PrologEpilogInserter tried to access the offset of a dead frame object.
The existing debug fixup code in SIFrameLowering and SILowerSGPRSpills
had two limitations:
1. It only checked one operand position, but DBG_VALUE_LIST instructions
can have multiple debug operands with frame indices.
2. It didn't handle all types of dead frame indices uniformly.
Fix by centralizing debug info cleanup in removeDeadFrameIndices(),
which already knows all frame indices being removed. This iterates over
all debug operands using MI.debug_operands().
Assisted-by: Claude Code.
Commit: 03b5539dd58584e6821e11123d5c8546147a6f41
https://github.com/llvm/llvm-project/commit/03b5539dd58584e6821e11123d5c8546147a6f41
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/unittests/Analysis/CFGTest.cpp
Log Message:
-----------
[ADT] Align `GenericCycle::getExitBlocks`/`getExitingBlocks` methods with LoopBase
Ensure `GenericCycle::getExitBlocks` does not replace the content
of the output vector and behaves as `LoopBase::getExitBlocks`,
previously exposing an issue within `isPotentiallyReachable`.
Fixes: https://github.com/llvm/llvm-project/issues/189800.
Fixes: https://github.com/llvm/llvm-project/issues/189289.
Fixes: https://github.com/llvm/llvm-project/issues/189234.
Fixes: https://github.com/llvm/llvm-project/issues/189180.
Commit: 9d592d9e07509f384c2bc0a29df1a8e4ec516763
https://github.com/llvm/llvm-project/commit/9d592d9e07509f384c2bc0a29df1a8e4ec516763
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
M llvm/test/Analysis/LoopAccessAnalysis/invariant-dep-same-ptr.ll
M llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected
Log Message:
-----------
[LAA] Catch load/store to invariant address in dependency checker. (#187023)
There are some accesses we cannot easily catch with the existing SSA
based tracking of uniform stores.
Extend the dependency checker to reject accesses the same invariant
address for cases SCEV can prove (distance is zero).
For those cases, we would not generate runtime checks for the
problematic pair, as they are part of the same group.
Note that this adds a new InvariantUnsafe kind, similar to
IndirectUnsafe, although maybe it would be sufficient to just have a
single Unsafe kind, with slight loss of precision.
Fixes https://github.com/llvm/llvm-project/issues/186922.
PR: https://github.com/llvm/llvm-project/pull/187023
Commit: bc36746ddfee3ca7724e00311f6371090a43754c
https://github.com/llvm/llvm-project/commit/bc36746ddfee3ca7724e00311f6371090a43754c
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/docs/use/aarch64-linux.md
Log Message:
-----------
[lldb][docs] Add documentation for AArch64 Linux SME only support (#165415)
As for other features, this is a mixture of user facing decisions and
internal design decisions.
Commit: 23d76784a5aa01140543881f2c27ace6a6545f98
https://github.com/llvm/llvm-project/commit/23d76784a5aa01140543881f2c27ace6a6545f98
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A lldb/test/API/linux/aarch64/sme_only_registers/Makefile
A lldb/test/API/linux/aarch64/sme_only_registers/TestSMEOnlyRegisters.py
A lldb/test/API/linux/aarch64/sme_only_registers/main.c
Log Message:
-----------
[lldb][AArch64][Linux] Add tests for SME only support (#165414)
This PR is the tests for #138717. I have split it from implementation as
there is a lot of code, and the two don't really overlap. The tests are
checking what a user will see in LLDB, and only indirectly what happens
in lldb-server.
There are two types of tests, the first is register access tests. These
start in a given mode, where a mode is a combination of the streaming
mode on or off, ZA on or off, and a vector length.
For register access tests I have used two states:
* Streaming mode, ZA on, default vector length
* Non-streaming mode, ZA off, default vector length
(changing mode and vector length is tested in existing SVE+SME tests and
the expression tests I'm adding in this same PR)
The test program:
* Sets up the requested mode.
* Allocates a bunch of buffers for LLDB to write expected register
values to.
* Sets initial register values.
Then LLDB looks for those expected values. Assuming they are present, it
then writes a new set of values to the registers, and to the buffers
within the program. The program is then stepped, which runs an
in-process function to check that it now sees those register values. If
that function fails, we have a bug. If it does not, LLDB then checks for
the same values.
This process repeats for several registers. Hence the repeated calls to
check_register_values in the test program.
In this way we make sure that LLDB sends the correct values to ptrace by
validating them in process. Also that LLDB does not write other
registers in the process of writing one register. Which happened to me
several times during development.
The buffer writes are done with memory writes not expression evaluation
becuase at this stage we cannot trust that expressions work (the
expression tests will later prove that they do).
The second type of tests are expression state restoration tests. For
each combination of states we check that we can restore to a given state
if an expression takes us into the other state. This includes between
the same state, and adds an extra vector length to check expanding and
shrinking SVE buffers. This produces roughly 64 tests.
I have written them all as one test case in a loop because these take a
long time (~20 minutes on an FVP) and you almost always want it to fail
fast. When tracing is enabled you'll see the current states logged.
It's possible that we could skip some of these tests as being very
unlikely to ever happen, but in the spirit of
"There are Only Four Billion Floats–So Test Them All!" I think it is
simpler to enumerate every possible state change.
I have not added a test for executing an expression incompatible with
the current mode because this leads to SIGILL, which I know we already
handle. At this time LLDB makes no effort to make the expression
compatible with the current mode either.
Commit: 5072c020aae1636f687af797d4082a26a761c721
https://github.com/llvm/llvm-project/commit/5072c020aae1636f687af797d4082a26a761c721
Author: Erick Ochoa Lopez <erick.ochoalopez at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/test/Dialect/Vector/vector-transfer-drop-unit-dims-patterns.mlir
Log Message:
-----------
[mlir][vector] Drop trailing 1-dims from constant_mask (#187383)
Generalize TransferReadDropUnitDimsPattern to also drop unit dimensions
when `vector::ConstantMaskOp` is used.
Previously TransferReadDropUnitDimsPattern would only drop unit
dimensions when `vector::CreateMaskOp` with a statically known operand
was used.
Assisted-by: Cursor
Commit: 9a33125e42925c1e4a9c9f83a2f251b046dd65cd
https://github.com/llvm/llvm-project/commit/9a33125e42925c1e4a9c9f83a2f251b046dd65cd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
M llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
M llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
Log Message:
-----------
[DAG] Add basic ISD::IS_FPCLASS constant/identity folds (#189944)
Attempts to match middle-end implementation in InstructionSimplify/foldIntrinsicIsFPClass
Fixes #189919
Commit: 461a1c51bf0998edc1fd3b9b7197437136c2fb18
https://github.com/llvm/llvm-project/commit/461a1c51bf0998edc1fd3b9b7197437136c2fb18
Author: AidinT <at.aidin at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/tools/mlir-tblgen/CppGenUtilities.cpp
Log Message:
-----------
[mlir][ods] resolve the wrong indent issue (#189277)
The `emitSummaryAndDescComments` is used to generate summary and
description for tablegen generated classes and structs such as Dialects
and Interfaces. The generated summary and description is indented
incorrectly in the output generated file. For example
`NVGPUDialect.h.inc ` looks like the following:
```cpp
namespace mlir::nvgpu {
/// The `NVGPU` dialect provides a bridge between higher-level target-agnostic
/// dialects (GPU and Vector) and the lower-level target-specific dialect
/// (LLVM IR based NVVM dialect) for NVIDIA GPUs. This allow representing PTX
/// specific operations while using MLIR high level dialects such as Memref
/// and Vector for memory and target-specific register operands, respectively.
class NVGPUDialect : public ::mlir::Dialect {
...
};
} // namespace mlir::nvgpu
```
This is because the `emitSummaryAndDescComments` trims the summary and
description from both sides, rendering the re-indentation useless. This
PR resolves this bug.
Commit: 158f10fe24a39208e45d6039dfc6d605967ade2a
https://github.com/llvm/llvm-project/commit/158f10fe24a39208e45d6039dfc6d605967ade2a
Author: Ming Yan <ming.yan at terapines.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
Log Message:
-----------
[mlir][memref] Fold memref.reinterpret_cast operations with valid offset or size constants. (#189533)
When encountering an invalid offset or size, we only skip the current
invalid value and continue attempting to fold other valid offsets or
sizes.
Commit: b46f8fa622ab8edf00e986eed2350f137b5efc0b
https://github.com/llvm/llvm-project/commit/b46f8fa622ab8edf00e986eed2350f137b5efc0b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A clang/test/CodeGen/tbaa-matrix.c
Log Message:
-----------
[Matrix] Add tests checking TBAA emission for matrix types (NFC). (#189953)
PR: https://github.com/llvm/llvm-project/pull/189953
Commit: 15d48c5bbe2189db1b79aca0b4f355d0c7d664b6
https://github.com/llvm/llvm-project/commit/15d48c5bbe2189db1b79aca0b4f355d0c7d664b6
Author: Gergo Stomfai <stomfaig at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
Log Message:
-----------
[X86][DAG] remove LowerFCanonicalize (#188127)
Remove LowerFCanonicalize. Added fallback for cases when the scalar type also has its Custom lowering to avoid regressions on AMDGPU and SystemZ.
Fixes #143862
Commit: d6b8163f3fb5b9fe8262171d9815030ccfc3772a
https://github.com/llvm/llvm-project/commit/d6b8163f3fb5b9fe8262171d9815030ccfc3772a
Author: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/neon-abd.ll
M llvm/test/CodeGen/X86/abds.ll
Log Message:
-----------
Retry "[SDAG] (abs (add nsw a, -b)) -> (abds a, b) (#175801)" (#186659)
A better version of #175801 . see that for more info.
Fixes #185467
The original patch was checking the correctness of the transformation
based on the original Op1 , which was then negated (in the case of
IsAdd). This patch fixes that issue by inverting the sign bit in that
case.
Also pushed a slight nfc there to simplify the code and remove some
duplication.
alive2 proofs:
abds: https://alive2.llvm.org/ce/z/oJQPss
abdu: https://alive2.llvm.org/ce/z/HfPF5q
Note that the regression test is not (wrongly) affected anymore by the
patch (as it did before)
Commit: 5781cc9bf6d4e2b1023162eb7878028e2d21e3d4
https://github.com/llvm/llvm-project/commit/5781cc9bf6d4e2b1023162eb7878028e2d21e3d4
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/test/TableGen/intrinsic-struct.td
Log Message:
-----------
[LLVM][Intrinsics] Refactor IIT encoding generation (#189790)
Refactor IIT encoding generation. The core change here is that when
generating IIT encodings, we pre-generate all the bits of the IIT
encoding except cases where a type needs to encode its own overload
index, which is patched in later in `TypeInfoGen`. In addition, this
change introduces a class hierarchy for dependent types, so that the
checks in `TypeInfoGen` are more meaningful, and renames/simplifies
several other pieces of code, as listed below.
1. Change the encoding for IIT_ARG's ArgInfo byte to encode the overload
slot index in lower 5 bits and the argument kind in upper 3 bits. This
enabled generating the same packed format for all other dependent types
that need to encode an overload slot index in the IIT encoding. Adjusted
the corresponding C++ code in `IITDescriptor::getArgumentNumber` and
`IIT_Descriptor::getArgumentKind`.
2. Introduce more descriptive classes to handle packing of the overload
index + arg kind into the IIT encoding. `OverloadIndexPlaceholder` is
used to generate a transient value in the type-signature that is patched
in `TypeInfoGen` with that type's overload index. `PackOverloadIndex` is
used to encapsulate the final packing of an overload index and argument
kind in a single byte, and `PatchOverloadIndex` is the class that does
the required patching of a `OverloadIndexPlaceholder` given the type's
overload index.
3. Delete `isAny`, `ArgCode` and `Number` from base `LLVMType` class.
Replace use of `isAny` with `isa<LLVMAnyType>`, `ArgCode` is not used
anymore, and move `Number`, which was used to represent the overload
index for a dependent type to the `LLVMDependentType` class and rename
it to `OverloadIndex`.
4. Introduce `LLVMDependentType` as a base class of all dependent types.
It holds the overload index of the type it depends on in its
`OverloadIndex` field. Also introduce 2 subclasses,
`LLVMFullyDependentType` to represent all fully dependent types (which
encode just the appropriate IIT code and the dependent type's overload
index) and `LLVMPartiallyDependentType` to represent partially dependent
types, that encode the appropriate IIT code and both this type's
overload index and the dependent type's overload index.
5. Change existing dependent type classes to derive from one of these
classes and rename the `num` class argument to `oidx` to better reflect
its meaning.
6. Rename various fields and classes used in `TypeInfoGen` to be more
meaningful. `AssignOverloadIndex` to do overload index assignment,
rename `ACIdxs` to `OverloadIdxs`, `ACTys` to `OverloadTypes` and use
the `DoPatchOverloadIndex` to patch in assigned overload slot indexes.
Commit: ce78c16738f805f8635ce6c575c184b94160fade
https://github.com/llvm/llvm-project/commit/ce78c16738f805f8635ce6c575c184b94160fade
Author: Lewis Crawford <lcrawford at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/Transforms/SROA/vector-promotion-via-tree-structure-merge.ll
Log Message:
-----------
SROA: Fix tree merge IRBuilder insert point (#189680)
StoreInfos is sorted by slice offset, not program order. Anchoring the
IRBuilder at StoreInfos.back() could emit shufflevectors before SSA
values defined later in the same block (invalid IR).
Insert merged shuffles immediately before TheLoad when the load shares
the store block. When the load is elsewhere, insert before the store
block terminator so the merge runs after every store + any trailing
instructions in that block.
Commit: d95292f67b48666be421afe0a3d919480458a6df
https://github.com/llvm/llvm-project/commit/d95292f67b48666be421afe0a3d919480458a6df
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/include/lldb/Host/FileAction.h
M lldb/include/lldb/Host/ProcessLaunchInfo.h
A lldb/include/lldb/Host/windows/WindowsFileAction.h
M lldb/source/Host/CMakeLists.txt
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
A lldb/source/Host/windows/WindowsFileAction.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/HostTest.cpp
Log Message:
-----------
[lldb][windows] refactor FileAction (#179274)
Commit: 31edb8fab547eaa76427bf5c62b0c9e58cba3e41
https://github.com/llvm/llvm-project/commit/31edb8fab547eaa76427bf5c62b0c9e58cba3e41
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/test/Transforms/LICM/preheader-safe.ll
M llvm/test/Transforms/LICM/read-only-calls.ll
Log Message:
-----------
[LICM] Generate test checks (NFC) (#189963)
Commit: fd40c606652137706bc336ef80ed1814ab3d3680
https://github.com/llvm/llvm-project/commit/fd40c606652137706bc336ef80ed1814ab3d3680
Author: David Green <david.green at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll
Log Message:
-----------
[VectorCombine] Fix transitive Uses in foldShuffleToIdentity (#188989)
The Uses in foldShuffleToIdentity is intended to detect where an operand
is used to distinguish between splats, identities and concats of the
same value. When looking through multiple unsimplified shuffles the same
Use could be both a splat and a identity though. This patch changes the
Use to a Value and an original Use, so that even if we are looking
through multiple vectors we recognise the splat vs identity vs concat of
each use correctly.
Fixes #180338
Commit: 1c55313f344ff2189500f87c89cec2a3cf2eb5c9
https://github.com/llvm/llvm-project/commit/1c55313f344ff2189500f87c89cec2a3cf2eb5c9
Author: Tony Allevato <tony.allevato at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
Treat `''` and `""` in Gnu-tokenized response files as an empty string argument. (#187566)
This matches the behavior of gcc and also fixes an inconsistency with
the way the same arguments would be parsed by the shell. For example,
this command line passed directly on the shell:
`command -option1 '' -option2`
has three arguments: `"-option1"`, `""`, and `"-option2"`. However, if
these are passed in a Gnu-tokenized response file today:
```
-option1
''
-option2
```
The `''` is discarded and the command incorrectly has two arguments:
`"-option1"` and `"-option2"`.
Commit: 86c3abe85e7d323c8b7fbe4b83442ca3794512c9
https://github.com/llvm/llvm-project/commit/86c3abe85e7d323c8b7fbe4b83442ca3794512c9
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/ADT/Uniformity.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
Log Message:
-----------
[NFC] Rename InstructionUniformity to ValueUniformity (#189935)
Commit: 9dc8f465a42d7187cfff73e56f525560af4f9349
https://github.com/llvm/llvm-project/commit/9dc8f465a42d7187cfff73e56f525560af4f9349
Author: Steven Perron <stevenperron at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/hlsl-resources/CalculateLevelOfDetail.ll
Log Message:
-----------
[SPIRV] Implement the int_spv_resource_calculate_lod* IntrinsicsSPIRV (#188337)
Implements intrinsics used to get the level-of-detail given a texture,
sampler, and a coordinate. It will be used to implement the
corresponding HLSL methods.
Assisted-by: Gemini
Commit: c6b25b4df3efddcc8ab7b781f299aea2ed682434
https://github.com/llvm/llvm-project/commit/c6b25b4df3efddcc8ab7b781f299aea2ed682434
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/include/llvm-libc-types/pthread_rwlock_t.h
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
R libc/src/__support/threads/linux/rwlock.h
A libc/src/__support/threads/raw_rwlock.h
A libc/src/__support/threads/unix_rwlock.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_rwlock_clockrdlock.cpp
M libc/src/pthread/pthread_rwlock_clockwrlock.cpp
M libc/src/pthread/pthread_rwlock_destroy.cpp
M libc/src/pthread/pthread_rwlock_init.cpp
M libc/src/pthread/pthread_rwlock_rdlock.cpp
M libc/src/pthread/pthread_rwlock_timedrdlock.cpp
M libc/src/pthread/pthread_rwlock_timedwrlock.cpp
M libc/src/pthread/pthread_rwlock_tryrdlock.cpp
M libc/src/pthread/pthread_rwlock_trywrlock.cpp
M libc/src/pthread/pthread_rwlock_unlock.cpp
M libc/src/pthread/pthread_rwlock_wrlock.cpp
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_rwlock_test.cpp
M libc/test/src/__support/threads/linux/CMakeLists.txt
A libc/test/src/__support/threads/linux/raw_rwlock_test.cpp
Log Message:
-----------
[libc] separate raw_rwlock and unix_rwlock to make it internally usable (#189773)
Commit: 9b00518419736f698d0a62d0721ee54ceeca4bd7
https://github.com/llvm/llvm-project/commit/9b00518419736f698d0a62d0721ee54ceeca4bd7
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A llvm/include/llvm/MC/MCAsmStreamer.h
M llvm/lib/MC/MCAsmStreamer.cpp
Log Message:
-----------
[MC] Introduce new base class for MCAsmStreamer (#187083)
The class MCAsmBaseStreamer serves as the common base class for streamers
which emit assembly output. It has the same role as MCObjectStreamer has
for streams which emits object files.
Commit: 5d393aee10810d18e30027e22ace3a856d72c0a2
https://github.com/llvm/llvm-project/commit/5d393aee10810d18e30027e22ace3a856d72c0a2
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang-tools-extra/unittests/clang-tidy/CMakeLists.txt
R clang-tools-extra/unittests/clang-tidy/ObjCModuleTest.cpp
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-tidy/BUILD.gn
Log Message:
-----------
[clang-tidy][NFC] Remove the `ObjCModuleTest.cpp` unit test (#185832)
These unit tests only duplicate the tests in
`clang-tools-extra/test/clang-tidy/checkers/objc/forbidden-subclassing.m`.
Commit: ed44820f722aae43f1f00bb3e201300966716973
https://github.com/llvm/llvm-project/commit/ed44820f722aae43f1f00bb3e201300966716973
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/test/Lower/Intrinsics/same_type_as.f90
M flang/test/Lower/Intrinsics/scan.f90
M flang/test/Lower/Intrinsics/secnds.f90
M flang/test/Lower/Intrinsics/selected_int_kind.f90
M flang/test/Lower/Intrinsics/selected_real_kind.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 40) (#189791)
Tests converted from test/Lower/Intrinsics: same_type_as.f9, scan.f90,
scan.f90, selected_int_kind.f90, selected_real_kind.f90
Commit: 0b61cd39e45ad7e0476740a5ecc455e7461488a4
https://github.com/llvm/llvm-project/commit/0b61cd39e45ad7e0476740a5ecc455e7461488a4
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
Log Message:
-----------
[LV] Add epilogue minimum iteration check in VPlan as well. (#189372)
Update LV to also use the VPlan-based addMinimumIterationCheck for the
iteration count check for the epilogue.
As the VPlan-based addMinimumIterationCheck uses VPExpandSCEV, those
need to be placed in the entry block for now, moving vscale * VF * IC to
the entry for scalable vectors.
The new logic also fails to simplify some checks involving PtrToInt,
because they were only simplified when going through generated IR, then
folding some PtrToInt in IR, then constructing SCEVs again. But those
should be cleaned up by later combines, and there is not really much we
can do other than trying to go through IR.
PR: https://github.com/llvm/llvm-project/pull/189372
Commit: c7c9b25e8b4efd338aadaa3c2ad744faa6422964
https://github.com/llvm/llvm-project/commit/c7c9b25e8b4efd338aadaa3c2ad744faa6422964
Author: argmaxin <srcydeveloper at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
Log Message:
-----------
Update ExtractAPIConsumer.cpp (#88285)
Fix small spelling mistake.
Co-authored-by: Srcy Dev <88575889+SrcyDev at users.noreply.github.com>
Commit: 54914a4287ca73bb95e42a6cdf19f5d786eb256f
https://github.com/llvm/llvm-project/commit/54914a4287ca73bb95e42a6cdf19f5d786eb256f
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen] Allow rematerializer to rematerialize at the end of a block (#184339)
This makes the rematerializer able to rematerialize MIs at the end of a
basic block. We achieve this by tracking the parent basic block of every
region inside the rematerializer and adding an explicit target region to
some of the class's methods. The latter removes the requirement that we
track the MI of every region (`Rematerializer::MIRegion`) after the
analysis phase; the class member is therefore deleted.
This new ability will be used shortly to improve the design of the
rollback mechanism.
Commit: c245d764b8bd70ff78044f56b2dea619b0d428dc
https://github.com/llvm/llvm-project/commit/c245d764b8bd70ff78044f56b2dea619b0d428dc
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/ProcessImplicitDefs.cpp
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
A llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
A llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
M llvm/test/CodeGen/X86/issue76416.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
A llvm/test/CodeGen/X86/multi-use-implicit-def.mir
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll
M llvm/test/CodeGen/X86/statepoint-two-results.ll
M llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
M llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
Log Message:
-----------
[CodeGen] Do not remove IMPLICIT_DEF unless all uses have undef flag added (#188133)
Do not remove IMPLICIT_DEF of a physreg unless all uses have an undef
flag added. Previously, only the first use instruction had undef flags
added. This will cause a failure in machine instruction verification.
Multi-instruction uses tested in AMDGPU/multi-use-implicit-def.mir and
X86/multi-use-implicit-def.mir.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 234b8469e92aa3bfcc08e5b7abd6fcbb11a258a6
https://github.com/llvm/llvm-project/commit/234b8469e92aa3bfcc08e5b7abd6fcbb11a258a6
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/lib/Lower/ConvertCall.cpp
A flang/test/Lower/HLFIR/elemental-character-min-max.f90
Log Message:
-----------
[Flang] Compute elemental character MIN/MAX result length in HLFIR (#189464)
This patch fixes lowering of elemental character MIN/MAX in HLFIR.
Previously, these cases could hit a lowering-time TODO
`ElementalIntrinsicCallBuilder::computeDynamicCharacterResultLength` and
abort. This change computes the character result length as the maximum
length of the present actual arguments, allowing valid elemental
character MIN/MAX calls to lower successfully.
Added regression coverage for elemental character MIN/MAX, including
differing-length arguments.
Co-authored-by: Sairudra More <moresair at pe31.hpc.amslabs.hpecorp.net>
Commit: 697ff31fc71fcc895edb077e6fc341761edc0acf
https://github.com/llvm/llvm-project/commit/697ff31fc71fcc895edb077e6fc341761edc0acf
Author: Lei Huang <lei at ca.ibm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/test/CodeGen/PowerPC/vector-rotates.ll
Log Message:
-----------
[PowerPC] Enhance vec_rl() to generate xvrlw (#189023)
Enhance existing builtin vec_rl() to generate the new xvrlw, VSX version
of vrlw, for cpu=future.
Commit: 6f0e961cc2d541e96b1a98c3f196855b0eab2856
https://github.com/llvm/llvm-project/commit/6f0e961cc2d541e96b1a98c3f196855b0eab2856
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Log Message:
-----------
[WebAssembly] Correct operands for NaN/Zero checks in min/max (#189712)
The `pmin` and `pmax` pattern fragments match `vselect`s, meaning that
the generated operands for `relaxed_min` and `relaxed_max` correspond to
operands 1 and 2 of the `vselect` (rather than operands 0 and 1).
Commit: 046e23fa4adaf4cdee23f4f3416d7d57009f19d5
https://github.com/llvm/llvm-project/commit/046e23fa4adaf4cdee23f4f3416d7d57009f19d5
Author: Roy Shi <royitaqi at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/DebugInfo/GSYM/FileWriter.cpp
M llvm/lib/Support/DataExtractor.cpp
Log Message:
-----------
[llvm lib] Fix endian bug in #189098 (#189778)
The bug was added in #189098. Both functions that I added/changed
assumed little-endian host memory layout when reading/writing
non-power-of-two byte sizes (3, 5, 6, 7). On big-endian hosts (SPARC,
s390x), memcpy copies bytes into the MSB end of a uint64_t, leaving the
value in the wrong bit position. Fix by offsetting the memcpy/write
pointer to always target the LSB bytes.
Commit: 364b19322db209f6a465934e7483a6e1dde14043
https://github.com/llvm/llvm-project/commit/364b19322db209f6a465934e7483a6e1dde14043
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
Log Message:
-----------
[RISCV] Add assertions to VSETVLIInfo::hasSEWLMULRatioOnly(). NFC (#189799)
Ensure that we can only call this on valid and not unknown.
Commit: 16255e457c9d5d418bd67543c97204448e195597
https://github.com/llvm/llvm-project/commit/16255e457c9d5d418bd67543c97204448e195597
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
Log Message:
-----------
[RISCV] Add RISCVISD::USATI/SATI to computeKnownBitsForTargetNode/ComputeNumSignBitsForTargetNode. (#189702)
Commit: 9506f20b4dccc6334cc36e04c93033d575cfee52
https://github.com/llvm/llvm-project/commit/9506f20b4dccc6334cc36e04c93033d575cfee52
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCUtils.h
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
A flang/test/Analysis/AliasAnalysis/alias-analysis-acc.mlir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
Log Message:
-----------
[flang][acc] Add AA implementation for acc operations (#189772)
This PR extends flang's alias analysis so it can reason about values
that originate from OpenACC data and privatization operations, including
values passed through block arguments.
Commit: 8a1d6c6f5e421bcade951ce9df4d9d300075cab7
https://github.com/llvm/llvm-project/commit/8a1d6c6f5e421bcade951ce9df4d9d300075cab7
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/test/Driver/linux-ld.c
Log Message:
-----------
clang: driver: update android packed relocation logic (#189758)
Hoist this up from the build system so that users of Android's NDK can
benefit from these various packed relocation encodings depending on
which API level they are targeting.
Link: https://github.com/android/ndk/issues/909
Fixes: https://github.com/android/ndk/issues/2193
Link: https://github.com/android/ndk/issues/2188#issuecomment-3366591142
Link:
https://android.googlesource.com/platform/build/soong/+/d046c2afef086a35d24222b09f4d2c4914e8a2a5/cc/linker.go#548
Commit: b528f6746d4dafdc5975041752b14c0c1714afbc
https://github.com/llvm/llvm-project/commit/b528f6746d4dafdc5975041752b14c0c1714afbc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M offload/test/CMakeLists.txt
Log Message:
-----------
[Offload] Run liboffload unit tests as a part of check-offload (#189731)
Summary:
These are currently only run with check-offload-unit. Make them a part
of the other tests by putting a dependency on it. We did something like
this previously but it was reverted because the tests failed if there
were no GPUs (like in systems that only checked the CPU case) but I
think that has been fixed.
Commit: 5d9eb0c76aec65c159fb104a241545680483212d
https://github.com/llvm/llvm-project/commit/5d9eb0c76aec65c159fb104a241545680483212d
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/include/clang/Basic/OffloadArch.h
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
Log Message:
-----------
[AMDGPU] Define new targets gfx1171 and gfx1172 (#187735)
Commit: 27c85964006ec45bd8215ec3271c79fbda435735
https://github.com/llvm/llvm-project/commit/27c85964006ec45bd8215ec3271c79fbda435735
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
Log Message:
-----------
[win][x64] Unwind v2: When making headroom leave space for the header (#188368)
When the `ensureHeadroom` call was added during unwind v2 info emission,
it didn't take into account that there is a header of 2-bytes before all
the fixups, so not enough space was actually reserved.
Commit: 1e06cd634e849054d1fe11c1493870b2a7ddf1c9
https://github.com/llvm/llvm-project/commit/1e06cd634e849054d1fe11c1493870b2a7ddf1c9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC] Fix uninitialized ReductionRoot in getTreeCost
ReductionRoot was initialized to nullptr instead of the RdxRoot
parameter. This caused two ScaleCost calls (for MinBWs cast cost and
ReductionBitWidth resize cost) to pass nullptr as the user instruction,
and suppressed the "Reduction Cost" line in debug output. In practice
the scale factor is the same because the tree root's main op and the
reduction root share the same basic block, so this is NFC.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/189994
Commit: 015f864215e91d05199fc3c61ef0ee804975d57e
https://github.com/llvm/llvm-project/commit/015f864215e91d05199fc3c61ef0ee804975d57e
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[lldb] Const some ASTContext pointers in TypeSystemClang (NFC) (#189975)
Commit: f918af7a702f32e35b2fb505de24801d06266ed4
https://github.com/llvm/llvm-project/commit/f918af7a702f32e35b2fb505de24801d06266ed4
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/lib/Semantics/check-omp-atomic.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-utils.cpp
Log Message:
-----------
[flang][OpenMP] Remove qualification from evaluate::SymbolVector, NFC (#189984)
`SymbolVector` is defined in flang/Semantics/symbol.h, so there is no
need to use a namespace-qualified name for it in lib/Semantics.
Commit: 82e84940701b3e7bba9069e99f8247e7434973bc
https://github.com/llvm/llvm-project/commit/82e84940701b3e7bba9069e99f8247e7434973bc
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
Log Message:
-----------
[VPlan] Avoid unnecessary BTC SymbolicValue creation (NFC) (#189929)
Don't unnecessarily create a backedge-taken-count SymbolicValue. This
allows us to simplify some code.
Commit: 5c36ef884321e293714da6e06239345ba2805d3c
https://github.com/llvm/llvm-project/commit/5c36ef884321e293714da6e06239345ba2805d3c
Author: yebinchon <86588366+yebinchon at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
A flang/test/HLFIR/bufferize-associate-block-ordering.fir
Log Message:
-----------
[flang] fix a dangling else in allOtherUsesAreSafeForAssociate (#189748)
Fix a dangling if condition in allOtherUsesAreSafeForAssociate that
caused isBeforeInBlock to be called even when instructions were known to
not be in the same block, triggering an assertion. The condition was
changed to else if and added brackets.
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
Commit: 44979bedf0b65db49c7ea67f5d40b0d4c44b06ea
https://github.com/llvm/llvm-project/commit/44979bedf0b65db49c7ea67f5d40b0d4c44b06ea
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Strip dead code in isUniformAcrossVFsAndUFs (NFC) (#189687)
Checking a VPInstruction for scalar-cast is equivalent to checking
opcode against Instruction::isCast via preservesUniformity.
Commit: 91adaeceb162357a33e2ea6155cb13a4198a981a
https://github.com/llvm/llvm-project/commit/91adaeceb162357a33e2ea6155cb13a4198a981a
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A clang/include/clang/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenMP/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/Transforms/omp-mark-declare-target.cir
M clang/tools/cir-opt/CMakeLists.txt
M clang/tools/cir-opt/cir-opt.cpp
M clang/tools/cir-translate/CMakeLists.txt
M clang/tools/cir-translate/cir-translate.cpp
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
Log Message:
-----------
[CIR][MLIR][OpenMP] Enable the MarkDeclareTarget pass for ClangIR (#189420)
This patch enables the MarkDeclareTarget for CIR by adding the pass to
the lowerings and attaching the declare target interface to the
cir::FuncOp. The MarkDeclareTarget is also generalized to work on the
FunctionOpInterface instead of func::Op since it needs to be able to
handle cir::FuncOp as well.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: d7e129dffbe1d8cdafd6731a4ff130da68deb40b
https://github.com/llvm/llvm-project/commit/d7e129dffbe1d8cdafd6731a4ff130da68deb40b
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
[SelectionDAGBuilder] Only check VPCmp for NaNs in fp comparisons (#189749)
`getFCmpCodeWithoutNaN` should only be used for FP comparisons (which is
also the only context in which `isKnownNeverNaN` makes sense).
Commit: 166806e792002325814e66cb05fd38540f65cc21
https://github.com/llvm/llvm-project/commit/166806e792002325814e66cb05fd38540f65cc21
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/mod-file.h
M flang/lib/Semantics/resolve-names.cpp
R flang/test/Semantics/Inputs/modfile84.f90
R flang/test/Semantics/modfile84.f90
Log Message:
-----------
Revert "[flang] Preserve UseErrorDetails in module files (#189423)" (#189997)
This reverts commit fce3a66f5e2f247890c57ac01a2c9847358c0f27. It broke a
Fortran application in our in-house testing.
Commit: 45b932a2d452c997d98b57e1aa31bc4951c5e9f4
https://github.com/llvm/llvm-project/commit/45b932a2d452c997d98b57e1aa31bc4951c5e9f4
Author: Katherine Rasmussen <krasmussen at lbl.gov>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/docs/Extensions.md
Log Message:
-----------
[flang] Update Flang Extension doc to reflect previous change (#188088)
Update Flang Extension doc to remove note about a warning that was
removed in a previous PR (PR #178088). It is an oversight that this doc
change was not made in that previous PR. The oversight was only recently
discovered and has led to this PR.
Commit: 66d1dc48ad7bc344e2656fcf3afb7470c70a9382
https://github.com/llvm/llvm-project/commit/66d1dc48ad7bc344e2656fcf3afb7470c70a9382
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbutil.py
Log Message:
-----------
Revert "[lldb] Increase timeout on lldbutil.wait_for_file_on_target" (#190004)
Reverts llvm/llvm-project#189471 because it seems like this breaks the
Sanitized bots:
https://github.com/llvm/llvm-project/pull/189471#issuecomment-4171688975
Commit: 33ca7a4667d7f60a4692a2e03b3de94f66ff0d10
https://github.com/llvm/llvm-project/commit/33ca7a4667d7f60a4692a2e03b3de94f66ff0d10
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-binop.ll
Log Message:
-----------
[LICM] Reassociate add/sub expressions to hoist invariant computations (#183082)
While `sub` is not associative, we can still reassociate `add` and
`sub`.
## Alive2 proofs
| Case | Transform | Proof |
|------|-----------|-------|
| 1 | `(x + c1) - c2` => `x + (c1 - c2)` |
[proof](https://alive2.llvm.org/ce/z/iofzYy) |
| 2 | `(x - c1) - c2` => `x - (c1 + c2)` |
[proof](https://alive2.llvm.org/ce/z/U4K_tE) |
| 3 | `(x - c1) + c2` => `x + (c2 - c1)` |
[proof](https://alive2.llvm.org/ce/z/moiJVw) |
Commit: 7c4b6dee7401769a359d2922629f7cd0103d6c72
https://github.com/llvm/llvm-project/commit/7c4b6dee7401769a359d2922629f7cd0103d6c72
Author: Sadaf Ebrahimi <sadafebrahimi at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
Log Message:
-----------
[scudo] Ensure that reallocate copies everything
getUsableSize returns the actual capacity of the underlying block, which
may be larger than the size originally requested by the user. If the
user writes data into this extra space accessible via getUsableSize and
subsequently calls reallocate, the existing implementation only copies
the original requested number of bytes. This resulted in data loss for
any information stored beyond the requested size but within the usable
bounds.
Commit: 996157cb17a0f608590bdd2b3d8560d798acc188
https://github.com/llvm/llvm-project/commit/996157cb17a0f608590bdd2b3d8560d798acc188
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
Fully disable `preserve_none` under ASan (#190001)
This crashes Clang 19, 21, and 22 on x86-64 that I've tested and I don't
have a ready-to-test build of any other versions but it seems much safer
to just disable for now.
Commit: 26a5a494c3c97219ea94fd0ca47a648ab8b32472
https://github.com/llvm/llvm-project/commit/26a5a494c3c97219ea94fd0ca47a648ab8b32472
Author: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] factor out repetitive code in GCD test (NFCI) (#189461)
The logic for recursively investigating the source and destination
AddRecs in GCD test is the same and can be factored out.
Commit: 07fc9b8155b4913c8fb235ae05898893ec7d388f
https://github.com/llvm/llvm-project/commit/07fc9b8155b4913c8fb235ae05898893ec7d388f
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_minnum, vp_maxnum (#189899)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off 2 intrinsics from #179622.
Commit: b71eacea7687f68c11299e3bda5654fbbaa1e20e
https://github.com/llvm/llvm-project/commit/b71eacea7687f68c11299e3bda5654fbbaa1e20e
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 91adaec (#189998)
This fixes 91adaeceb162357a33e2ea6155cb13a4198a981a.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 24b6ee90c1eed2f6f9f5d086b74a4e5fd55e0717
https://github.com/llvm/llvm-project/commit/24b6ee90c1eed2f6f9f5d086b74a4e5fd55e0717
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Assert on non-FP operand to `computeKnownFPClass` (#189752)
Assert correct usage of `computeKnownFPClass` or users (i.e.,
`isKnownNeverNaN`).
Commit: fbf484009c782a3ecb8bae6526d4c10d006365fc
https://github.com/llvm/llvm-project/commit/fbf484009c782a3ecb8bae6526d4c10d006365fc
Author: Vito Secona <77039267+secona at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Pipelines/Passes.h
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
Log Message:
-----------
[mlir][sparse] add GPU num threads to sparsifier options (#189078)
This change adds a `gpu-num-threads` option to the sparsifier. This
allows users to specify the number of threads used for GPU codegen,
similar to the `num-threads` option in the `-sparse-gpu-codegen` pass.
Commit: e55c85341d9f757021b4f31b910d2ad2175f7e6c
https://github.com/llvm/llvm-project/commit/e55c85341d9f757021b4f31b910d2ad2175f7e6c
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/lib/Lower/Bridge.cpp
A flang/test/Lower/OpenMP/requires-usm.f90
Log Message:
-----------
[Flang][OpenMP] Extend omp requires detection in Bridge.cpp (#188106)
Currently, we do not check the module for requires directives, which
means we'll miss these and not set them on the OpenMP module.
Otherwise, due to the first come first serve method we currently check
the symbols, there is certain formats that would mean the compiler would
miss that a user had specified requires somewhere in the module. This is
partially but not fully avoided by the Semantics layer pushing the
requires on to the top most PFT symbol, as it is entirely possible to
create a legal Fortran program where you could have two or more of these
(e.g. module and main program in one file, standalone funcitons
intermixed with modules or main program). Some examples of this are
shown in the added Fortran test. This PR opts to resolve it by gathering
all of the relevant symbols and processing them.
Also removed gathering from BlockDataUnit as I don't think these symbols
ever get the requires applied.
Commit: 54e5803d0231211decb64105b10b4701dce938c2
https://github.com/llvm/llvm-project/commit/54e5803d0231211decb64105b10b4701dce938c2
Author: Zhige Chen <zhige_chen at outlook.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/tools/llubi/lib/CMakeLists.txt
A llvm/tools/llubi/lib/ExecutorBase.cpp
A llvm/tools/llubi/lib/ExecutorBase.h
M llvm/tools/llubi/lib/Interpreter.cpp
Log Message:
-----------
[llubi] Extract reusable methods of InstExecutor into ExecutorBase (#186976)
This PR extracts the non-visitor methods of class InstExecutor into a
separate class ExecutorAPI. This reorganization allows library functions
(and any future extensions) to reuse the functionality of InstExecutor
without introducing cyclic dependencies.
See also #185645 and #185817.
Commit: 6c7c575556cbcd49d3fe6321b3bf55c30111b4d9
https://github.com/llvm/llvm-project/commit/6c7c575556cbcd49d3fe6321b3bf55c30111b4d9
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
Log Message:
-----------
[clang] fix OutputSemantic list in HLSL (#185550)
Normally sane front-ends with the common calling-conventions avoid
having multiple sret with a return value, so this is NFCI. However,
multiple can be valid. This rewrites an odd looking DenseMap of one
element that was needed for iteration into a more sensible vector.
Noted in https://github.com/llvm/llvm-project/pull/181740 review.
Commit: 01cf792d1e68b28104c777927acf18fda3d41a95
https://github.com/llvm/llvm-project/commit/01cf792d1e68b28104c777927acf18fda3d41a95
Author: PiJoules <leonardchan at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/test/SemaCXX/using-if-exists.cpp
Log Message:
-----------
[clang] Fix conflicting declaration error with using_if_exists (#167646)
This fixes an issue with using_if_exists where we would hit `conflicts
with target of using declaration already in scope` with a
using_if_exists attribute referring to a declaration which did not
exist. That is, if we have `using ::bar
__attribute__((using_if_exists))` but `bar` is not in the global
namespace, then nothing should actually be declared here.
This PR contains the following changes:
1. Ensure we only diagnose this error if the target decl and [Non]Tag
decl can be substitutes for each other.
2. Prevent LookupResult from considering UnresolvedUsingIfExistsDecls in
the event of ambiguous results.
3. Update tests. This includes the minimal repo for a regression test,
and changes to existing tests which also seem to exhibit this bug.
Fixes #85335
---------
Co-authored-by: Petr Hosek <phosek at google.com>
Commit: 3b3b556a12a79109785394233779d89982068705
https://github.com/llvm/llvm-project/commit/3b3b556a12a79109785394233779d89982068705
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[mlir][NVVM] Add managed attribute for global variables (#189751)
Add support for the `nvvm.managed` attribute on `llvm.mlir.global` ops.
When present, the LLVM IR translation emits `!nvvm.annotations` metadata
with `!"managed"` for the global variable, which the NVPTX backend uses
to generate `.attribute(.managed)` in PTX output.
This enables CUDA managed memory support for frontends that lower
through MLIR.
Commit: 573935d7b3a2565605b22edd8a7a60d6d6638244
https://github.com/llvm/llvm-project/commit/573935d7b3a2565605b22edd8a7a60d6d6638244
Author: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-delta-signed-min.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-overflow.ll
Log Message:
-----------
[DA] Overflow check in WeakCrossing Delta calculation (#185046)
When subtracting the constant part of two addrecs, we need to ensure the
calculation won't overflow. If it may overflow, we conservatively stop
the analysis and return false.
Commit: b5745e1e28c0503069804ebb8921a4b66a4d0a3d
https://github.com/llvm/llvm-project/commit/b5745e1e28c0503069804ebb8921a4b66a4d0a3d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/config/gpu/amdgpu/entrypoints.txt
M libc/config/gpu/amdgpu/headers.txt
M libc/config/gpu/nvptx/entrypoints.txt
M libc/config/gpu/nvptx/headers.txt
Log Message:
-----------
[libc] Support basic 'complex.h' functionality on GPUs (#189999)
Summary:
This PR adds the basic complex functions needed by some targets. This is
an attempt to provide the standard interface needed by
'https://github.com/llvm/llvm-project/pull/187831'
Commit: d736e1bd0b98706ced9b689211c8df39abb7cd46
https://github.com/llvm/llvm-project/commit/d736e1bd0b98706ced9b689211c8df39abb7cd46
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/atomic.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/floating-point.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/integer.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/arithmetic.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/bitwise.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/comparison.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/conversion.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fma.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fp.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mask.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/minmax.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mul-div.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/permutation.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/reduction.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vle-vse-vlm.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlse-vsse.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlseg-vsseg.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlxe-vsxe.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbb.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbc.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkg.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkned.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvknhb.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksed.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksh.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zba.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbb.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbs.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfhmin.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
Log Message:
-----------
[RISCV][MCA] Update sifive-p670 tests to consume input files instead (#189785)
Use the new input file system for `sifive-p670`'s llvm-mca tests. Some
of the vector crypto extension tests are left intact, due to the lack of
corresponding input files, and moved under the `rvv` sub-directory.
Commit: c794742bd7f41c80b764b58019258cafd87f4a6a
https://github.com/llvm/llvm-project/commit/c794742bd7f41c80b764b58019258cafd87f4a6a
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang-rt/lib/cuda/registration.cpp
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-device-address.mlir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
Log Message:
-----------
[flang][cuda] Support non-allocatable module-level managed variables (#189753)
Add support for non-allocatable module-level CUDA managed variables
using pointer indirection through a companion global in
__nv_managed_data__. The CUDA runtime populates this pointer with the
unified memory address via __cudaRegisterManagedVar and
__cudaInitModule.
- Create a .managed.ptr companion global in the __nv_managed_data__
section and register it with _FortranACUFRegisterManagedVariable
- Call __cudaInitModule once after all variables are registered, only
when non-allocatable managed globals are present, to populate managed
pointers
- Annotate managed globals in gpu.module with nvvm.managed for PTX
.attribute(.managed) generation
- Suppress cuf.data_transfer for assignments to/from non-allocatable
module managed variables, since cudaMemcpy would target the shadow
address rather than the actual unified memory
- Preserve cuf.data_transfer for device_var = managed_var assignments
where explicit transfer is still required
Note: This PR depends on
[#189751](https://github.com/llvm/llvm-project/pull/189751) (MLIR:
nvvm.managed attribute).
Commit: e5d57ce707e388219f0341002b8d8c908095bad1
https://github.com/llvm/llvm-project/commit/e5d57ce707e388219f0341002b8d8c908095bad1
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaObjC.cpp
R clang/test/Sema/gh183974.c
Log Message:
-----------
Revert "[Clang] Fix assertion when __block is used on global variables in C mode" (#190018)
Reverts llvm/llvm-project#183988
Breaks ObjC code, see
https://github.com/llvm/llvm-project/pull/183988#issuecomment-4134934748
Commit: 35ceec6a785f623b0e7f20b46297a2509c4a4e5b
https://github.com/llvm/llvm-project/commit/35ceec6a785f623b0e7f20b46297a2509c4a4e5b
Author: lntue <lntue at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/config/config.json
M libc/config/gpu/config.json
M libc/src/__support/CMakeLists.txt
M libc/src/__support/time/CMakeLists.txt
M libc/src/time/linux/CMakeLists.txt
M libc/src/unistd/CMakeLists.txt
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/TestLogger.cpp
Log Message:
-----------
[libc] Finetune libc.src.__support.OSUtil.osutil dependency. (#189501)
Several key targets unconditionally depend on `OSUtil.osutil` target,
causing errors when it is unnecessarily linked, or not available. This
PR fine-tuning the dependency on `OSUtil.osutil` to cleanly decouple
those targets, and gracefully skip targets that need `osutil`. Main
changes include:
* Make `LIBC_COPT_USE_C_ASSERT` to a cmake config, allowing
`LIBC_ASSERT` to use system's `assert` and not depending on `osutil`.
* Adjust cmake dependency for the following targets:
- libc.src.__support.libc_assert
- libc.src.__support.time.*
- libc.src.time.linux.*
- libc.src.unistd.*
- LibcTest
* Give an option for `TestLogger` to use system's `fprintf` instead of
`osutil`.
Commit: 150aa6f2d385d9c1ffa378e16595d7a738f921fc
https://github.com/llvm/llvm-project/commit/150aa6f2d385d9c1ffa378e16595d7a738f921fc
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
Log Message:
-----------
[MLIR][XeGPU] Add support for convert layout with scalar in Sg to WI distribution (#189721)
Commit: 34028294e49b732c15c75e3b812f3868e6a89da8
https://github.com/llvm/llvm-project/commit/34028294e49b732c15c75e3b812f3868e6a89da8
Author: Leandro Lacerda <leandrolcampos at yahoo.com.br>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M offload/include/Shared/RefCnt.h
M offload/liboffload/API/Event.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa_ext_amd.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/event/olGetEventElapsedTime.cpp
Log Message:
-----------
[Offload] Add support for measuring elapsed time between events (#186856)
This patch adds `olGetEventElapsedTime` to the new LLVM Offload API, as
requested in
[#185728](https://github.com/llvm/llvm-project/issues/185728), and adds
the corresponding support in `plugins-nextgen`.
A main motivation for this change is to make it possible to measure the
elapsed time of work submitted to a queue, especially kernel launches.
This is relevant to the intended use of the new Offload API for
microbenchmarking GPU libc math functions.
### Summary
The new API returns the elapsed time, in milliseconds, between two
events on the same device.
To support the common pattern `create start event → enqueue kernel →
create end event → sync end event → get elapsed time`, `olCreateEvent`
now always creates and records a backend event through the device
interface. For backends that materialize real event state, this gives
the event concrete backend state that can be used for elapsed-time
measurement. For backends that do not materialize backend event state,
`EventInfo` may still remain null and existing event operations continue
to treat such events as trivially complete.
Previously, an event created on an empty queue could be represented only
as a logical event. That representation was sufficient for sync and
completion queries, but it was not suitable for elapsed-time measurement
because there was no backend event state to timestamp. The new behavior
preserves the meaning of completion of prior work while also allowing
backends with timing support to attach real event state.
### Changes in `plugins-nextgen`
#### Common interface
Add elapsed-time support to the common device and plugin interfaces:
* `GenericPluginTy::get_event_elapsed_time`
* `GenericDeviceTy::getEventElapsedTime`
* `GenericDeviceTy::getEventElapsedTimeImpl`
#### AMDGPU
* Add the required ROCr declarations and wrappers.
* Enable queue profiling at queue creation time.
* Record events by enqueuing a real barrier marker packet on the stream.
* Retain the timing signal needed to query the recorded marker later.
* Implement `getEventElapsedTimeImpl` using
`hsa_amd_profiling_get_dispatch_time`, converting the result to
milliseconds with `HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY`.
This follows the ROCm/HIP approach of enabling queue profiling at HSA
queue creation time, while keeping the AMDGPU queue path simpler than
the lazy-enable alternative discussed during review.
#### CUDA
* Add the required CUDA driver declarations and wrappers.
* Implement `getEventElapsedTimeImpl` with `cuEventElapsedTime`.
#### Host
* Add `getEventElapsedTimeImpl` that stores `0.0f` in the output
pointer, when present, and returns success.
Reason: the host plugin does not materialize backend event state and
already treats event operations as trivially successful. Returning
`0.0f` preserves that model without introducing a new failure mode.
#### Level Zero
* Add `getEventElapsedTimeImpl`, but leave it unimplemented.
Reason: the Level Zero plugin currently does not provide standalone
backend event support for this event model. For example, `waitEventImpl`
/ `syncEventImpl` are still unimplemented there.
---------
Signed-off-by: Leandro Augusto Lacerda Campos <leandrolcampos at yahoo.com.br>
Signed-off-by: Leandro A. Lacerda Campos <leandrolcampos at yahoo.com.br>
Commit: 75333a09818147f72387a6f93e3248595ab88048
https://github.com/llvm/llvm-project/commit/75333a09818147f72387a6f93e3248595ab88048
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/CMakeLists.txt
A libc/shared/CMakeLists.txt
Log Message:
-----------
[libc] Install the RPC headers so they can be used without LLVM source (#189996)
Summary:
The RPC headers are completely freestanding and can be installed and
used. This just places them in the standard compiler install directory
along with everything else. We put it under `shared/` so the usage
matches with using the upstream version. People using the installed
version will need to manuall `-isystem` into the include directory, but
this is part for the course for these LLVM extra headers.
Commit: 8ea475fdf923619760108a2109cc4dcee8041942
https://github.com/llvm/llvm-project/commit/8ea475fdf923619760108a2109cc4dcee8041942
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/include/clang/Serialization/ModuleCache.h
M clang/lib/DependencyScanning/InProcessModuleCache.cpp
M clang/lib/Serialization/ModuleCache.cpp
M clang/lib/Serialization/ModuleManager.cpp
Log Message:
-----------
[clang] Introduce `ModuleCache::read()` (#188876)
This PR introduces new `ModuleCache` API for reading PCM files. This
makes it so that we don't go through the `FileManager` and VFS, which is
problematic downstream. We interpose a VFS that unintentionally shuffles
implicitly-built modules in and out of the CAS database, leading to some
unnecessary storage and runtime overhead. Moreover, this (together with
a reading API) will enable adding a caching layer into the
`InProcessModuleCache` implementation, hopefully reducing IO cost.
Commit: 873d6bc3b415f1c2d942bbf4e4219c4bdcd4f2f8
https://github.com/llvm/llvm-project/commit/873d6bc3b415f1c2d942bbf4e4219c4bdcd4f2f8
Author: Marco Elver <elver at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Analysis/ThreadSafety.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
Log Message:
-----------
Thread Safety Analysis: Drop call-based alias invalidation (#187691)
Local variables passed by non-const pointer or reference to a function
were previously invalidated in the LocalVariableMap (VarMapBuilder), on
the assumption that the callee might change what they point to. This
caused false positives when the function also carries ACQUIRE/RELEASE
annotations: handleCall translates those annotations with the pre-call
context, while subsequent guard checks use the post-invalidation
context, producing an expansion mismatch and a spurious warning.
The invalidation rules were a heuristic with significant complexity
(including a special-case carve-out for std::bind/bind_front) and
unclear benefit. Instead of adding more heuristics, drop the
alias-invalidation rules entirely.
Discussion: https://github.com/llvm/llvm-project/pull/183640
Commit: 09c4d8ce0f9b9125d53340b7f9b7a5b0cf70f866
https://github.com/llvm/llvm-project/commit/09c4d8ce0f9b9125d53340b7f9b7a5b0cf70f866
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
A clang/test/CodeGenCXX/dead-on-return-deleting-destructor.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/ptrauth-apple-kext-indirect-virtual-dtor-call.cpp
Log Message:
-----------
[Clang] Fix miscompile with custom operator delete (#190017)
See discussion in #183347.
Added a separate test case rather than reusing
destructor-dead-on-return.cpp as we need to test functionality of the
deleting destructor which update_cc_test_checks.py does not add check
lines for.
Commit: 934438ad86fcd623e100a74ddfe7f05e829a5497
https://github.com/llvm/llvm-project/commit/934438ad86fcd623e100a74ddfe7f05e829a5497
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[VPlanPatternMatch] Unify and clarify m_Isa (NFC) (#189941)
Commit: 95a76886c1b5da2af87bb28541d34def63a98d82
https://github.com/llvm/llvm-project/commit/95a76886c1b5da2af87bb28541d34def63a98d82
Author: Jeff Sandoval <jeffreysandoval at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir
Log Message:
-----------
[OpenMP][MLIR] Fix GPU teams reduction buffer size for by-ref reductions (#185460)
The `ReductionDataSize` field in `KernelEnvironmentTy` and the
`MaxDataSize` used to compute the `reduce_data_size` argument to
`__kmpc_nvptx_teams_reduce_nowait_v2` were both computed using pointer
types for by-ref reductions instead of the actual element types. This
caused the global teams reduction buffer to be undersized relative to
the offsets used by the copy/reduce callbacks, resulting in
out-of-bounds accesses faults at runtime.
For example, a by-ref reduction over `[4 x i32]` (16 bytes) would
allocate buffer slots based on `sizeof(ptr)` = 8 bytes, but the
generated callbacks would access 16 bytes per slot.
Fix both computation sites:
1. In MLIR's `getReductionDataSize()`, use
`DeclareReductionOp::getByrefElementType()` instead of `getType()` when
the reduction is by-ref, so the reduction buffer struct layout (and more
importantly its size) matches that emitted by the `OMPIRBuilder`.
2. In `OMPIRBuilder::createReductionsGPU()`, use
`ReductionInfo::ByRefElementType` instead of `ElementType` for by-ref
reductions when computing `MaxDataSize`. It seems that `MaxDataSize`
isn't actually used in the deviceRTL, but it's better to fix it to avoid
future propagation of this bug.
Finally, add CHECK lines to the existing array-descriptor reduction test
to verify both the kernel environment `ReductionDataSize` and the
`reduce_data_size` call argument reflect the actual element type size.
Assisted-by: Claude Opus 4.6
---------
Co-authored-by: Jeffrey Sandoval <jeffrey.sandoval at hpe.com>
Commit: 75c6f4791c8c1031e5ab170a9987c4d300026e1e
https://github.com/llvm/llvm-project/commit/75c6f4791c8c1031e5ab170a9987c4d300026e1e
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Serialization/ModuleCache.h
M clang/lib/DependencyScanning/InProcessModuleCache.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Serialization/ModuleCache.cpp
Log Message:
-----------
[clang] Introduce `ModuleCache::write()` (#188877)
This introduces new `ModuleCache` interface for writing PCM files.
Together with #188876, this will enable adding a caching layer into the
`InProcessModuleCache` implementation, hopefully reducing IO cost.
Moreover, this makes it super explicit that the PCM is written before
its timestamp, which is an important invariant that we've broken before.
Commit: 401ba6df84f66885fdf68d4d1fb52b422c338b89
https://github.com/llvm/llvm-project/commit/401ba6df84f66885fdf68d4d1fb52b422c338b89
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
Log Message:
-----------
[MLIR][XeGPU] Add Layout Propagation support for multi-reduction/reduction op with scalar result (#189133)
This PR add Layout Propagation support for multi-reduction/reduction op
with scalar result:
1) Enhance setupMultiReductionResultLayout() and
LayoutInfoPropagation::visitVectorMultiReductionOp() to support scalar
result
2) Add propagation support for vector.reduction op at the lane level,
since the op is only introduced at the lane level.
Commit: 84f23eb3113f2e75d1a2e45db1b5c570a5d2f4c5
https://github.com/llvm/llvm-project/commit/84f23eb3113f2e75d1a2e45db1b5c570a5d2f4c5
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/config/config.json
M libc/config/gpu/config.json
M libc/src/__support/CMakeLists.txt
M libc/src/__support/time/CMakeLists.txt
M libc/src/time/linux/CMakeLists.txt
M libc/src/unistd/CMakeLists.txt
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/TestLogger.cpp
Log Message:
-----------
Revert "[libc] Finetune libc.src.__support.OSUtil.osutil dependency." (#190033)
Reverts llvm/llvm-project#189501
Buildbot failure on libc for GPU buildbots
Commit: 791e68a6ad48201daff91ad7083803c1393395bd
https://github.com/llvm/llvm-project/commit/791e68a6ad48201daff91ad7083803c1393395bd
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-prio-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
M llvm/test/CodeGen/MLRegAlloc/dev-mode-prio-logging.ll
Log Message:
-----------
[MLGO] Update regalloc tests after c245d764b8bd70ff78044f56b2dea619b0… (#190025)
…d428dc
This caused some codegen changes that caused different calculations in
places. Update the tests to adapat to the changes.
Commit: c5f67a0128a928af609b68e3b7d695037e306a84
https://github.com/llvm/llvm-project/commit/c5f67a0128a928af609b68e3b7d695037e306a84
Author: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] Perform `nsw` check for SIV AddRecs earlier (NFCI) (#189740)
The repetitive code at the start of each SIV test can be factored out to
`testSIV` function
Commit: a89c778a8b4639bc2efc3dfde5a10e1db4a9e9d5
https://github.com/llvm/llvm-project/commit/a89c778a8b4639bc2efc3dfde5a10e1db4a9e9d5
Author: Tharun V K <40231849+tharunvk at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Add SpaceBeforeEnumUnderlyingTypeColon for enum underlying types (#189011)
Introduce a new formatting option to control spacing before enum
underlying type colons. This preserves existing behavior while
allowing independent control from inheritance colon spacing.
Previously, enum underlying type colons were not configurable.
Fixes #188734
---------
Co-authored-by: Tharun V K <Tharun.V.K at ibm.com>
Commit: 4e76a7959493b97e6881f476278d43d1c67406ef
https://github.com/llvm/llvm-project/commit/4e76a7959493b97e6881f476278d43d1c67406ef
Author: Eugene Shalygin <eugene.shalygin at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] fix aligning inheritance lists and binary operator operands with UT_AlignWithSpaces (#189218)
fix aligning inheritance lists with UT_AlignWithSpaces
fix aligning binary operator operands
---------
Co-authored-by: Eugene Shalygin <e.shalygin at abberior-instruments.com>
Commit: 2b87d02b035b97940474d0b3b27f3dcdb8934623
https://github.com/llvm/llvm-project/commit/2b87d02b035b97940474d0b3b27f3dcdb8934623
Author: Thorsten Klein <thorsten.klein at bshg.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
Log Message:
-----------
[clang-tidy] Properly escape printed clang-tidy command in `run-clang-tidy.py` (#189974)
The `run-clang-tidy.py` script now uses `shlex.join()` to construct the
command string for printing.
This ensures that arguments containing shell metacharacters, such as the
asterisk in `--warnings-as-errors=*`, are correctly quoted. This allows
the command to be safely copied and pasted into any shell for manual
execution, fixing errors previously seen with shells like `fish` that
are strict about wildcard expansion.
Before:
```
[ 1/15][0.2s] /usr/bin/clang-tidy -p=/home/user/work/project/build --warnings-as-errors=* /home/user/work/project/src/main.cpp
```
Note: When running this command in fish shell you get some error like
`fish: No matches for wildcard '--warnings-as-errors=*'. See `help
wildcards-globbing``
After:
```
[ 1/15][0.2s] /usr/bin/clang-tidy -p=/home/user/work/project/build '--warnings-as-errors=*' /home/user/work/project/src/main.cpp
```
Commit: d6d0876d1a9aa4364a9f684d3923253bd626e767
https://github.com/llvm/llvm-project/commit/d6d0876d1a9aa4364a9f684d3923253bd626e767
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[NFC][SelectionDAG] Refactor out common default `DemandedElts` calculation (#190031)
Deduplicating the repeated pattern
```cpp
APInt DemandedElts = VT.isFixedLengthVector()
? APInt::getAllOnes(VT.getVectorNumElements())
: APInt(1, 1);
```
in SelectionDAG.
Commit: 9f500046511e6e85345d9229bb2d4d2e627bb9d4
https://github.com/llvm/llvm-project/commit/9f500046511e6e85345d9229bb2d4d2e627bb9d4
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
M mlir/test/Dialect/XeGPU/peephole-optimize.mlir
Log Message:
-----------
[MLIR][XeGPU] Enhance the peephole optimization to remove the convert_layout after multi-reduction rewrite (#188849)
Commit: b75bf1e722b8dfeabe41074819786d7540f7466e
https://github.com/llvm/llvm-project/commit/b75bf1e722b8dfeabe41074819786d7540f7466e
Author: Marco Elver <elver at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Analysis/ThreadSafety.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
Log Message:
-----------
Revert "Thread Safety Analysis: Drop call-based alias invalidation (#187691)" (#190041)
This reverts commit 873d6bc3b415f1c2d942bbf4e4219c4bdcd4f2f8.
This causes Linux kernel build to fail because it relied on
alias-invalidation in kernel/core/sched.c.
Commit: 478a6abc0ceea812c9486d13fda4afbe876c670f
https://github.com/llvm/llvm-project/commit/478a6abc0ceea812c9486d13fda4afbe876c670f
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
Log Message:
-----------
[lldb/test] Codesign executables built with custom Makefile rules (#189902)
Tests with custom a.out targets in their Makefile (i.e.
`TestBSDArchives.py`) bypass the standard Makefile.rules linking step
where `CODESIGN` is applied. This leaves the binary unsigned, causing
the process to get kill it on remote darwin devices.
This adds a codesigning step to the all target in Makefile.rules that
signs both $(EXE) and a.out if they exist. This ensures all test
binaries are signed regardless of how they were built.
rdar://173840592
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 6c923741c1278348b257856ecf480124894997ba
https://github.com/llvm/llvm-project/commit/6c923741c1278348b257856ecf480124894997ba
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll
Log Message:
-----------
ValueTracking: llvm.amdgcn.fract cannot introduce overflow (#189002)
This returns a value with an absolute value less than 1.
Commit: c6669c4993ee591e2414e3190cc8f0d623c1357a
https://github.com/llvm/llvm-project/commit/c6669c4993ee591e2414e3190cc8f0d623c1357a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
Log Message:
-----------
[SLP] Guard FMulAdd conversion to require single-use/non-reordered FMul operands
The FMulAdd (CombinedVectorize) transformation in transformNodes() marks
an FMul child entry with zero cost, assuming it is fully absorbed into
the fmuladd intrinsic. However, when any FMul scalar has multiple uses
(e.g., also stored separately), the FMul must survive as a separate
node.
Reviewers: hiraditya, RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/189692
Commit: a9df7c71866d379ea8bdd88c14bafcce90553add
https://github.com/llvm/llvm-project/commit/a9df7c71866d379ea8bdd88c14bafcce90553add
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
Log Message:
-----------
[AMDGPU] True16 support for bf16 clamp pattern on gfx1250 (#190036)
Commit: 7d24b175ebe20b427dddbee5bf0e77bd7d0657f6
https://github.com/llvm/llvm-project/commit/7d24b175ebe20b427dddbee5bf0e77bd7d0657f6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir
Log Message:
-----------
[RISCV] Add SATI_RV64/USATI_RV64 to RISCVOptWInstrs. (#190030)
Note the immediates for these 2 instructions in their MachineInstr
representations both use the type width. The SATI_RV64 binary encoding
and the RISCVISD::SATI encoding uses the type width minus one.
Assisted-by: Claude Sonnet 4.5
Commit: 1a1fbf967addf3a1d7837a8f75fb3414daa34e73
https://github.com/llvm/llvm-project/commit/1a1fbf967addf3a1d7837a8f75fb3414daa34e73
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
Log Message:
-----------
[MLIR][XeGPU] Support round-robin layout for constant and broadcast in wg-to-sg distribution (#189798)
As title.
Commit: b3ca423a78ec436936834170cd8b96a25d3f8b7e
https://github.com/llvm/llvm-project/commit/b3ca423a78ec436936834170cd8b96a25d3f8b7e
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
Log Message:
-----------
[MLIR][Vector] Enhance vector.multi_reduction unrolling to handle scalar result (#188633)
Previously, UnrollMultiReductionPattern bailed out when all the
dimensions were reduced to a scalar. This PR adds support for this case
by tiling the source vector and chaining partial reductions through the
accumulator operand.
Commit: e5a7a9a95ffda04e4ce2398d1950662873b8cd65
https://github.com/llvm/llvm-project/commit/e5a7a9a95ffda04e4ce2398d1950662873b8cd65
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[Fuchsia] Cortex-m33 runtime libraries hard float ABI (#190023)
Make cortex-m33 runtime libraries build to use hard float ABI instead of
softfp.
Commit: e87ea848b7a00f8b020ff02c74a2f09e63b7c735
https://github.com/llvm/llvm-project/commit/e87ea848b7a00f8b020ff02c74a2f09e63b7c735
Author: lntue <lntue at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/config/config.json
M libc/src/__support/CMakeLists.txt
M libc/src/__support/time/CMakeLists.txt
M libc/src/assert/gpu/__assert_fail.cpp
M libc/src/time/linux/CMakeLists.txt
M libc/src/unistd/CMakeLists.txt
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/TestLogger.cpp
Log Message:
-----------
Reapply "[libc] Finetune libc.src.__support.OSUtil.osutil dependency." (#190033) (#190065)
This reverts commit 84f23eb3113f2e75d1a2e45db1b5c570a5d2f4c5 and fix GPU
builds.
Commit: 52fb23eef8e4c331ae7cfa21e26d07918cfebd5e
https://github.com/llvm/llvm-project/commit/52fb23eef8e4c331ae7cfa21e26d07918cfebd5e
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/src/__support/math/log1pf.h
Log Message:
-----------
[libc][math] Remove static from log1pf implementation (#190042)
Reflecting changes according to
https://github.com/llvm/llvm-project/commit/823e3e001724ca2e93ce410a675f3b538f8a74b3
Commit: 29391328ab66052b03babb2d147615f180827793
https://github.com/llvm/llvm-project/commit/29391328ab66052b03babb2d147615f180827793
Author: Demetrius Kanios <demetrius at kanios.net>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
Log Message:
-----------
[WebAssembly][GlobalISel] CallLowering `lowerFormalArguments` (#180263)
Implements `WebAssemblyCallLowering::lowerFormalArguments`
Split from #157161
Commit: 7c260d3966534031f9fe3a35b54887f6d979606d
https://github.com/llvm/llvm-project/commit/7c260d3966534031f9fe3a35b54887f6d979606d
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
Log Message:
-----------
[scudo] Fix reallocate for MTE. (#190086)
For MTE, we can't use the whole size or we might trigger a segfault.
Therefore, use the exact size when MTE is enabled or the exact usable
size parameter is true.
Also, optimize out the call to getUsableSize and use a simpler
calculation.
Commit: b9e01c26f0bb754307d12c19b957be576ff422a8
https://github.com/llvm/llvm-project/commit/b9e01c26f0bb754307d12c19b957be576ff422a8
Author: Jim Lin <jim at andestech.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
Log Message:
-----------
[RISCV] Relax VL constraint in convertSameMaskVMergeToVMv (#189797)
When converting a PseudoVMERGE_VVM to PseudoVMV_V_V, we previously
required MIVL <= TrueVL to avoid losing False elements in the tail.
Relax this constraint when the vmerge's False operand equals its
Passthru operand and the True instruction's tail policy is TU
(tail undisturbed). In this case, True's tail lanes preserve its
passthru value (which equals False and Passthru), so the conversion
is safe even when MIVL > TrueVL.
---------
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: 3d7eedce5658c41a1b22775938359bfafac47fc9
https://github.com/llvm/llvm-project/commit/3d7eedce5658c41a1b22775938359bfafac47fc9
Author: Jim Lin <jim at andestech.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
Log Message:
-----------
[RISCV] Fix stackmap shadow trimming NOP size for compressed targets (#189774)
The shadow trimming loop in LowerSTACKMAP hardcoded a 4-byte decrement
per instruction, but when Zca is enabled NOPs are 2 bytes. Use NOPBytes
instead of the hardcoded 4 so the shadow is correctly trimmed on
compressed targets.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: fd609e5d33eae0df48d37a215f13a78bab3f8ebb
https://github.com/llvm/llvm-project/commit/fd609e5d33eae0df48d37a215f13a78bab3f8ebb
Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lld/ELF/BPSectionOrderer.cpp
M lld/ELF/BPSectionOrderer.h
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/BPSectionOrderer.h
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/SectionPriorities.cpp
M lld/docs/ReleaseNotes.rst
A lld/include/lld/Common/BPSectionOrdererBase.h
M lld/include/lld/Common/BPSectionOrdererBase.inc
A lld/test/ELF/bp-section-orderer-cold.s
M lld/test/ELF/bp-section-orderer.s
M lld/test/MachO/bp-section-orderer-errs.s
A lld/test/MachO/compression-order-sections.s
Log Message:
-----------
[lld] Glob-based BP compression sort groups (#185661)
Add
--bp-compression-sort-section=<glob>[=<layout_priority>[=<match_priority>]]
to let users split input sections into multiple compression groups, run
balanced partitioning independently per group, and leave out sections
that are poor candidates for BP. This replaces the old coarse
--bp-compression-sort with a more explicit, user-controlled one.
In ELF, the glob matches input section names (.text.unlikely.cold1). In
Mach-O, it matches the concatenated segment+section name (__TEXT__text).
layout_priority controls group placement in the final layout.
match_priority resolves conflicts when multiple globs match the same
section: explicit priority beats positional matching, and among
positional specs the last match wins.
A CRTP hook getCompressionSubgroupKey() allows backends to further
subdivide glob groups into independent BP instances. This allows Mach-O
backend to separate cold functions via N_COLD_FUNC in the future.
The deprecated --bp-compression-sort option keeps its existing
function/data behavior by assigning sections to fixed legacy groups.
Commit: 096f9d0aa8edb8bad77e8061a6aa9cbf61bcb5ac
https://github.com/llvm/llvm-project/commit/096f9d0aa8edb8bad77e8061a6aa9cbf61bcb5ac
Author: lntue <lntue at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
A libc/config/linux/power/config.json
A libc/config/linux/power/entrypoints.txt
A libc/config/linux/power/headers.txt
M libc/src/__support/FPUtil/generic/sqrt.h
Log Message:
-----------
[libc] Initial support so that libc-shared-tests can be built with pp64le (#188882)
Commit: c97e08e331736ae8c7d17bf1f24954570f564ad0
https://github.com/llvm/llvm-project/commit/c97e08e331736ae8c7d17bf1f24954570f564ad0
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclContextInternals.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/include-between-imports-enums.cppm
Log Message:
-----------
[C++20] [Modules] Add VisiblePromoted module ownership kind (#189903)
This patch adds a new ModuleOwnershipKind::VisiblePromoted to handle
declarations that are not visible to the current TU but are promoted to
be visible to avoid re-parsing.
Originally we set the visible visiblity directly in such cases. But
https://github.com/llvm/llvm-project/issues/188853 shows such decls may
be excluded later if we import #include and then import. So we have to
introduce a new visibility to express the intention that the visibility
of the decl is intentionally promoted.
Close https://github.com/llvm/llvm-project/issues/188853
Commit: e27e7e433974b24c90fed9f0b646bed84e47681e
https://github.com/llvm/llvm-project/commit/e27e7e433974b24c90fed9f0b646bed84e47681e
Author: Anshul Nigham <nigham at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
Log Message:
-----------
[NFC][AAarch64] Remove PreLegalizerCombiner pass dependency on TargetPassConfig (#190073)
This will enable NewPM porting.
Replaced with the definition in
[AArch64PassConfig::getCSEConfig](https://github.com/llvm/llvm-project/blob/1d549d9a777a6faef6d425cb6482ab1fa6b91bb7/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp#L614)
Commit: dee982d6c872d3985acede6fe8cb914ad87801c2
https://github.com/llvm/llvm-project/commit/dee982d6c872d3985acede6fe8cb914ad87801c2
Author: Anshul Nigham <nigham at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/test/CodeGen/AArch64/aarch64-post-coalescer.mir
Log Message:
-----------
[NewPM] Adds a port for AArch64PostCoalescerPass (#189520)
Adds a standard porting for AArch64PostCoalescer to NewPM.
Commit: 8daaa26efdda3802f73367d844b267bda3f84cbe
https://github.com/llvm/llvm-project/commit/8daaa26efdda3802f73367d844b267bda3f84cbe
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lld/test/ELF/merge-piece-oob.s
M llvm/include/llvm/Support/Parallel.h
M llvm/lib/Support/Parallel.cpp
M llvm/unittests/Support/ParallelTest.cpp
Log Message:
-----------
[Support] Support nested parallel TaskGroup via work-stealing (#189293)
Nested TaskGroups run serially to prevent deadlock, as documented by
https://reviews.llvm.org/D61115 and refined by
https://reviews.llvm.org/D148984 to use threadIndex.
Enable nested parallelism by having worker threads actively execute
tasks from the work queue while waiting (work-stealing), instead of
just blocking. Root-level TaskGroups (main thread) keep the efficient
blocking Latch::sync(), so there is no overhead for the common
non-nested case.
In lld, https://reviews.llvm.org/D131247 worked around the limitation
by passing a single root TaskGroup into OutputSection::writeTo and
spawning 4MB-chunked tasks into it. However, SyntheticSection::writeTo
calls with internal parallelism (e.g. GdbIndexSection,
MergeNoTailSection) still ran serially on worker threads. With this
change, their internal parallelFor/parallelForEach calls parallelize
automatically via helpSync work-stealing.
The increased parallelism can reorder error messages from parallel
phases (e.g. relocation processing during section writes), so one lld
test is updated to use --threads=1 for deterministic output.
Commit: c8c7186b462e32724bf7942d9345b2cb922b8af8
https://github.com/llvm/llvm-project/commit/c8c7186b462e32724bf7942d9345b2cb922b8af8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/gfni-rotates.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
Log Message:
-----------
[X86] LowerRotate - expand vXi8 non-uniform variable rotates using uniform constant rotates (#189986)
We expand vXi8 non-uniform variable rotates as a sequence of uniform
constant rotates along with a SELECT depending on whether the original
rotate amount needs it
This patch removes premature uniform constant rotate expansion to the
OR(SHL,SRL) sequences to allow GFNI targets to use single VGF2P8AFFINEQB
calls
Commit: d52daeac796637ee4578bae728d867c60902a882
https://github.com/llvm/llvm-project/commit/d52daeac796637ee4578bae728d867c60902a882
Author: lntue <lntue at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/test/shared/shared_math_test.cpp
Log Message:
-----------
[libc] Fix the remaining long double issue in shared_math_test.cpp. (#190098)
Commit: 495e1a42579c8f540303ab72e6449a448b89e537
https://github.com/llvm/llvm-project/commit/495e1a42579c8f540303ab72e6449a448b89e537
Author: yebinchon <86588366+yebinchon at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/Math/Transforms/SincosFusion.cpp
M mlir/test/Dialect/Math/sincos-fusion.mlir
Log Message:
-----------
[mlir] added a check in the walk to prevent catching a cos in a nested region (#190064)
The walk in SincosFusion may detect a cos within a nested region of the
sin block. This triggers an assertion in `isBeforeInBlock` later on.
Added a check within the walk so it filters operations in nested
regions, which are not in the same block and should not be fused anyway.
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
Commit: 8c2feea2f746de8e3afc101d5621c7ab60a74644
https://github.com/llvm/llvm-project/commit/8c2feea2f746de8e3afc101d5621c7ab60a74644
Author: wangjue <wangjue.wangjue at alibaba-inc.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/runtime/instr.cpp
M bolt/runtime/sys_riscv64.h
Log Message:
-----------
[BOLT] Delete unnecessary instructions (#189297)
Commit: 18a065763d267354bafe1d0a41325f50500d5b29
https://github.com/llvm/llvm-project/commit/18a065763d267354bafe1d0a41325f50500d5b29
Author: Sudharsan Veeravalli <svs at qti.qualcomm.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi-multiple.mir
Log Message:
-----------
[RISCV] Move unpaired instruction back in RISCVLoadStoreOptimizer (#189912)
There are cases when the `Xqcilsm` vendor extension is enabled that we
are unable to pair non-adjacent load/store instructions. The
`RISCVLoadStoreOptimizer` moves the instruction adjacent to the other
before attempting to pair them but does not move them back when it
fails. This can sometimes prevent the generation of the `Xqcilsm`
load/store multiple instructions. This patch ensures that we move the
unpaired instruction back to it's original location.
Commit: 06aae40c6dee03741f96c1b09ccc57f7fb110dd1
https://github.com/llvm/llvm-project/commit/06aae40c6dee03741f96c1b09ccc57f7fb110dd1
Author: Diego Novillo <dnovillo at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
A clang/test/CodeGenHLSL/debug/source-language.hlsl
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
A llvm/test/CodeGen/SPIRV/debug-info/hlsl-debug-info-auto-activation.ll
A llvm/test/CodeGen/SPIRV/debug-info/no-nonsemantic-without-extension.ll
M llvm/test/CodeGen/SPIRV/hlsl-resources/SampleErrorsDebug.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
Log Message:
-----------
[HLSL][SPIRV] Restore support for -g to generate NSDI (#190007)
The original attempt (#187051) produced a regression for
`intel-sycl-gpu` because `SPIRVEmitNonSemanticDI` will now self-activate
whenever `llvm.dbg.cu` is present. This removed the need for the
explicit `--spv-emit-nonsemantic-debug-info` flag.
The pass is now entered unconditionally for all SPIR-V targets, but
`NonSemantic.Shader.DebugInfo.100` requires the
`SPV_KHR_non_semantic_info`. Targets like `spirv64-intel` do not enable
that extension by default. When `checkSatisfiable()` ran on those
targets, it issued a fatal error rather than silently skipping.
Adds an early-out from `emitGlobalDI()`: if
`SPV_KHR_non_semantic_info` is not available for the current target, the
pass returns without emitting anything.
Commit: dbc206f35d36370b9adac7868eb319799de7abe1
https://github.com/llvm/llvm-project/commit/dbc206f35d36370b9adac7868eb319799de7abe1
Author: Chaitanya <Krishna.Sankisa at amd.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/global-section.c
Log Message:
-----------
[CIR][CIRGen] Support for section atttribute on cir.global (#188200)
Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/422
This PR implement support for `__attribute__((section("name")))` on
global variables in ClangIR, matching OGCG behavior.
Commit: 9a354fc5a16cb68ac61c1963d1d12123aa5a6dbf
https://github.com/llvm/llvm-project/commit/9a354fc5a16cb68ac61c1963d1d12123aa5a6dbf
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
[SelectionDAG] Use `KnownBits` to determine if an operand may be NaN. (#188606)
Given a bitcast into a fp type, use the known bits of the operand to
infer whether the resulting value can never be NaN.
Commit: 3346a76d32ee6de1324d570be912c935fdcee265
https://github.com/llvm/llvm-project/commit/3346a76d32ee6de1324d570be912c935fdcee265
Author: Lang Hames <lhames at gmail.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
Log Message:
-----------
[JITLink] Remove unnecessary SymbolStringPtr copy. (#190101)
This was probably intended to be a `const SymbolStringPtr&` originally,
but if we were going to copy it anyway it's better to just take the
argument by value and std::move it.
Commit: 0bde74ab04992bcd63bc0bfd8b79e2ef5eab270b
https://github.com/llvm/llvm-project/commit/0bde74ab04992bcd63bc0bfd8b79e2ef5eab270b
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lld/ELF/InputSection.cpp
Log Message:
-----------
[ELF] Pass SectionPiece by reference in getSectionPiece. NFC (#190110)
The generated assembly looks more optimized. In addition, this avoids
widened load, which would cause a TSan-detected data race with parallel
--gc-sections (#189321).
Commit: 2a7ca3a3fa46c544704e9ca6d8006b110af652ab
https://github.com/llvm/llvm-project/commit/2a7ca3a3fa46c544704e9ca6d8006b110af652ab
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_ctlz, vp_cttz, vp_ctpop (#189904)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off 3 intrinsics from #179622.
Note that vp.cttz is the elementwise version, not vp.cttz.elts.
Commit: 2118499a898b514f70fb1754ad8713a4267f7bd3
https://github.com/llvm/llvm-project/commit/2118499a898b514f70fb1754ad8713a4267f7bd3
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/MarkLive.cpp
Log Message:
-----------
[ELF] Decouple SharedFile::isNeeded from GC mark. NFC (#190112)
... out of the per-relocation resolveReloc and into a post-GC scan of
global symbols. This decouples the --as-needed logic from the mark
algorithm, simplifying the imminent parallel GC mark.
Commit: 68cbcf7ec2010a6fc4ad825ecf55e86b3c49f5fb
https://github.com/llvm/llvm-project/commit/68cbcf7ec2010a6fc4ad825ecf55e86b3c49f5fb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
A llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
Log Message:
-----------
[RISCV] Check EnsureWholeVectorRegisterMoveValidVTYPE in RISCVInsertVSETVLI::transferBefore. (#190022)
Fixes #189786
Commit: 802d4631e02b35a5890802a83459607d42cf4e98
https://github.com/llvm/llvm-project/commit/802d4631e02b35a5890802a83459607d42cf4e98
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
Log Message:
-----------
[clang-doc] Update lookup routines for consistency (#190043)
When filtering is enabled, its possible an Info doesn't have a
Parent USR. Use `find()` to safely handle that case.
Additionally, I noticed the comparison code for the index
poorly reimplemented the existing comparison from StringRef.
We can just use the one from ADT.
Commit: 6a874161621ec52b8efa125790e3e8e72bb9167a
https://github.com/llvm/llvm-project/commit/6a874161621ec52b8efa125790e3e8e72bb9167a
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/Symbols.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Move Symbol::used to atomic flags field (#190117)
Move the `used` bitfield into the existing `std::atomic<uint16_t>
flags`,
making it safe for concurrent access from parallel GC mark (#189321).
Commit: 083f9c158a6ecc3a0a1d9bb5c0997af036a4efbd
https://github.com/llvm/llvm-project/commit/083f9c158a6ecc3a0a1d9bb5c0997af036a4efbd
Author: David Green <david.green at arm.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/ctlz.ll
Log Message:
-----------
[AArch64][GISel] Widen non-power2 element sizes for ctlz. (#189371)
This addresses an illegal mutation kind, where gisel would hit an
assert. It expands vector elements for non-power2 elements or elements
less that i8 to a power of 2.
A fix to handle vector types correctly was needed in LegalizerHandler.
Fixes #185411
Commit: 6f9646a598f25efa3c4db066d2d51fb248b13526
https://github.com/llvm/llvm-project/commit/6f9646a598f25efa3c4db066d2d51fb248b13526
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
Log Message:
-----------
[ELF] Parallelize --gc-sections mark phase (#189321)
Add `markParallel` using level-synchronized `parallelFor`. Each BFS
level is processed in parallel; newly discovered sections are collected
in per-thread queues and merged for the next level.
The parallel path is used when `!TrackWhyLive && partitions.size()==1`.
`parallelFor` naturally degrades to serial when `--threads=1`.
Uses depth-limited inline recursion (depth<3) and optimistic
load-then-exchange dedup for best performance.
Linking a Release+Asserts clang (--gc-sections, --time-trace) on an old
x86-64:
8 threads: markLive 315ms -> 82ms (-234ms). Total 1562ms -> 1350ms
(1.16x).
16 threads: markLive 199ms -> 50ms (-149ms). Total 1017ms -> 862ms
(1.18x).
and on Apple M4: markLive 61ms -> 13ms. Total 317.3ms -> 272.7ms
(1.16x).
Commit: e3cbd9984a78422c3799629eb6b5f7f7818c1a11
https://github.com/llvm/llvm-project/commit/e3cbd9984a78422c3799629eb6b5f7f7818c1a11
Author: David Rivera <davidriverg at gmail.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/TargetInfo.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h
A clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/amdgpu-address-spaces.cpp
A clang/test/CIR/CodeGen/amdgpu-target-lowering-as.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
R clang/test/CIR/Lowering/global-address-space.cir
Log Message:
-----------
[CIR][AMDGPU] Lower Language specific address spaces and implement AMDGPU target (#179084)
Commit: 3b81be803f613f5b316945b1fbdb783333cdd4ff
https://github.com/llvm/llvm-project/commit/3b81be803f613f5b316945b1fbdb783333cdd4ff
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll
M llvm/test/Transforms/WholeProgramDevirt/import.ll
Log Message:
-----------
WholeProgramDevirt: Import/export the CVP byte directly in the summary (#188979)
rather than using absolute symbol constants on ELF/x86.
This leads to better codegen as the absolute symbol constants were not
resolved until link time (see bug for example).
Fixes #188470
Commit: 40e7fa632dbca6bb7ed0b3d50e47315256488865
https://github.com/llvm/llvm-project/commit/40e7fa632dbca6bb7ed0b3d50e47315256488865
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
A llvm/test/Transforms/FunctionSpecialization/function-specialization-optsize.ll
Log Message:
-----------
[Passes][FuncSpec] Move optsize/minsize handling into pass (#189952)
Instead of using the Os/Oz level during pass pipeline construction,
query the optsize/minsize attribute on the function to determine whether
specialization is allowed to take place. This ensures consistent
behavior for per-function attributes.
It's worth noting that FuncSpec *already* checks for minsize, but at the
call-site level.
Commit: 1662c200a5b151ad15b7efc82837076d8967dc11
https://github.com/llvm/llvm-project/commit/1662c200a5b151ad15b7efc82837076d8967dc11
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/Scalar/LoopRotation.cpp
M llvm/test/Transforms/LoopRotate/oz-disable.ll
M llvm/test/Transforms/PhaseOrdering/enable-loop-header-duplication-oz.ll
Log Message:
-----------
[Passes][LoopRotate] Move minsize handling fully into pass (#189956)
Make this dependent only on the minsize attribute and drop the pipeline
handling.
Rename the enable-loop-header-duplication option to
enable-loop-header-duplication-at-minsize to clarify that it controls
header duplication at minsize only (in other cases it is enabled by
default, independently of this option).
Commit: 7ccd1cb9a470525570b5759fd7e9ef85e0b9dbba
https://github.com/llvm/llvm-project/commit/7ccd1cb9a470525570b5759fd7e9ef85e0b9dbba
Author: Weibo He <NewSigma at 163.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll
M llvm/test/Transforms/Coroutines/coro-await-suspend-lower.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-01.ll
Log Message:
-----------
Reland "[CoroSplit] Erase trivially dead allocas after spilling (#189295)" (#190124)
The original PR contained a use-after-delete issue, which has been
resolved in #189521.
Reland #189295, which is reverted in #189311
Commit: a599a06e7cc3c6801f5bc755a33517299cacda4c
https://github.com/llvm/llvm-project/commit/a599a06e7cc3c6801f5bc755a33517299cacda4c
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M libc/test/src/math/CMakeLists.txt
Log Message:
-----------
[libc] Indentation consistency in CMake (#190120)
This PR just fixes the indentation/style for the whole CMake file for
consistency.
No other changes.
c698f55b0245ffbaae55c7f854fadba33df16e9d
Commit: 5e0a06b34d09e44ced6a6820862a424efd2bd163
https://github.com/llvm/llvm-project/commit/5e0a06b34d09e44ced6a6820862a424efd2bd163
Author: Gabriel Baraldi <baraldigabriel at gmail.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
R llvm/include/llvm/CodeGen/ExpandMemCmp.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Transforms/Scalar.h
A llvm/include/llvm/Transforms/Scalar/ExpandMemCmp.h
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
R llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
A llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Scalar/Scalar.cpp
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
M llvm/test/CodeGen/AArch64/bcmp.ll
M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
M llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
M llvm/test/CodeGen/AArch64/memcmp.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/BPF/memcmp.ll
M llvm/test/CodeGen/Generic/llc-start-stop.ll
M llvm/test/CodeGen/LoongArch/expandmemcmp-optsize.ll
M llvm/test/CodeGen/LoongArch/expandmemcmp.ll
M llvm/test/CodeGen/LoongArch/memcmp.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/M68k/pipeline.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
M llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
M llvm/test/CodeGen/PowerPC/memcmp.ll
M llvm/test/CodeGen/PowerPC/memcmp32_fixsize.ll
M llvm/test/CodeGen/PowerPC/memcmp64_fixsize.ll
M llvm/test/CodeGen/PowerPC/memcmpIR.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/pr186969.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
M llvm/test/CodeGen/WebAssembly/memcmp-expand.ll
M llvm/test/CodeGen/WebAssembly/simd-memcmp.ll
M llvm/test/CodeGen/WebAssembly/simd-setcc.ll
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
M llvm/test/CodeGen/X86/memcmp-constant.ll
M llvm/test/CodeGen/X86/memcmp-mergeexpand.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
M llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
M llvm/test/CodeGen/X86/memcmp-optsize.ll
M llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
M llvm/test/CodeGen/X86/memcmp-pgso.ll
M llvm/test/CodeGen/X86/memcmp-x32.ll
M llvm/test/CodeGen/X86/memcmp.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
A llvm/test/Transforms/ExpandMemCmp/X86/sanitizer-skip.ll
A llvm/test/Transforms/PhaseOrdering/X86/expand-memcmp-middle-end.ll
M llvm/test/tools/llc/new-pm/option-conflict.ll
M llvm/test/tools/llc/new-pm/start-stop.ll
M llvm/tools/opt/optdriver.cpp
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
Log Message:
-----------
Move ExpandMemCmp and MergeIcmp to the middle end (#77370)
Moving these into the middle-end pipeline will allow for additional
optimization of the expansion result, such as CSE of redundant loads
(c.f. https://godbolt.org/z/bEna4Md9r). For now, we conservatively place
the passes at the end of the middle-end pipeline, so we mostly don't
benefit from additional optimizations yet. The pipeline position will be
moved in a future change.
This builds on work done by legrosbuffle in
https://reviews.llvm.org/D60318.
---------
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: e3cfcf48d0c966f163c9807839a900936af0e759
https://github.com/llvm/llvm-project/commit/e3cfcf48d0c966f163c9807839a900936af0e759
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticCrossTUKinds.td
M clang/include/clang/CrossTU/CrossTranslationUnit.h
M clang/lib/CrossTU/CrossTranslationUnit.cpp
A clang/test/Analysis/ctu/diag/Inputs/third.cpp
M clang/test/Analysis/ctu/diag/invlist-ambiguous.cpp
M clang/test/Analysis/ctu/diag/invlist-empty.cpp
M clang/test/Analysis/ctu/diag/invlist-lookup-miss.cpp
M clang/test/Analysis/ctu/diag/invlist-missing.cpp
A clang/test/Analysis/ctu/diag/invlist-wrong-format-late.cpp
M clang/test/Analysis/ctu/diag/invlist-wrong-format.cpp
M clang/test/Analysis/ctu/diag/lang-dialect-mismatch.cpp
M clang/test/Analysis/ctu/diag/lang-mismatch.c
M clang/test/Analysis/ctu/diag/load-threshold.cpp
M clang/test/Analysis/ctu/import-type-decl-definition.c
M clang/test/Analysis/ctu/invalid-ast.cpp
M clang/test/Analysis/ctu/main.c
M clang/test/Analysis/ctu/missing-ast.cpp
M clang/test/Analysis/ctu/on-demand-parsing.c
M clang/test/Analysis/ctu/test-import-failure.cpp
M clang/unittests/CrossTU/CrossTranslationUnitTest.cpp
Log Message:
-----------
[clang][analyzer] Forward CTU-import failure conditions
Forward all CTU-import failures as diagnostics (remarks, warnings,
errors), except for `index_error_code::missing_definition` which has the
potential of generating too many diagnostics.
--
CPP-7804
Commit: 76fc936175304b521d8f5d9f0a67fe479237b4ac
https://github.com/llvm/llvm-project/commit/76fc936175304b521d8f5d9f0a67fe479237b4ac
Author: wanglei <wanglei at loongson.cn>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsLoongArchLASX.def
M clang/include/clang/Basic/BuiltinsLoongArchLSX.def
A clang/test/CodeGen/LoongArch/lasx/lasxintrin-lax-vector-conversions.c
A clang/test/CodeGen/LoongArch/lsx/lsxintrin-lax-vector-conversions.c
Log Message:
-----------
[Clang][LoongArch] Align LSX/LASX built-in signatures with intrinsic types to avoid lax conversions (#189900)
Update the built-in signatures in BuiltinsLoongArchLSX.def and
BuiltinsLoongArchLASX.def to precisely match the vector types used in
the corresponding intrinsic headers (lsxintrin.h and lasxintrin.h).
This alignment ensures that these intrinsics can be compiled
successfully even when -flax-vector-conversions=none is specified, since
the built-in arguments no longer rely on implicit vector type
conversions.
Added new test cases to verify the macro-defined LSX/LASX
intrinsic interfaces under -flax-vector-conversions=none.
Fixes #189898
Commit: 5f6835daf481948f42740f5167221dba608a6493
https://github.com/llvm/llvm-project/commit/5f6835daf481948f42740f5167221dba608a6493
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
Log Message:
-----------
[lldb][AArch64][Linux] Qualify uses of user_sve_header (#190130)
Fixes #165413. Where a build failure was reported:
```
/b/s/w/ir/x/w/llvm-llvm-project/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:1182:9: error: unknown type name 'user_sve_header'; did you mean 'sve::user_sve_header'?
1182 | user_sve_header *header =
| ^~~~~~~~~~~~~~~
| sve::user_sve_header
```
To fix this, add sve:: as we do for all other uses of this.
This is LLDB's copy of a structure that Linux also defines. I think the
build worked on some machines because that version ended up being
included, but with a more isolated build, it may not.
We have our own definition of it so we can be sure what we're using in
case Linux extends it later.
Commit: 703d43ca3b66279b4ad81b88d6805f6f27edc557
https://github.com/llvm/llvm-project/commit/703d43ca3b66279b4ad81b88d6805f6f27edc557
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.h
Log Message:
-----------
[CostModel] Move default expand cost for partial reductions to BasicTTIImpl (#189905)
This is a follow-up of the suggestion left here:
https://github.com/llvm/llvm-project/pull/181707#discussion_r2995733831
The override functions in AMDGPU/ARM/SystemZ/X86 are required to avoid
enabling partial reductions where they were previously disabled (I've
added this for all targets that implement getArithmeticReductionCost).
Commit: 81691d23cd1895436bcf2bdbf1b92adf1dcb761e
https://github.com/llvm/llvm-project/commit/81691d23cd1895436bcf2bdbf1b92adf1dcb761e
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/extract-last-active.ll
Log Message:
-----------
[RISCV][TTI] Update cost and prevent exceed m8 for vector.extract.last.active (#188160)
This patch contains two parts.
1. Update costs reflect to the codegen changes. This is not that
accurate since the step vector can use smaller type if there is a
vscale_range attribute. But we cannot get that in the type-based query
in TTI.
2. Return invalid cost for the vector.extract.last.active that needs
vector split for the step vector. But currently this is not handled
correctly and will hit the assertion.
For not blocking the FindLast reduction in LV
(https://github.com/llvm/llvm-project/pull/184931). We should land this
first and fix the SelectionDAG for vector.extract.last.active lowering.
Commit: 018e048daf9dcc5e21f1372b85e9f0a6e4597c64
https://github.com/llvm/llvm-project/commit/018e048daf9dcc5e21f1372b85e9f0a6e4597c64
Author: Julian Oppermann <julian.oppermann at intel.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.h
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
Log Message:
-----------
[MLIR][Linalg] Generic to category specialization for unary elementwise ops (#187217)
Handle specialization of `linalg.generic` ops representing a unary
elementwise computation to the `linalg.elementwise` category op. This
implements a previously absent path in the linalg morphism.
Commit: d835dd2b430c259020e2fc5ce4b1eb1f5a464a07
https://github.com/llvm/llvm-project/commit/d835dd2b430c259020e2fc5ce4b1eb1f5a464a07
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[LV] Strip createStepForVF (NFC) (#185668)
The mul -> shl simplification is already done in VPlan.
Commit: 4c9a739c5ea72eb37a7c998e25d9a0a096042c73
https://github.com/llvm/llvm-project/commit/4c9a739c5ea72eb37a7c998e25d9a0a096042c73
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M bolt/test/AArch64/compare-and-branch-inversion.S
M bolt/test/AArch64/compare-and-branch-reorder-blocks.S
M bolt/test/AArch64/compare-and-branch-split-functions.S
M bolt/test/AArch64/compare-and-branch-unsupported.S
Log Message:
-----------
[BOLT][AArch64] Strip uneeded labels from FEAT_CMPBR tests. (#189931)
Eliminates the temporary labels so that BOLT does not recognize them as
secondary entry points.
Commit: dc9be4ee30d07060a21273bdf8c64e4f34165562
https://github.com/llvm/llvm-project/commit/dc9be4ee30d07060a21273bdf8c64e4f34165562
Author: Simi Pallipurath <simi.pallipurath at arm.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M lld/ELF/Arch/ARM.cpp
A lld/test/ELF/arm-be8-data-mapsym.s
Log Message:
-----------
[LLD][ELF] Skip non-inputsections to avoid invalid cast in Arm BE8 handling (#188154)
This patch fixes https://github.com/llvm/llvm-project/issues/187033
In BE8 mode, instruction bytes are reversed for sections containing
code. This logic currently assumes that arm mapping symbols (e.g. $a,
$t, $d) are always associated with InputSections.
However, mapping symbols can also be defined in other section types such
as mergeable sections (SHF_MERGE). These are not represented as
InputSection, and attempting to cast them using
cast_if_present<InputSection> results in an assertion failure.
Commit: d0bf354828717ee7228527237e61e0fcccfe0f15
https://github.com/llvm/llvm-project/commit/d0bf354828717ee7228527237e61e0fcccfe0f15
Author: Jiachen Yuan <jiacheny at nvidia.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/include/llvm/ADT/Bitset.h
M llvm/unittests/ADT/BitsetTest.cpp
Log Message:
-----------
[ADT] Reinstate "Refactor Bitset to Be More Constexpr-Usable" (#189497)
Reland of #172062 (a71b1d2), which was reverted in b0234d1.
This patch makes essential Bitset member functions constexpr (`set()`,
`any()`, `none()`, `count()`, `operator==`, `!=`, `<`, `\~`) and adds a
new `all()` method. It also introduces a `maskLastWord()` invariant to
ensure unused high bits in the last word are always zero, which is
required for correctness of `operator~`, `set()`, `all()`, and
comparisons on non-word-aligned sizes (e.g., `Bitset<33>`).
Changes from the original reverted PR:
- Replaced `llvm::any_of` with an inline loop to avoid depending on
constexpr `any_of`/`none_of` from `STLExtras` (#172536), which was also
reverted due to a GCC 15.2.1 bootstrap miscompile.
- The patch is now fully self-contained with no prerequisite changes.
Motivation: This is a prerequisite for making `LaneBitmask` a wrapper
around `Bitset`, enabling scalable lane bitmasks beyond 64 bits
(https://discourse.llvm.org/t/rfc-out-of-lanebitmask-bits-again/88613).
Commit: 9ff2ef97111bf3b281b1b8950ddfa7ba4d01c281
https://github.com/llvm/llvm-project/commit/9ff2ef97111bf3b281b1b8950ddfa7ba4d01c281
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/AArch64/sve-stepvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve2-bsl.ll
M llvm/test/CodeGen/AArch64/sve2-rsh.ll
M llvm/test/CodeGen/AArch64/sve2-xar.ll
Log Message:
-----------
[AArch64][SVE] Define pseudos for arithmetic immediate instructions. (#188579)
This patch uses DestructiveBinaryShImmUnpred (which was previously
unused as far as I could tell) to define pseudos for arithmetic
immediate instructions such as ADD (immediate), which allows using
MOVPRFX with these instructions.
Commit: c329cc59d91b3f9774383e5e933d812539f17d1e
https://github.com/llvm/llvm-project/commit/c329cc59d91b3f9774383e5e933d812539f17d1e
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
A lldb/test/API/commands/register/TestRegistersUnavailable.py
A lldb/test/API/commands/register/aarch64_dynamic_regset/Makefile
A lldb/test/API/commands/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
A lldb/test/API/commands/register/aarch64_dynamic_regset/main.c
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/Makefile
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/main.c
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/Makefile
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/TestSMEZRegistersSaveRestore.py
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/main.c
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/Makefile
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/TestZAThreadedDynamic.py
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/main.c
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/Makefile
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c
A lldb/test/API/commands/register/aarch64_sve_simd_registers/Makefile
A lldb/test/API/commands/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
A lldb/test/API/commands/register/aarch64_sve_simd_registers/main.c
R lldb/test/API/commands/register/register/TestRegistersUnavailable.py
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/Makefile
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/Makefile
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/main.c
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/Makefile
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/TestSMEZRegistersSaveRestore.py
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/main.c
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/Makefile
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/TestZAThreadedDynamic.py
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/main.c
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
R lldb/test/API/commands/register/register/register_command/Makefile
R lldb/test/API/commands/register/register/register_command/TestRegisters.py
R lldb/test/API/commands/register/register/register_command/a.cpp
R lldb/test/API/commands/register/register/register_command/main.cpp
A lldb/test/API/commands/register/register_command/Makefile
A lldb/test/API/commands/register/register_command/TestRegisters.py
A lldb/test/API/commands/register/register_command/a.cpp
A lldb/test/API/commands/register/register_command/main.cpp
Log Message:
-----------
[lldb][test][NFC] Move register command tests (#190144)
For whatever reason we ended up with register/register but the first
register just had the second register folder in it.
Move the files up one level so we have register/<test files>.
Commit: 91b90652bb022417bc1f34c1231ca4b50128f735
https://github.com/llvm/llvm-project/commit/91b90652bb022417bc1f34c1231ca4b50128f735
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter-tests/nrvo.cpp
M cross-project-tests/lit.cfg.py
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
A llvm/test/DebugInfo/COFF/indirect-local.ll
M llvm/test/DebugInfo/COFF/nrvo.ll
M llvm/test/DebugInfo/COFF/pieces.ll
M llvm/test/DebugInfo/COFF/types-array-advanced.ll
Log Message:
-----------
Reland "[CodeView] Generate `S_DEFRANGE_REGISTER_REL_INDIR`" (#189401)
Initially added in #187709. It was reverted in #188833, because
[llvm-clang-x86_64-sie-win](https://lab.llvm.org/buildbot/#/builders/46/builds/32873)
was failing in
`cross-project-tests/debuginfo-tests/dexter-tests/nrvo.cpp`.
The test passed for me locally. After checking on another machine, I
found that `S_DEFRANGE_REGISTER_REL_INDIR` is only supported by
dbgeng/WinDbg from Windows 10.0 Build 19041 (released 2020) onwards.
SDKs before this will fail to read the value. That buildbot is on
Windows 10.0 Build 17763.
I'm not sure if we should make the generation of that record
conditional. Debuggers that can't read the record will skip it. They'll
still see that there's some local variable, but won't be able to display
the value.
As far as I know, users of older Windows 10 builds should be able to
install a newer Windows SDK and use the WinDbg from that version. But I
haven't tested that.
Commit: 57ee29a2a1fc33add3e1736614e6e666c432a840
https://github.com/llvm/llvm-project/commit/57ee29a2a1fc33add3e1736614e6e666c432a840
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CodeGen/CGClass.cpp
A clang/test/CIR/CodeGen/copy-constructor-memcpy.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
M clang/test/CIR/CodeGen/cxx-special-member-attr.cpp
M clang/test/CIR/CodeGen/nrvo.cpp
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
Log Message:
-----------
[CIR] Implement isMemcpyEquivalentSpecialMember for trivial copy/move ctors (#186700)
Implements isMemcpyEquivalentSpecialMember in CIR codegen so that
trivial copy/move constructors and defaulted union copy/move ops emit a
cir.copy directly instead of making a real constructor call. The logic
is shared with OG codegen by moving the implementation into ASTContext,
where it also gains the pointer field protection (PFP) check that was
previously missing in CIR.
Commit: afb80bddf147c134c5e3cf3f357f8d00bdfd526c
https://github.com/llvm/llvm-project/commit/afb80bddf147c134c5e3cf3f357f8d00bdfd526c
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
A cmake/Modules/GetToolchainDirs.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
R flang-rt/cmake/modules/GetToolchainDirs.cmake
M flang-rt/test/lit.site.cfg.py.in
M libc/CMakeLists.txt
M libcxx/CMakeLists.txt
M libcxxabi/CMakeLists.txt
M libsycl/CMakeLists.txt
M libunwind/CMakeLists.txt
M llvm-libgcc/CMakeLists.txt
M offload/CMakeLists.txt
M openmp/CMakeLists.txt
M orc-rt/lib/executor/CMakeLists.txt
M runtimes/CMakeLists.txt
Log Message:
-----------
[Runtimes] Introduce variables containing resource dir paths (#177953)
Introduce common infrastructure for runtimes that determines compiler
resource path locations. These variables introduced are:
* RUNTIMES_OUTPUT_RESOURCE_DIR
* RUNTIMES_INSTALL_RESOURCE_PATH
That contain the location for the compiler resource path (typically
`lib/clang/<version>`) in the build tree and the install tree (the
latter relative to CMAKE_INSTALL_PREFIX).
Additionally, define
* RUNTIMES_OUTPUT_RESOURCE_LIB_DIR
* RUNTIMES_INSTALL_RESOURCE_LIB_PATH
as for the location of clang/flang version-locked libraries (typically
`lib${LLVM_LIBDIR_SUFFIX}/<targer-triple>`, but also depends on `APPLE`
and `LLVM_ENABLE_PER_TARGET_RUNTIME_DIR`). This code is moved from
flang-rt and initially becomes its only user.
Refactored out of #171610 as requested
[here](https://github.com/llvm/llvm-project/pull/171610#discussion_r2687382481).
Extracted `get_runtimes_target_libdir_common` from compiler-rt as
requested
[here](https://github.com/llvm/llvm-project/pull/171610#discussion_r2689565634).
Added TODO comments to all runtimes as requested
[here](https://github.com/llvm/llvm-project/pull/171610#issuecomment-3789598635).
Commit: f51e343ed5896c05af0feee3d27d37dca7e94c32
https://github.com/llvm/llvm-project/commit/f51e343ed5896c05af0feee3d27d37dca7e94c32
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/memcmp.ll
Log Message:
-----------
[AArch64] Select REV16 for zext(bswap(i16)) (#189576)
Extend the existing any_extend(bswap i16) -> rev16 combine to also
handle zero_extend. REV16 preserves a zero upper half, so for i16 loads
this saves one instruction: ldrh+rev+lsr#16 -> ldrh+rev16.
Commit: 0ef3906aea92d86aa958c3a18e1e2f82f39ff353
https://github.com/llvm/llvm-project/commit/0ef3906aea92d86aa958c3a18e1e2f82f39ff353
Author: Naveen Seth Hanig <naveen.hanig at outlook.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/lib/Driver/ModulesDriver.cpp
Log Message:
-----------
[clang][modules-driver] Avoid copy of -cc1 command & const correctness (NFC) (#190142)
Commit: 5613f7729311da94568e469412418450b695bc18
https://github.com/llvm/llvm-project/commit/5613f7729311da94568e469412418450b695bc18
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
R libcxx/test/libcxx/diagnostics/ranges.nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.utility/range.utility.conv/nodiscard.verify.cpp
Log Message:
-----------
[libc++][ranges] Updated `ranges::to` `[[nodiscard]]` tests (#173574)
- Updated and moved `ranges::to` `[[nodiscard]]` tests to the new
conventinional location.
- Removed libcxx/test/libcxx/diagnostics/ranges.nodiscard.verify.cpp,
which is now obsolete in favor of more specific test files.
# References:
- https://wg21.link/range.utility.conv
- https://wg21.link/range.utility.conv.to
- https://wg21.link/range.utility.conv.adaptors
Towards #172124
Commit: 94ec7ffa46d351b86fbbe3a445ceef37f331c4a2
https://github.com/llvm/llvm-project/commit/94ec7ffa46d351b86fbbe3a445ceef37f331c4a2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
Log Message:
-----------
[SLP] Do not skip tiny trees with gathered loads to vectorize
The isTreeTinyAndNotFullyVectorizable check for 2-node trees
(insertelement root + gather child) was too aggressive: it rejected
trees even when LoadEntriesToVectorize was non-empty, preventing
gathered loads from being vectorized into masked loads/strided loads, etc.
Reviewers: RKSimon, hiraditya
Pull Request: https://github.com/llvm/llvm-project/pull/190040
Commit: bed2761bc012b23e652c1f9377a7fd0a9a302bee
https://github.com/llvm/llvm-project/commit/bed2761bc012b23e652c1f9377a7fd0a9a302bee
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M polly/include/polly/CodeGen/IslNodeBuilder.h
M polly/include/polly/CodeGen/RuntimeDebugBuilder.h
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/test/CodeGen/RuntimeDebugBuilder/stmt_tracing.ll
Log Message:
-----------
[Polly] Print params with stmt tracing (#189362)
It was helpful for #189350.
Commit: 3468ee025ed5934f5fb224b497da15227c3de447
https://github.com/llvm/llvm-project/commit/3468ee025ed5934f5fb224b497da15227c3de447
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticCrossTUKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/test/Analysis/ctu/diag/load-threshold.cpp
Log Message:
-----------
fixup! [publish-sphinx-docs] Forward CTU-import failure conditions
Fix the Sphinx build failure
https://lab.llvm.org/buildbot/#/builders/45/builds/24533
introduced in e3cfcf48d0c966f163c9807839a900936af0e759 (PR #189064)
by using a dedicated group for CTU remarks.
Commit: 64b728128df355b9838eb7f6c19082628fb30dbe
https://github.com/llvm/llvm-project/commit/64b728128df355b9838eb7f6c19082628fb30dbe
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LivenessAnalysis.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/unittests/Passes/CMakeLists.txt
A bolt/unittests/Passes/LivenessAnalysis.cpp
Log Message:
-----------
[BOLT][AArch64] Add minimal support for liveness analysis. (#183298)
In this patch I am adding the missing target hooks required for the
liveness analysis to run on AArch64. These are
- getFlagsReg()
- getRegsUsedAsParams()
- getDefaultLiveOut()
- getGPRegs()
- isCleanRegXOR()
I am also introducing the following API in LivenessAnalysis
- BitVector getLiveIn/Out(const MCInst &)
- MCPhysReg scavengeRegFromState(BitVector &)
My intention is to allow the LongJmp pass scavenge usable registers when
injecting code.
Commit: 72e8c9b78f01439d34cbd05ed8d269a2758834de
https://github.com/llvm/llvm-project/commit/72e8c9b78f01439d34cbd05ed8d269a2758834de
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
R llvm/test/CodeGen/Generic/llc-start-stop.ll
A llvm/test/CodeGen/X86/llc-start-stop.ll
Log Message:
-----------
[CodeGen] Move llc-start-stop.ll test to X86 (#190151)
The pass pipeline differs across targets, so make this test use
one specific pipeline, instead of trying to cater to cross-target
differences. Those differences are not relevant to the intent of
the test.
Commit: c4b0f9959abe998f4985c1ef4ccfa22dc9096864
https://github.com/llvm/llvm-project/commit/c4b0f9959abe998f4985c1ef4ccfa22dc9096864
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M libsycl/docs/index.rst
M libsycl/src/CMakeLists.txt
A libsycl/src/detail/device_binary_structures.hpp
A libsycl/src/detail/device_image_wrapper.hpp
M libsycl/src/detail/device_impl.hpp
M libsycl/src/detail/global_objects.cpp
M libsycl/src/detail/global_objects.hpp
A libsycl/src/detail/kernel_id.hpp
A libsycl/src/detail/program_manager.cpp
A libsycl/src/detail/program_manager.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/usm_functions.cpp
Log Message:
-----------
[libsycl] Add device image registration & compatibility check (#187528)
This is part of the SYCL support upstreaming effort. The relevant RFCs
can be found here:
https://discourse.llvm.org/t/rfc-add-full-support-for-the-sycl-programming-model/74080
https://discourse.llvm.org/t/rfc-sycl-runtime-upstreaming/74479
---------
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 803d1d66094c9d2e543f5e62a426ef972e100a93
https://github.com/llvm/llvm-project/commit/803d1d66094c9d2e543f5e62a426ef972e100a93
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M clang/include/clang/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphSummary.h
M clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CMakeLists.txt
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractor.cpp
A clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphJSONFormat.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
A clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/invalid-direct-callee-element.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/invalid-direct-callee-id.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-col.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-file.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-line.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-direct-callees.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-pretty-name.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-virtual-callees.json
A clang/test/Analysis/Scalable/ssaf-format/call-graph-invalid-json-format.test
M clang/test/Analysis/Scalable/ssaf-format/list.test
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractorTest.cpp
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysisFramework/Analyses/BUILD.gn
Log Message:
-----------
[clang][ssaf] Implement JSON format for CallGraph summary (#189681)
rdar://170258016
Commit: 7389131f6843fd6110f98e1d102387fb576ff2ef
https://github.com/llvm/llvm-project/commit/7389131f6843fd6110f98e1d102387fb576ff2ef
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LivenessAnalysis.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/runtime/instr.cpp
M bolt/runtime/sys_riscv64.h
M bolt/test/AArch64/compare-and-branch-inversion.S
M bolt/test/AArch64/compare-and-branch-reorder-blocks.S
M bolt/test/AArch64/compare-and-branch-split-functions.S
M bolt/test/AArch64/compare-and-branch-unsupported.S
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/unittests/Passes/CMakeLists.txt
A bolt/unittests/Passes/LivenessAnalysis.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang-tools-extra/unittests/clang-tidy/CMakeLists.txt
R clang-tools-extra/unittests/clang-tidy/ObjCModuleTest.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclContextInternals.h
M clang/include/clang/Basic/BuiltinsLoongArchLASX.def
M clang/include/clang/Basic/BuiltinsLoongArchLSX.def
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticCrossTUKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/OffloadArch.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/include/clang/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.h
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/CrossTU/CrossTranslationUnit.h
M clang/include/clang/Driver/SyclInstallationDetector.h
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Frontend/FrontendActions.h
A clang/include/clang/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphSummary.h
M clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
M clang/include/clang/Serialization/ModuleCache.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/CodeGen/TargetInfo.cpp
M clang/lib/CIR/Dialect/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
A clang/lib/CIR/Dialect/OpenMP/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.cpp
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h
A clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/DependencyScanning/InProcessModuleCache.cpp
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/ModulesDriver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/SYCL.cpp
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/FrontendTool/CMakeLists.txt
M clang/lib/Lex/TokenLexer.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractor.cpp
A clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphJSONFormat.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ModuleCache.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/cxx26.cpp
A clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/invalid-direct-callee-element.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/invalid-direct-callee-id.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-col.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-file.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-line.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-direct-callees.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-pretty-name.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-virtual-callees.json
A clang/test/Analysis/Scalable/ssaf-format/call-graph-invalid-json-format.test
M clang/test/Analysis/Scalable/ssaf-format/list.test
A clang/test/Analysis/ctu/diag/Inputs/third.cpp
M clang/test/Analysis/ctu/diag/invlist-ambiguous.cpp
M clang/test/Analysis/ctu/diag/invlist-empty.cpp
M clang/test/Analysis/ctu/diag/invlist-lookup-miss.cpp
M clang/test/Analysis/ctu/diag/invlist-missing.cpp
A clang/test/Analysis/ctu/diag/invlist-wrong-format-late.cpp
M clang/test/Analysis/ctu/diag/invlist-wrong-format.cpp
M clang/test/Analysis/ctu/diag/lang-dialect-mismatch.cpp
M clang/test/Analysis/ctu/diag/lang-mismatch.c
M clang/test/Analysis/ctu/diag/load-threshold.cpp
M clang/test/Analysis/ctu/import-type-decl-definition.c
M clang/test/Analysis/ctu/invalid-ast.cpp
M clang/test/Analysis/ctu/main.c
M clang/test/Analysis/ctu/missing-ast.cpp
M clang/test/Analysis/ctu/on-demand-parsing.c
M clang/test/Analysis/ctu/test-import-failure.cpp
A clang/test/CIR/CodeGen/amdgpu-address-spaces.cpp
A clang/test/CIR/CodeGen/amdgpu-target-lowering-as.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
A clang/test/CIR/CodeGen/copy-constructor-memcpy.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
M clang/test/CIR/CodeGen/cxx-special-member-attr.cpp
A clang/test/CIR/CodeGen/delegating-ctor-exceptions.cpp
A clang/test/CIR/CodeGen/global-section.c
M clang/test/CIR/CodeGen/nonzeroinit-struct.cpp
M clang/test/CIR/CodeGen/nrvo.cpp
A clang/test/CIR/CodeGen/return-in-if-with-cleanups.cpp
M clang/test/CIR/CodeGen/throws.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
A clang/test/CIR/CodeGenOpenMP/omp-module-attrs.c
A clang/test/CIR/IR/string-trailing-zeros.cir
R clang/test/CIR/Lowering/global-address-space.cir
A clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
A clang/test/CIR/Transforms/omp-mark-declare-target.cir
A clang/test/CodeGen/LoongArch/lasx/lasxintrin-lax-vector-conversions.c
A clang/test/CodeGen/LoongArch/lsx/lsxintrin-lax-vector-conversions.c
A clang/test/CodeGen/async-exceptions.c
A clang/test/CodeGen/tbaa-matrix.c
A clang/test/CodeGen/ubsan-aggregate-null-align.c
M clang/test/CodeGenCUDA/fp-contract.cu
A clang/test/CodeGenCXX/dead-on-return-deleting-destructor.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/ptrauth-apple-kext-indirect-virtual-dtor-call.cpp
M clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp
A clang/test/CodeGenHLSL/debug/source-language.hlsl
M clang/test/CodeGenObjC/constant-string-class-1.m
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
A clang/test/Driver/Inputs/SYCL/libLLVMSYCL.ll
R clang/test/Driver/Inputs/SYCL/libsycl.ll
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Driver/link-device-code.test
M clang/test/Driver/linux-ld.c
M clang/test/Driver/sycl-offload-jit.cpp
M clang/test/Lexer/gnu-flags.c
A clang/test/Lexer/gnu-zero-variadic-macro-argument-fixit.c
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
A clang/test/Modules/include-between-imports-enums.cppm
A clang/test/Modules/pr189415.cppm
A clang/test/Parser/decltype-gh188014.cpp
M clang/test/Preprocessor/macro_fn.c
R clang/test/Sema/gh183974.c
M clang/test/SemaCXX/using-if-exists.cpp
M clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
A clang/test/SemaTemplate/GH188759.cpp
M clang/tools/cir-opt/CMakeLists.txt
M clang/tools/cir-opt/cir-opt.cpp
M clang/tools/cir-translate/CMakeLists.txt
M clang/tools/cir-translate/cir-translate.cpp
M clang/tools/clang-ssaf-format/CMakeLists.txt
M clang/tools/clang-ssaf-linker/CMakeLists.txt
M clang/unittests/CrossTU/CrossTranslationUnitTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
A clang/unittests/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/CMakeLists.txt
M clang/unittests/ScalableStaticAnalysisFramework/Registries/SummaryExtractorRegistryTest.cpp
M clang/utils/TableGen/CIRLoweringEmitter.cpp
M compiler-rt/cmake/Modules/CheckAssemblerFlag.cmake
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_errors.cpp
M compiler-rt/lib/asan/asan_errors.h
M compiler-rt/lib/asan/asan_flags.inc
M compiler-rt/lib/asan/asan_report.cpp
M compiler-rt/lib/asan/asan_report.h
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/arm/adddf3.S
M compiler-rt/lib/builtins/int_math.h
M compiler-rt/lib/builtins/muldc3.c
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/test/CMakeLists.txt
A compiler-rt/test/asan/TestCases/Linux/free_aligned_sized_mismatch.cpp
A compiler-rt/test/asan/TestCases/Linux/free_sized_mismatch.cpp
A compiler-rt/test/builtins/Unit/adddf3new_test.c
A compiler-rt/test/builtins/Unit/subdf3new_test.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/soft_rss_limit_mb_test.cpp
M cross-project-tests/debuginfo-tests/dexter-tests/nrvo.cpp
M cross-project-tests/lit.cfg.py
M flang-rt/lib/cuda/registration.cpp
M flang/docs/C++style.md
M flang/docs/Extensions.md
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCUtils.h
M flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/lib/Semantics/check-omp-atomic.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-utils.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-acc.mlir
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-device-address.mlir
A flang/test/HLFIR/bufferize-associate-block-ordering.fir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
A flang/test/Lower/HLFIR/elemental-character-min-max.f90
M flang/test/Lower/Intrinsics/same_type_as.f90
M flang/test/Lower/Intrinsics/scan.f90
M flang/test/Lower/Intrinsics/secnds.f90
M flang/test/Lower/Intrinsics/selected_int_kind.f90
M flang/test/Lower/Intrinsics/selected_real_kind.f90
R flang/test/Lower/OpenMP/Todo/depend-clause.f90
M flang/test/Lower/OpenMP/composite_simd_linear.f90
A flang/test/Lower/OpenMP/depend-iterator.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/linear_modifier.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
A flang/test/Lower/OpenMP/requires-usm.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
M flang/test/Transforms/FIRToMemRef/array-coor-slice-shift.mlir
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/config.json
M libc/config/gpu/amdgpu/entrypoints.txt
M libc/config/gpu/amdgpu/headers.txt
M libc/config/gpu/nvptx/entrypoints.txt
M libc/config/gpu/nvptx/headers.txt
A libc/config/linux/power/config.json
A libc/config/linux/power/entrypoints.txt
A libc/config/linux/power/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/siginfo_t.h
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/include/llvm-libc-types/pthread_rwlock_t.h
A libc/shared/CMakeLists.txt
M libc/src/__support/CMakeLists.txt
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/raise.h
M libc/src/__support/math/log1pf.h
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
R libc/src/__support/threads/linux/rwlock.h
A libc/src/__support/threads/raw_rwlock.h
A libc/src/__support/threads/unix_rwlock.h
M libc/src/__support/time/CMakeLists.txt
M libc/src/assert/gpu/__assert_fail.cpp
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_rwlock_clockrdlock.cpp
M libc/src/pthread/pthread_rwlock_clockwrlock.cpp
M libc/src/pthread/pthread_rwlock_destroy.cpp
M libc/src/pthread/pthread_rwlock_init.cpp
M libc/src/pthread/pthread_rwlock_rdlock.cpp
M libc/src/pthread/pthread_rwlock_timedrdlock.cpp
M libc/src/pthread/pthread_rwlock_timedwrlock.cpp
M libc/src/pthread/pthread_rwlock_tryrdlock.cpp
M libc/src/pthread/pthread_rwlock_trywrlock.cpp
M libc/src/pthread/pthread_rwlock_unlock.cpp
M libc/src/pthread/pthread_rwlock_wrlock.cpp
M libc/src/setjmp/aarch64/CMakeLists.txt
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/raise.cpp
M libc/src/signal/linux/sigaction.cpp
M libc/src/signal/linux/signal_utils.h
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/scanf_core/CMakeLists.txt
M libc/src/time/linux/CMakeLists.txt
M libc/src/unistd/CMakeLists.txt
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/TestLogger.cpp
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_rwlock_test.cpp
M libc/test/shared/shared_math_test.cpp
M libc/test/src/__support/threads/linux/CMakeLists.txt
A libc/test/src/__support/threads/linux/raw_rwlock_test.cpp
M libc/test/src/math/CMakeLists.txt
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdlib/CMakeLists.txt
M libcxx/docs/ReleaseNotes/23.rst
R libcxx/test/libcxx/diagnostics/ranges.nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.utility/range.utility.conv/nodiscard.verify.cpp
M libsycl/docs/index.rst
M libsycl/src/CMakeLists.txt
A libsycl/src/detail/device_binary_structures.hpp
A libsycl/src/detail/device_image_wrapper.hpp
M libsycl/src/detail/device_impl.hpp
M libsycl/src/detail/global_objects.cpp
M libsycl/src/detail/global_objects.hpp
A libsycl/src/detail/kernel_id.hpp
A libsycl/src/detail/program_manager.cpp
A libsycl/src/detail/program_manager.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/usm_functions.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/BPSectionOrderer.cpp
M lld/ELF/BPSectionOrderer.h
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/InputSection.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/Options.td
M lld/ELF/Symbols.h
M lld/ELF/Writer.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/BPSectionOrderer.h
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/SectionPriorities.cpp
M lld/docs/ReleaseNotes.rst
A lld/include/lld/Common/BPSectionOrdererBase.h
M lld/include/lld/Common/BPSectionOrdererBase.inc
A lld/test/ELF/arm-be8-data-mapsym.s
A lld/test/ELF/bp-section-orderer-cold.s
M lld/test/ELF/bp-section-orderer.s
M lld/test/ELF/merge-piece-oob.s
M lld/test/MachO/bp-section-orderer-errs.s
A lld/test/MachO/compression-order-sections.s
M lldb/docs/use/aarch64-linux.md
M lldb/examples/python/formatter_bytecode.py
M lldb/include/lldb/Host/FileAction.h
M lldb/include/lldb/Host/ProcessLaunchInfo.h
A lldb/include/lldb/Host/windows/WindowsFileAction.h
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/include/lldb/Target/Platform.h
M lldb/include/lldb/Target/StackFrame.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/include/lldb/lldb-private-enumerations.h
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Commands/CommandObjectMemory.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Expression/IRMemoryMap.cpp
M lldb/source/Host/CMakeLists.txt
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
A lldb/source/Host/windows/WindowsFileAction.cpp
M lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
M lldb/source/Plugins/Process/NetBSD/NativeProcessNetBSD.cpp
M lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
M lldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Target/MemoryRegionInfo.cpp
M lldb/source/Target/Platform.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/source/ValueObject/ValueObject.cpp
A lldb/test/API/commands/register/TestRegistersUnavailable.py
A lldb/test/API/commands/register/aarch64_dynamic_regset/Makefile
A lldb/test/API/commands/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
A lldb/test/API/commands/register/aarch64_dynamic_regset/main.c
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/Makefile
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/main.c
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/Makefile
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/TestSMEZRegistersSaveRestore.py
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/main.c
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/Makefile
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/TestZAThreadedDynamic.py
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/main.c
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/Makefile
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c
A lldb/test/API/commands/register/aarch64_sve_simd_registers/Makefile
A lldb/test/API/commands/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
A lldb/test/API/commands/register/aarch64_sve_simd_registers/main.c
R lldb/test/API/commands/register/register/TestRegistersUnavailable.py
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/Makefile
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/Makefile
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/main.c
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/Makefile
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/TestSMEZRegistersSaveRestore.py
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/main.c
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/Makefile
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/TestZAThreadedDynamic.py
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/main.c
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
R lldb/test/API/commands/register/register/register_command/Makefile
R lldb/test/API/commands/register/register/register_command/TestRegisters.py
R lldb/test/API/commands/register/register/register_command/a.cpp
R lldb/test/API/commands/register/register/register_command/main.cpp
A lldb/test/API/commands/register/register_command/Makefile
A lldb/test/API/commands/register/register_command/TestRegisters.py
A lldb/test/API/commands/register/register_command/a.cpp
A lldb/test/API/commands/register/register_command/main.cpp
M lldb/test/API/commands/target/create-deps/TestTargetCreateDeps.py
M lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/TestBreakInLoadedDylib.py
M lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
M lldb/test/API/functionalities/load_after_attach/TestLoadAfterAttach.py
M lldb/test/API/functionalities/load_lazy/TestLoadUsingLazyBind.py
M lldb/test/API/functionalities/load_unload/TestLoadUnload.py
A lldb/test/API/linux/aarch64/sme_only_registers/Makefile
A lldb/test/API/linux/aarch64/sme_only_registers/TestSMEOnlyRegisters.py
A lldb/test/API/linux/aarch64/sme_only_registers/main.c
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
M lldb/test/Shell/ScriptInterpreter/Python/python-bytecode.test
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/HostTest.cpp
M lldb/unittests/Platform/PlatformDarwinTest.cpp
M lldb/unittests/Platform/PlatformTest.cpp
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
M lldb/unittests/Target/MemoryRegionInfoTest.cpp
M llvm/CMakeLists.txt
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/SPIRVUsage.rst
M llvm/docs/SandboxVectorizer.md
M llvm/include/llvm/ADT/Bitset.h
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/Uniformity.h
M llvm/include/llvm/ADT/bit.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/MsgPackDocument.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
R llvm/include/llvm/CodeGen/ExpandMemCmp.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/DebugInfo/CodeView/LazyRandomTypeCollection.h
M llvm/include/llvm/DebugInfo/PDB/Native/TpiStream.h
M llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
A llvm/include/llvm/MC/MCAsmStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Support/Alignment.h
M llvm/include/llvm/Support/Parallel.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/Scalar.h
A llvm/include/llvm/Transforms/Scalar/ExpandMemCmp.h
A llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/BinaryFormat/MsgPackDocument.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
R llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/LowerEmuTLS.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/ProcessImplicitDefs.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/DebugInfo/CodeView/LazyRandomTypeCollection.cpp
M llvm/lib/DebugInfo/GSYM/FileWriter.cpp
M llvm/lib/DebugInfo/PDB/Native/TpiStream.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/LLVMContextImpl.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Support/APInt.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DataExtractor.cpp
M llvm/lib/Support/Parallel.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
A llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
M llvm/lib/Transforms/Scalar/LoopRotation.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/Scalar.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/PassRegistry.def
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizerPassBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/RISCV/extract-last-active.ll
M llvm/test/Analysis/DependenceAnalysis/PR188098.ll
M llvm/test/Analysis/DependenceAnalysis/exact-rdiv-delta-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-delta-signed-min.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-overflow.ll
M llvm/test/Analysis/LoopAccessAnalysis/invariant-dep-same-ptr.ll
M llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll
M llvm/test/CMakeLists.txt
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/aarch64-post-coalescer.mir
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
M llvm/test/CodeGen/AArch64/bcmp.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/ctlz.ll
M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/emutls.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
M llvm/test/CodeGen/AArch64/memcmp.ll
M llvm/test/CodeGen/AArch64/neon-abd.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/AArch64/sve-stepvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve2-bsl.ll
M llvm/test/CodeGen/AArch64/sve2-rsh.ll
M llvm/test/CodeGen/AArch64/sve2-xar.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
A llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-alloca-issue-155902.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
A llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
A llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
A llvm/test/CodeGen/ARM/emutls-alignment.ll
M llvm/test/CodeGen/BPF/memcmp.ll
R llvm/test/CodeGen/Generic/llc-start-stop.ll
M llvm/test/CodeGen/LoongArch/expandmemcmp-optsize.ll
M llvm/test/CodeGen/LoongArch/expandmemcmp.ll
M llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
M llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
M llvm/test/CodeGen/LoongArch/memcmp.ll
A llvm/test/CodeGen/LoongArch/mergestores.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/M68k/pipeline.ll
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-prio-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
M llvm/test/CodeGen/MLRegAlloc/dev-mode-prio-logging.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
M llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
M llvm/test/CodeGen/PowerPC/memcmp.ll
M llvm/test/CodeGen/PowerPC/memcmp32_fixsize.ll
M llvm/test/CodeGen/PowerPC/memcmp64_fixsize.ll
M llvm/test/CodeGen/PowerPC/memcmpIR.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
M llvm/test/CodeGen/PowerPC/vector-rotates.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
A llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir
M llvm/test/CodeGen/RISCV/pr186969.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
A llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
M llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi-multiple.mir
M llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
A llvm/test/CodeGen/SPIRV/debug-info/hlsl-debug-info-auto-activation.ll
A llvm/test/CodeGen/SPIRV/debug-info/no-nonsemantic-without-extension.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll
A llvm/test/CodeGen/SPIRV/function/variadics-lowering-builtin-substr-in-name.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/CalculateLevelOfDetail.ll
M llvm/test/CodeGen/SPIRV/hlsl-resources/SampleErrorsDebug.ll
M llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-kernel-pre16.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-non-extinst.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-infer-fnptr-todo-type.ll
M llvm/test/CodeGen/SPIRV/printf.ll
M llvm/test/CodeGen/SPIRV/spec_const_decoration.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
M llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
M llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
M llvm/test/CodeGen/WebAssembly/memcmp-expand.ll
M llvm/test/CodeGen/WebAssembly/simd-memcmp.ll
M llvm/test/CodeGen/WebAssembly/simd-setcc.ll
A llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
M llvm/test/CodeGen/X86/abds.ll
M llvm/test/CodeGen/X86/addcarry.ll
M llvm/test/CodeGen/X86/gfni-rotates.ll
M llvm/test/CodeGen/X86/issue76416.ll
A llvm/test/CodeGen/X86/known-fpclass.ll
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
A llvm/test/CodeGen/X86/llc-start-stop.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
M llvm/test/CodeGen/X86/memcmp-constant.ll
M llvm/test/CodeGen/X86/memcmp-mergeexpand.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
M llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
M llvm/test/CodeGen/X86/memcmp-optsize.ll
M llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
M llvm/test/CodeGen/X86/memcmp-pgso.ll
M llvm/test/CodeGen/X86/memcmp-x32.ll
M llvm/test/CodeGen/X86/memcmp.ll
A llvm/test/CodeGen/X86/multi-use-implicit-def.mir
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll
M llvm/test/CodeGen/X86/statepoint-two-results.ll
M llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
M llvm/test/CodeGen/X86/subcarry.ll
M llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
A llvm/test/DebugInfo/COFF/indirect-local.ll
M llvm/test/DebugInfo/COFF/nrvo.ll
M llvm/test/DebugInfo/COFF/pieces.ll
M llvm/test/DebugInfo/COFF/types-array-advanced.ll
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/MC/AArch64/armv8.9a-prfm-slc.s
M llvm/test/MC/AArch64/armv9.6a-pcdphint.s
M llvm/test/MC/AArch64/armv9a-tlbip.s
M llvm/test/MC/AArch64/basic-a64-instructions.s
M llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt
M llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/TableGen/intrinsic-arginfo-error.td
A llvm/test/TableGen/intrinsic-overload-dependent-type-validation.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll
M llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll
M llvm/test/Transforms/Coroutines/coro-await-suspend-lower.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-01.ll
M llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
A llvm/test/Transforms/ExpandMemCmp/X86/sanitizer-skip.ll
A llvm/test/Transforms/FunctionSpecialization/function-specialization-optsize.ll
A llvm/test/Transforms/InstCombine/printf-puts-not-emittable.ll
M llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll
M llvm/test/Transforms/LICM/hoist-binop.ll
M llvm/test/Transforms/LICM/preheader-safe.ll
M llvm/test/Transforms/LICM/read-only-calls.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
M llvm/test/Transforms/LoopRotate/oz-disable.ll
A llvm/test/Transforms/LoopUnroll/RISCV/runtime-unroll-max-trip-count.ll
M llvm/test/Transforms/LoopUnroll/debug.ll
M llvm/test/Transforms/LoopUnroll/runtime-small-upperbound.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/predicated-reverse-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
A llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
A llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
A llvm/test/Transforms/PhaseOrdering/X86/expand-memcmp-middle-end.ll
M llvm/test/Transforms/PhaseOrdering/enable-loop-header-duplication-oz.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
A llvm/test/Transforms/SLPVectorizer/X86/constant-based-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
M llvm/test/Transforms/SROA/vector-promotion-via-tree-structure-merge.ll
A llvm/test/Transforms/SampleProfile/pseudo-probe-emit-macho.ll
A llvm/test/Transforms/SandboxVectorizer/load_store_vec.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll
M llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll
M llvm/test/Transforms/WholeProgramDevirt/import.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected
M llvm/test/tools/llc/new-pm/option-conflict.ll
M llvm/test/tools/llc/new-pm/start-stop.ll
M llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/atomic.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/floating-point.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/integer.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/arithmetic.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/bitwise.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/comparison.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/conversion.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fma.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fp.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mask.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/minmax.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mul-div.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/permutation.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/reduction.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vle-vse-vlm.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlse-vsse.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlseg-vsseg.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlxe-vsxe.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbb.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbc.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkg.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkned.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvknhb.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksed.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksh.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zba.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbb.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbs.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfhmin.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llc/llc.cpp
M llvm/tools/llubi/lib/CMakeLists.txt
A llvm/tools/llubi/lib/ExecutorBase.cpp
A llvm/tools/llubi/lib/ExecutorBase.h
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llvm-c-test/echo.cpp
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/ADT/APIntTest.cpp
M llvm/unittests/ADT/BitsetTest.cpp
M llvm/unittests/Analysis/CFGTest.cpp
M llvm/unittests/BinaryFormat/MsgPackDocumentTest.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
A llvm/unittests/DebugInfo/PDB/TpiStreamTest.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/unittests/Support/ParallelTest.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-tidy/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/FrontendTool/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysisFramework/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysisFramework/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
M mlir/docs/Interfaces.md
M mlir/docs/Tools/mlir-reduce.md
A mlir/include/mlir/Bytecode/BytecodeDialectInterface.td
M mlir/include/mlir/Bytecode/BytecodeImplementation.h
M mlir/include/mlir/Bytecode/CMakeLists.txt
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRef.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/Dialect/SPIRV/IR/TargetAndABI.h
M mlir/include/mlir/Dialect/SparseTensor/Pipelines/Passes.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/IR/ExtensibleDialect.h
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/Interfaces/InferTypeOpInterface.td
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/CAPI/Interfaces/Interfaces.cpp
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/ConvertToEmitC/CMakeLists.txt
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/Math/Transforms/SincosFusion.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/WasmSSA/IR/WasmSSAOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/IR/ExtensibleDialect.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/Target/IRDLToCpp/Templates/PerOperationDecl.txt
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/CSE.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Conversion/SCFToSPIRV/for.mlir
M mlir/test/Conversion/SCFToSPIRV/while.mlir
M mlir/test/Dialect/Affine/scalrep.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
M mlir/test/Dialect/Math/sincos-fusion.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Dialect/Vector/vector-transfer-drop-unit-dims-patterns.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
M mlir/test/Dialect/XeGPU/peephole-optimize.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir
A mlir/test/Target/LLVMIR/openmp-simd-linear.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/CppGenUtilities.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
M mlir/unittests/Debug/FileLineColLocBreakpointManagerTest.cpp
M mlir/unittests/IR/AttributeTest.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M mlir/unittests/IR/VerifierTest.cpp
M mlir/unittests/Interfaces/MemorySlotUtilsTest.cpp
M mlir/unittests/Transforms/DialectConversion.cpp
M offload/include/Shared/RefCnt.h
M offload/liboffload/API/Event.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa_ext_amd.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/test/CMakeLists.txt
M offload/test/offloading/target_critical_region.cpp
M offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/event/olGetEventElapsedTime.cpp
M openmp/cmake/modules/LibompUtils.cmake
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/LibompGetArchitecture.cmake
A openmp/runtime/cmake/arm64x.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_atomic.cpp
A openmp/runtime/src/kmp_invoke_microtask.cpp
M openmp/runtime/src/kmp_os.h
M openmp/runtime/src/kmp_platform.h
M openmp/runtime/src/kmp_runtime.cpp
M openmp/runtime/src/thirdparty/ittnotify/ittnotify_config.h
M openmp/runtime/src/z_Linux_asm.S
M openmp/runtime/src/z_Linux_util.cpp
M openmp/runtime/src/z_Windows_NT-586_util.cpp
M openmp/runtime/test/misc_bugs/many-microtask-args.c
M polly/include/polly/CodeGen/IslNodeBuilder.h
M polly/include/polly/CodeGen/RuntimeDebugBuilder.h
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/test/CodeGen/RuntimeDebugBuilder/stmt_tracing.ll
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
Merge commit '803d1d66094c9d2e543f5e62a426ef972e100a93' into HEAD
Commit: 2bec75c4d6d1bcd369c16055402959636e241336
https://github.com/llvm/llvm-project/commit/2bec75c4d6d1bcd369c16055402959636e241336
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-04-02 (Thu, 02 Apr 2026)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LivenessAnalysis.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/runtime/instr.cpp
M bolt/runtime/sys_riscv64.h
M bolt/test/AArch64/compare-and-branch-inversion.S
M bolt/test/AArch64/compare-and-branch-reorder-blocks.S
M bolt/test/AArch64/compare-and-branch-split-functions.S
M bolt/test/AArch64/compare-and-branch-unsupported.S
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/unittests/Passes/CMakeLists.txt
A bolt/unittests/Passes/LivenessAnalysis.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang-tools-extra/unittests/clang-tidy/CMakeLists.txt
R clang-tools-extra/unittests/clang-tidy/ObjCModuleTest.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclContextInternals.h
M clang/include/clang/Basic/BuiltinsLoongArchLASX.def
M clang/include/clang/Basic/BuiltinsLoongArchLSX.def
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticCrossTUKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/OffloadArch.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/include/clang/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.h
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/CrossTU/CrossTranslationUnit.h
M clang/include/clang/Driver/SyclInstallationDetector.h
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Frontend/FrontendActions.h
A clang/include/clang/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphSummary.h
M clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
M clang/include/clang/Serialization/ModuleCache.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/CodeGen/TargetInfo.cpp
M clang/lib/CIR/Dialect/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
A clang/lib/CIR/Dialect/OpenMP/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.cpp
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h
A clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/DependencyScanning/InProcessModuleCache.cpp
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/ModulesDriver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/SYCL.cpp
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/FrontendTool/CMakeLists.txt
M clang/lib/Lex/TokenLexer.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractor.cpp
A clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphJSONFormat.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ModuleCache.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/cxx26.cpp
A clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/invalid-direct-callee-element.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/invalid-direct-callee-id.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-col.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-file.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def-line.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-def.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-direct-callees.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-pretty-name.json
A clang/test/Analysis/Scalable/ssaf-format/Inputs/CallGraph/missing-virtual-callees.json
A clang/test/Analysis/Scalable/ssaf-format/call-graph-invalid-json-format.test
M clang/test/Analysis/Scalable/ssaf-format/list.test
A clang/test/Analysis/ctu/diag/Inputs/third.cpp
M clang/test/Analysis/ctu/diag/invlist-ambiguous.cpp
M clang/test/Analysis/ctu/diag/invlist-empty.cpp
M clang/test/Analysis/ctu/diag/invlist-lookup-miss.cpp
M clang/test/Analysis/ctu/diag/invlist-missing.cpp
A clang/test/Analysis/ctu/diag/invlist-wrong-format-late.cpp
M clang/test/Analysis/ctu/diag/invlist-wrong-format.cpp
M clang/test/Analysis/ctu/diag/lang-dialect-mismatch.cpp
M clang/test/Analysis/ctu/diag/lang-mismatch.c
M clang/test/Analysis/ctu/diag/load-threshold.cpp
M clang/test/Analysis/ctu/import-type-decl-definition.c
M clang/test/Analysis/ctu/invalid-ast.cpp
M clang/test/Analysis/ctu/main.c
M clang/test/Analysis/ctu/missing-ast.cpp
M clang/test/Analysis/ctu/on-demand-parsing.c
M clang/test/Analysis/ctu/test-import-failure.cpp
A clang/test/CIR/CodeGen/amdgpu-address-spaces.cpp
A clang/test/CIR/CodeGen/amdgpu-target-lowering-as.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
A clang/test/CIR/CodeGen/copy-constructor-memcpy.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
M clang/test/CIR/CodeGen/cxx-special-member-attr.cpp
A clang/test/CIR/CodeGen/delegating-ctor-exceptions.cpp
A clang/test/CIR/CodeGen/global-section.c
M clang/test/CIR/CodeGen/nonzeroinit-struct.cpp
M clang/test/CIR/CodeGen/nrvo.cpp
A clang/test/CIR/CodeGen/return-in-if-with-cleanups.cpp
M clang/test/CIR/CodeGen/throws.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
A clang/test/CIR/CodeGenOpenMP/omp-module-attrs.c
A clang/test/CIR/IR/string-trailing-zeros.cir
R clang/test/CIR/Lowering/global-address-space.cir
A clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
A clang/test/CIR/Transforms/omp-mark-declare-target.cir
A clang/test/CodeGen/LoongArch/lasx/lasxintrin-lax-vector-conversions.c
A clang/test/CodeGen/LoongArch/lsx/lsxintrin-lax-vector-conversions.c
A clang/test/CodeGen/async-exceptions.c
A clang/test/CodeGen/tbaa-matrix.c
A clang/test/CodeGen/ubsan-aggregate-null-align.c
M clang/test/CodeGenCUDA/fp-contract.cu
A clang/test/CodeGenCXX/dead-on-return-deleting-destructor.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/ptrauth-apple-kext-indirect-virtual-dtor-call.cpp
M clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp
A clang/test/CodeGenHLSL/debug/source-language.hlsl
M clang/test/CodeGenObjC/constant-string-class-1.m
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
A clang/test/Driver/Inputs/SYCL/libLLVMSYCL.ll
R clang/test/Driver/Inputs/SYCL/libsycl.ll
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Driver/link-device-code.test
M clang/test/Driver/linux-ld.c
M clang/test/Driver/sycl-offload-jit.cpp
M clang/test/Lexer/gnu-flags.c
A clang/test/Lexer/gnu-zero-variadic-macro-argument-fixit.c
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
A clang/test/Modules/include-between-imports-enums.cppm
A clang/test/Modules/pr189415.cppm
A clang/test/Parser/decltype-gh188014.cpp
M clang/test/Preprocessor/macro_fn.c
R clang/test/Sema/gh183974.c
M clang/test/SemaCXX/using-if-exists.cpp
M clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
A clang/test/SemaTemplate/GH188759.cpp
M clang/tools/cir-opt/CMakeLists.txt
M clang/tools/cir-opt/cir-opt.cpp
M clang/tools/cir-translate/CMakeLists.txt
M clang/tools/cir-translate/cir-translate.cpp
M clang/tools/clang-ssaf-format/CMakeLists.txt
M clang/tools/clang-ssaf-linker/CMakeLists.txt
M clang/unittests/CrossTU/CrossTranslationUnitTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
A clang/unittests/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/CMakeLists.txt
M clang/unittests/ScalableStaticAnalysisFramework/Registries/SummaryExtractorRegistryTest.cpp
M clang/utils/TableGen/CIRLoweringEmitter.cpp
M compiler-rt/cmake/Modules/CheckAssemblerFlag.cmake
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_errors.cpp
M compiler-rt/lib/asan/asan_errors.h
M compiler-rt/lib/asan/asan_flags.inc
M compiler-rt/lib/asan/asan_report.cpp
M compiler-rt/lib/asan/asan_report.h
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/arm/adddf3.S
M compiler-rt/lib/builtins/int_math.h
M compiler-rt/lib/builtins/muldc3.c
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/test/CMakeLists.txt
A compiler-rt/test/asan/TestCases/Linux/free_aligned_sized_mismatch.cpp
A compiler-rt/test/asan/TestCases/Linux/free_sized_mismatch.cpp
A compiler-rt/test/builtins/Unit/adddf3new_test.c
A compiler-rt/test/builtins/Unit/subdf3new_test.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/soft_rss_limit_mb_test.cpp
M cross-project-tests/debuginfo-tests/dexter-tests/nrvo.cpp
M cross-project-tests/lit.cfg.py
M flang-rt/lib/cuda/registration.cpp
M flang/docs/C++style.md
M flang/docs/Extensions.md
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCUtils.h
M flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/lib/Semantics/check-omp-atomic.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-utils.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-acc.mlir
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-device-address.mlir
A flang/test/HLFIR/bufferize-associate-block-ordering.fir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
A flang/test/Lower/HLFIR/elemental-character-min-max.f90
M flang/test/Lower/Intrinsics/same_type_as.f90
M flang/test/Lower/Intrinsics/scan.f90
M flang/test/Lower/Intrinsics/secnds.f90
M flang/test/Lower/Intrinsics/selected_int_kind.f90
M flang/test/Lower/Intrinsics/selected_real_kind.f90
R flang/test/Lower/OpenMP/Todo/depend-clause.f90
M flang/test/Lower/OpenMP/composite_simd_linear.f90
A flang/test/Lower/OpenMP/depend-iterator.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/linear_modifier.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
A flang/test/Lower/OpenMP/requires-usm.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
M flang/test/Transforms/FIRToMemRef/array-coor-slice-shift.mlir
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/config.json
M libc/config/gpu/amdgpu/entrypoints.txt
M libc/config/gpu/amdgpu/headers.txt
M libc/config/gpu/nvptx/entrypoints.txt
M libc/config/gpu/nvptx/headers.txt
A libc/config/linux/power/config.json
A libc/config/linux/power/entrypoints.txt
A libc/config/linux/power/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/siginfo_t.h
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/include/llvm-libc-types/pthread_rwlock_t.h
A libc/shared/CMakeLists.txt
M libc/src/__support/CMakeLists.txt
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/raise.h
M libc/src/__support/math/log1pf.h
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
R libc/src/__support/threads/linux/rwlock.h
A libc/src/__support/threads/raw_rwlock.h
A libc/src/__support/threads/unix_rwlock.h
M libc/src/__support/time/CMakeLists.txt
M libc/src/assert/gpu/__assert_fail.cpp
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_rwlock_clockrdlock.cpp
M libc/src/pthread/pthread_rwlock_clockwrlock.cpp
M libc/src/pthread/pthread_rwlock_destroy.cpp
M libc/src/pthread/pthread_rwlock_init.cpp
M libc/src/pthread/pthread_rwlock_rdlock.cpp
M libc/src/pthread/pthread_rwlock_timedrdlock.cpp
M libc/src/pthread/pthread_rwlock_timedwrlock.cpp
M libc/src/pthread/pthread_rwlock_tryrdlock.cpp
M libc/src/pthread/pthread_rwlock_trywrlock.cpp
M libc/src/pthread/pthread_rwlock_unlock.cpp
M libc/src/pthread/pthread_rwlock_wrlock.cpp
M libc/src/setjmp/aarch64/CMakeLists.txt
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/raise.cpp
M libc/src/signal/linux/sigaction.cpp
M libc/src/signal/linux/signal_utils.h
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/scanf_core/CMakeLists.txt
M libc/src/time/linux/CMakeLists.txt
M libc/src/unistd/CMakeLists.txt
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/TestLogger.cpp
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_rwlock_test.cpp
M libc/test/shared/shared_math_test.cpp
M libc/test/src/__support/threads/linux/CMakeLists.txt
A libc/test/src/__support/threads/linux/raw_rwlock_test.cpp
M libc/test/src/math/CMakeLists.txt
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdlib/CMakeLists.txt
M libcxx/docs/ReleaseNotes/23.rst
R libcxx/test/libcxx/diagnostics/ranges.nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.utility/range.utility.conv/nodiscard.verify.cpp
M libsycl/docs/index.rst
M libsycl/src/CMakeLists.txt
A libsycl/src/detail/device_binary_structures.hpp
A libsycl/src/detail/device_image_wrapper.hpp
M libsycl/src/detail/device_impl.hpp
M libsycl/src/detail/global_objects.cpp
M libsycl/src/detail/global_objects.hpp
A libsycl/src/detail/kernel_id.hpp
A libsycl/src/detail/program_manager.cpp
A libsycl/src/detail/program_manager.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/usm_functions.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/BPSectionOrderer.cpp
M lld/ELF/BPSectionOrderer.h
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/InputSection.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/Options.td
M lld/ELF/Symbols.h
M lld/ELF/Writer.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/BPSectionOrderer.h
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/SectionPriorities.cpp
M lld/docs/ReleaseNotes.rst
A lld/include/lld/Common/BPSectionOrdererBase.h
M lld/include/lld/Common/BPSectionOrdererBase.inc
A lld/test/ELF/arm-be8-data-mapsym.s
A lld/test/ELF/bp-section-orderer-cold.s
M lld/test/ELF/bp-section-orderer.s
M lld/test/ELF/merge-piece-oob.s
M lld/test/MachO/bp-section-orderer-errs.s
A lld/test/MachO/compression-order-sections.s
M lldb/docs/use/aarch64-linux.md
M lldb/examples/python/formatter_bytecode.py
M lldb/include/lldb/Host/FileAction.h
M lldb/include/lldb/Host/ProcessLaunchInfo.h
A lldb/include/lldb/Host/windows/WindowsFileAction.h
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/include/lldb/Target/Platform.h
M lldb/include/lldb/Target/StackFrame.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/include/lldb/lldb-private-enumerations.h
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Commands/CommandObjectMemory.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Expression/IRMemoryMap.cpp
M lldb/source/Host/CMakeLists.txt
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
A lldb/source/Host/windows/WindowsFileAction.cpp
M lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
M lldb/source/Plugins/Process/NetBSD/NativeProcessNetBSD.cpp
M lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
M lldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Target/MemoryRegionInfo.cpp
M lldb/source/Target/Platform.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/source/ValueObject/ValueObject.cpp
A lldb/test/API/commands/register/TestRegistersUnavailable.py
A lldb/test/API/commands/register/aarch64_dynamic_regset/Makefile
A lldb/test/API/commands/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
A lldb/test/API/commands/register/aarch64_dynamic_regset/main.c
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/Makefile
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
A lldb/test/API/commands/register/aarch64_mte_ctrl_register/main.c
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/Makefile
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/TestSMEZRegistersSaveRestore.py
A lldb/test/API/commands/register/aarch64_sme_z_registers/save_restore/main.c
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/Makefile
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/TestZAThreadedDynamic.py
A lldb/test/API/commands/register/aarch64_sme_z_registers/za_dynamic_resize/main.c
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/Makefile
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
A lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c
A lldb/test/API/commands/register/aarch64_sve_simd_registers/Makefile
A lldb/test/API/commands/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
A lldb/test/API/commands/register/aarch64_sve_simd_registers/main.c
R lldb/test/API/commands/register/register/TestRegistersUnavailable.py
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/Makefile
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
R lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/Makefile
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
R lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/main.c
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/Makefile
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/TestSMEZRegistersSaveRestore.py
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/main.c
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/Makefile
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/TestZAThreadedDynamic.py
R lldb/test/API/commands/register/register/aarch64_sme_z_registers/za_dynamic_resize/main.c
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
R lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/Makefile
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
R lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
R lldb/test/API/commands/register/register/register_command/Makefile
R lldb/test/API/commands/register/register/register_command/TestRegisters.py
R lldb/test/API/commands/register/register/register_command/a.cpp
R lldb/test/API/commands/register/register/register_command/main.cpp
A lldb/test/API/commands/register/register_command/Makefile
A lldb/test/API/commands/register/register_command/TestRegisters.py
A lldb/test/API/commands/register/register_command/a.cpp
A lldb/test/API/commands/register/register_command/main.cpp
M lldb/test/API/commands/target/create-deps/TestTargetCreateDeps.py
M lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/TestBreakInLoadedDylib.py
M lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
M lldb/test/API/functionalities/load_after_attach/TestLoadAfterAttach.py
M lldb/test/API/functionalities/load_lazy/TestLoadUsingLazyBind.py
M lldb/test/API/functionalities/load_unload/TestLoadUnload.py
A lldb/test/API/linux/aarch64/sme_only_registers/Makefile
A lldb/test/API/linux/aarch64/sme_only_registers/TestSMEOnlyRegisters.py
A lldb/test/API/linux/aarch64/sme_only_registers/main.c
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
M lldb/test/Shell/ScriptInterpreter/Python/python-bytecode.test
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/HostTest.cpp
M lldb/unittests/Platform/PlatformDarwinTest.cpp
M lldb/unittests/Platform/PlatformTest.cpp
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
M lldb/unittests/Target/MemoryRegionInfoTest.cpp
M llvm/CMakeLists.txt
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/SPIRVUsage.rst
M llvm/docs/SandboxVectorizer.md
M llvm/include/llvm/ADT/Bitset.h
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/Uniformity.h
M llvm/include/llvm/ADT/bit.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/MsgPackDocument.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
R llvm/include/llvm/CodeGen/ExpandMemCmp.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/DebugInfo/CodeView/LazyRandomTypeCollection.h
M llvm/include/llvm/DebugInfo/PDB/Native/TpiStream.h
M llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
A llvm/include/llvm/MC/MCAsmStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Support/Alignment.h
M llvm/include/llvm/Support/Parallel.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/Scalar.h
A llvm/include/llvm/Transforms/Scalar/ExpandMemCmp.h
A llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/BinaryFormat/MsgPackDocument.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
R llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/LowerEmuTLS.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/ProcessImplicitDefs.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/DebugInfo/CodeView/LazyRandomTypeCollection.cpp
M llvm/lib/DebugInfo/GSYM/FileWriter.cpp
M llvm/lib/DebugInfo/PDB/Native/TpiStream.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/LLVMContextImpl.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Support/APInt.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DataExtractor.cpp
M llvm/lib/Support/Parallel.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
A llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
M llvm/lib/Transforms/Scalar/LoopRotation.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/Scalar.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/PassRegistry.def
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizerPassBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/RISCV/extract-last-active.ll
M llvm/test/Analysis/DependenceAnalysis/PR188098.ll
M llvm/test/Analysis/DependenceAnalysis/exact-rdiv-delta-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-delta-signed-min.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-overflow.ll
M llvm/test/Analysis/LoopAccessAnalysis/invariant-dep-same-ptr.ll
M llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll
M llvm/test/CMakeLists.txt
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/aarch64-post-coalescer.mir
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
M llvm/test/CodeGen/AArch64/bcmp.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/ctlz.ll
M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/emutls.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
M llvm/test/CodeGen/AArch64/memcmp.ll
M llvm/test/CodeGen/AArch64/neon-abd.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/AArch64/sve-stepvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve2-bsl.ll
M llvm/test/CodeGen/AArch64/sve2-rsh.ll
M llvm/test/CodeGen/AArch64/sve2-xar.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
A llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-alloca-issue-155902.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
A llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
A llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
A llvm/test/CodeGen/ARM/emutls-alignment.ll
M llvm/test/CodeGen/BPF/memcmp.ll
R llvm/test/CodeGen/Generic/llc-start-stop.ll
M llvm/test/CodeGen/LoongArch/expandmemcmp-optsize.ll
M llvm/test/CodeGen/LoongArch/expandmemcmp.ll
M llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
M llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
M llvm/test/CodeGen/LoongArch/memcmp.ll
A llvm/test/CodeGen/LoongArch/mergestores.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/M68k/pipeline.ll
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-prio-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
M llvm/test/CodeGen/MLRegAlloc/dev-mode-prio-logging.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
M llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
M llvm/test/CodeGen/PowerPC/memcmp.ll
M llvm/test/CodeGen/PowerPC/memcmp32_fixsize.ll
M llvm/test/CodeGen/PowerPC/memcmp64_fixsize.ll
M llvm/test/CodeGen/PowerPC/memcmpIR.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
M llvm/test/CodeGen/PowerPC/vector-rotates.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
A llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir
M llvm/test/CodeGen/RISCV/pr186969.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
A llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
M llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi-multiple.mir
M llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
A llvm/test/CodeGen/SPIRV/debug-info/hlsl-debug-info-auto-activation.ll
A llvm/test/CodeGen/SPIRV/debug-info/no-nonsemantic-without-extension.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll
A llvm/test/CodeGen/SPIRV/function/variadics-lowering-builtin-substr-in-name.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/CalculateLevelOfDetail.ll
M llvm/test/CodeGen/SPIRV/hlsl-resources/SampleErrorsDebug.ll
M llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-kernel-pre16.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-non-extinst.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-infer-fnptr-todo-type.ll
M llvm/test/CodeGen/SPIRV/printf.ll
M llvm/test/CodeGen/SPIRV/spec_const_decoration.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
M llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
M llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
M llvm/test/CodeGen/WebAssembly/memcmp-expand.ll
M llvm/test/CodeGen/WebAssembly/simd-memcmp.ll
M llvm/test/CodeGen/WebAssembly/simd-setcc.ll
A llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
M llvm/test/CodeGen/X86/abds.ll
M llvm/test/CodeGen/X86/addcarry.ll
M llvm/test/CodeGen/X86/gfni-rotates.ll
M llvm/test/CodeGen/X86/issue76416.ll
A llvm/test/CodeGen/X86/known-fpclass.ll
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
A llvm/test/CodeGen/X86/llc-start-stop.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
M llvm/test/CodeGen/X86/memcmp-constant.ll
M llvm/test/CodeGen/X86/memcmp-mergeexpand.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
M llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
M llvm/test/CodeGen/X86/memcmp-optsize.ll
M llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
M llvm/test/CodeGen/X86/memcmp-pgso.ll
M llvm/test/CodeGen/X86/memcmp-x32.ll
M llvm/test/CodeGen/X86/memcmp.ll
A llvm/test/CodeGen/X86/multi-use-implicit-def.mir
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll
M llvm/test/CodeGen/X86/statepoint-two-results.ll
M llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
M llvm/test/CodeGen/X86/subcarry.ll
M llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
A llvm/test/DebugInfo/COFF/indirect-local.ll
M llvm/test/DebugInfo/COFF/nrvo.ll
M llvm/test/DebugInfo/COFF/pieces.ll
M llvm/test/DebugInfo/COFF/types-array-advanced.ll
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/MC/AArch64/armv8.9a-prfm-slc.s
M llvm/test/MC/AArch64/armv9.6a-pcdphint.s
M llvm/test/MC/AArch64/armv9a-tlbip.s
M llvm/test/MC/AArch64/basic-a64-instructions.s
M llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt
M llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/TableGen/intrinsic-arginfo-error.td
A llvm/test/TableGen/intrinsic-overload-dependent-type-validation.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll
M llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll
M llvm/test/Transforms/Coroutines/coro-await-suspend-lower.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-01.ll
M llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
A llvm/test/Transforms/ExpandMemCmp/X86/sanitizer-skip.ll
A llvm/test/Transforms/FunctionSpecialization/function-specialization-optsize.ll
A llvm/test/Transforms/InstCombine/printf-puts-not-emittable.ll
M llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll
M llvm/test/Transforms/LICM/hoist-binop.ll
M llvm/test/Transforms/LICM/preheader-safe.ll
M llvm/test/Transforms/LICM/read-only-calls.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
M llvm/test/Transforms/LoopRotate/oz-disable.ll
A llvm/test/Transforms/LoopUnroll/RISCV/runtime-unroll-max-trip-count.ll
M llvm/test/Transforms/LoopUnroll/debug.ll
M llvm/test/Transforms/LoopUnroll/runtime-small-upperbound.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/predicated-reverse-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
A llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
A llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
A llvm/test/Transforms/PhaseOrdering/X86/expand-memcmp-middle-end.ll
M llvm/test/Transforms/PhaseOrdering/enable-loop-header-duplication-oz.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
A llvm/test/Transforms/SLPVectorizer/X86/constant-based-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
M llvm/test/Transforms/SROA/vector-promotion-via-tree-structure-merge.ll
A llvm/test/Transforms/SampleProfile/pseudo-probe-emit-macho.ll
A llvm/test/Transforms/SandboxVectorizer/load_store_vec.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll
M llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll
M llvm/test/Transforms/WholeProgramDevirt/import.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected
M llvm/test/tools/llc/new-pm/option-conflict.ll
M llvm/test/tools/llc/new-pm/start-stop.ll
M llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/atomic.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/floating-point.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/integer.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/arithmetic.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/bitwise.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/comparison.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/conversion.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fma.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fp.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mask.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/minmax.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mul-div.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/permutation.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/reduction.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vle-vse-vlm.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlse-vsse.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlseg-vsseg.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlxe-vsxe.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbb.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbc.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkg.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkned.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvknhb.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksed.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksh.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zba.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbb.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbs.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfhmin.test
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
R llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llc/llc.cpp
M llvm/tools/llubi/lib/CMakeLists.txt
A llvm/tools/llubi/lib/ExecutorBase.cpp
A llvm/tools/llubi/lib/ExecutorBase.h
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llvm-c-test/echo.cpp
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/ADT/APIntTest.cpp
M llvm/unittests/ADT/BitsetTest.cpp
M llvm/unittests/Analysis/CFGTest.cpp
M llvm/unittests/BinaryFormat/MsgPackDocumentTest.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
A llvm/unittests/DebugInfo/PDB/TpiStreamTest.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/unittests/Support/ParallelTest.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-tidy/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/FrontendTool/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysisFramework/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysisFramework/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
M mlir/docs/Interfaces.md
M mlir/docs/Tools/mlir-reduce.md
A mlir/include/mlir/Bytecode/BytecodeDialectInterface.td
M mlir/include/mlir/Bytecode/BytecodeImplementation.h
M mlir/include/mlir/Bytecode/CMakeLists.txt
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRef.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/Dialect/SPIRV/IR/TargetAndABI.h
M mlir/include/mlir/Dialect/SparseTensor/Pipelines/Passes.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/IR/ExtensibleDialect.h
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/Interfaces/InferTypeOpInterface.td
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/CAPI/Interfaces/Interfaces.cpp
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/ConvertToEmitC/CMakeLists.txt
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/Math/Transforms/SincosFusion.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/WasmSSA/IR/WasmSSAOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/IR/ExtensibleDialect.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/Target/IRDLToCpp/Templates/PerOperationDecl.txt
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/CSE.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Conversion/SCFToSPIRV/for.mlir
M mlir/test/Conversion/SCFToSPIRV/while.mlir
M mlir/test/Dialect/Affine/scalrep.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
M mlir/test/Dialect/Math/sincos-fusion.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Dialect/Vector/vector-transfer-drop-unit-dims-patterns.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
M mlir/test/Dialect/XeGPU/peephole-optimize.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir
A mlir/test/Target/LLVMIR/openmp-simd-linear.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/CppGenUtilities.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
M mlir/unittests/Debug/FileLineColLocBreakpointManagerTest.cpp
M mlir/unittests/IR/AttributeTest.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M mlir/unittests/IR/VerifierTest.cpp
M mlir/unittests/Interfaces/MemorySlotUtilsTest.cpp
M mlir/unittests/Transforms/DialectConversion.cpp
M offload/include/Shared/RefCnt.h
M offload/liboffload/API/Event.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa_ext_amd.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/test/CMakeLists.txt
M offload/test/offloading/target_critical_region.cpp
M offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/event/olGetEventElapsedTime.cpp
M openmp/cmake/modules/LibompUtils.cmake
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/LibompGetArchitecture.cmake
A openmp/runtime/cmake/arm64x.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_atomic.cpp
A openmp/runtime/src/kmp_invoke_microtask.cpp
M openmp/runtime/src/kmp_os.h
M openmp/runtime/src/kmp_platform.h
M openmp/runtime/src/kmp_runtime.cpp
M openmp/runtime/src/thirdparty/ittnotify/ittnotify_config.h
M openmp/runtime/src/z_Linux_asm.S
M openmp/runtime/src/z_Linux_util.cpp
M openmp/runtime/src/z_Windows_NT-586_util.cpp
M openmp/runtime/test/misc_bugs/many-microtask-args.c
M polly/include/polly/CodeGen/IslNodeBuilder.h
M polly/include/polly/CodeGen/RuntimeDebugBuilder.h
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/test/CodeGen/RuntimeDebugBuilder/stmt_tracing.ll
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
Merge commit '7389131f6843fd6110f98e1d102387fb576ff2ef' into HEAD
Compare: https://github.com/llvm/llvm-project/compare/7c4e03a06bcf...2bec75c4d6d1
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