[all-commits] [llvm/llvm-project] b9e01c: [RISCV] Relax VL constraint in convertSameMaskVMer...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b9e01c26f0bb754307d12c19b957be576ff422a8
      https://github.com/llvm/llvm-project/commit/b9e01c26f0bb754307d12c19b957be576ff422a8
  Author: Jim Lin <jim at andestech.com>
  Date:   2026-04-02 (Thu, 02 Apr 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir

  Log Message:
  -----------
  [RISCV] Relax VL constraint in convertSameMaskVMergeToVMv (#189797)

When converting a PseudoVMERGE_VVM to PseudoVMV_V_V, we previously
required MIVL <= TrueVL to avoid losing False elements in the tail.

Relax this constraint when the vmerge's False operand equals its
Passthru operand and the True instruction's tail policy is TU
(tail undisturbed). In this case, True's tail lanes preserve its
passthru value (which equals False and Passthru), so the conversion
is safe even when MIVL > TrueVL.

---------

Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>



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