[all-commits] [llvm/llvm-project] 7d24b1: [RISCV] Add SATI_RV64/USATI_RV64 to RISCVOptWInstr...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7d24b175ebe20b427dddbee5bf0e77bd7d0657f6
      https://github.com/llvm/llvm-project/commit/7d24b175ebe20b427dddbee5bf0e77bd7d0657f6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-04-01 (Wed, 01 Apr 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    M llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir

  Log Message:
  -----------
  [RISCV] Add SATI_RV64/USATI_RV64 to RISCVOptWInstrs. (#190030)

Note the immediates for these 2 instructions in their MachineInstr
representations both use the type width. The SATI_RV64 binary encoding
and the RISCVISD::SATI encoding uses the type width minus one.

Assisted-by: Claude Sonnet 4.5



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